Index: binutils-2.16.1-avr32/bfd/elf-bfd.h =================================================================== --- binutils-2.16.1-avr32.orig/bfd/elf-bfd.h 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/bfd/elf-bfd.h 2006-06-30 09:49:14.000000000 +0200 @@ -1251,6 +1251,10 @@ struct elf_obj_tdata find_nearest_line. */ struct mips_elf_find_line *find_line_info; + /* Used by AVR32 ELF relaxation code. Contains an array of pointers + for each local symbol to the fragment where it is defined. */ + struct fragment **local_sym_frag; + /* A place to stash dwarf1 info for this bfd. */ struct dwarf1_debug *dwarf1_find_line_info; Index: binutils-2.16.1-avr32/gas/write.c =================================================================== --- binutils-2.16.1-avr32.orig/gas/write.c 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/gas/write.c 2006-06-30 09:49:14.000000000 +0200 @@ -159,7 +159,9 @@ static fixS *fix_new_internal (fragS *, #if defined (BFD_ASSEMBLER) || (!defined (BFD) && !defined (OBJ_VMS)) static long fixup_segment (fixS *, segT); #endif +#if !defined (TC_RELAX_ALIGN) static relax_addressT relax_align (relax_addressT addr, int align); +#endif #if defined (BFD_ASSEMBLER) || ! defined (BFD) static fragS *chain_frchains_together_1 (segT, struct frchain *); #endif @@ -2136,6 +2138,10 @@ relax_frag (segT segment, fragS *fragP, #endif /* defined (TC_GENERIC_RELAX_TABLE) */ +#ifdef TC_RELAX_ALIGN +#define RELAX_ALIGN(SEG, FRAG, ADDR) TC_RELAX_ALIGN(SEG, FRAG, ADDR) +#else +#define RELAX_ALIGN(SEG, FRAG, ADDR) relax_align(ADDR, (FRAG)->fr_offset) /* Relax_align. Advance location counter to next address that has 'alignment' lowest order bits all 0s, return size of adjustment made. */ static relax_addressT @@ -2155,6 +2161,7 @@ relax_align (register relax_addressT add #endif return (new_address - address); } +#endif /* Now we have a segment, not a crowd of sub-segments, we can make fr_address values. @@ -2198,7 +2205,7 @@ relax_segment (struct frag *segment_frag case rs_align_code: case rs_align_test: { - addressT offset = relax_align (address, (int) fragP->fr_offset); + addressT offset = RELAX_ALIGN(segment, fragP, address); if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype) offset = 0; @@ -2358,10 +2365,10 @@ relax_segment (struct frag *segment_frag { addressT oldoff, newoff; - oldoff = relax_align (was_address + fragP->fr_fix, - (int) offset); - newoff = relax_align (address + fragP->fr_fix, - (int) offset); + oldoff = RELAX_ALIGN (segment, fragP, + was_address + fragP->fr_fix); + newoff = RELAX_ALIGN (segment, fragP, + address + fragP->fr_fix); if (fragP->fr_subtype != 0) { Index: binutils-2.16.1-avr32/bfd/Makefile.am =================================================================== --- binutils-2.16.1-avr32.orig/bfd/Makefile.am 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/bfd/Makefile.am 2006-06-30 09:49:14.000000000 +0200 @@ -58,6 +58,7 @@ ALL_MACHINES = \ cpu-arc.lo \ cpu-arm.lo \ cpu-avr.lo \ + cpu-avr32.lo \ cpu-cr16c.lo \ cpu-cris.lo \ cpu-crx.lo \ @@ -222,6 +223,7 @@ BFD32_BACKENDS = \ elf32-arc.lo \ elf32-arm.lo \ elf32-avr.lo \ + elf32-avr32.lo \ elf32-cr16c.lo \ elf32-cris.lo \ elf32-crx.lo \ @@ -1169,6 +1171,10 @@ elf32-avr.lo: elf32-avr.c $(INCDIR)/file $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h $(INCDIR)/elf/avr.h $(INCDIR)/elf/reloc-macros.h \ elf32-target.h +elf32-avr32.lo: elf32-avr32.c $(INCDIR)/filenames.h elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/avr32.h $(INCDIR)/elf/reloc-macros.h \ + elf32-target.h elf32-cr16c.lo: elf32-cr16c.c $(INCDIR)/filenames.h \ $(INCDIR)/bfdlink.h $(INCDIR)/elf/cr16c.h $(INCDIR)/elf/reloc-macros.h \ elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ Index: binutils-2.16.1-avr32/bfd/archures.c =================================================================== --- binutils-2.16.1-avr32.orig/bfd/archures.c 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/bfd/archures.c 2006-07-06 13:03:09.000000000 +0200 @@ -323,6 +323,8 @@ DESCRIPTION .#define bfd_mach_avr3 3 .#define bfd_mach_avr4 4 .#define bfd_mach_avr5 5 +. bfd_arch_avr32, {* Atmel AVR32 *} +.#define bfd_mach_at32ap7000 7000 . bfd_arch_cr16c, {* National Semiconductor CompactRISC. *} .#define bfd_mach_cr16c 1 . bfd_arch_crx, {* National Semiconductor CRX. *} @@ -401,6 +403,7 @@ extern const bfd_arch_info_type bfd_alph extern const bfd_arch_info_type bfd_arc_arch; extern const bfd_arch_info_type bfd_arm_arch; extern const bfd_arch_info_type bfd_avr_arch; +extern const bfd_arch_info_type bfd_avr32_arch; extern const bfd_arch_info_type bfd_cr16c_arch; extern const bfd_arch_info_type bfd_cris_arch; extern const bfd_arch_info_type bfd_crx_arch; @@ -464,6 +467,7 @@ static const bfd_arch_info_type * const &bfd_arc_arch, &bfd_arm_arch, &bfd_avr_arch, + &bfd_avr32_arch, &bfd_cr16c_arch, &bfd_cris_arch, &bfd_crx_arch, Index: binutils-2.16.1-avr32/bfd/config.bfd =================================================================== --- binutils-2.16.1-avr32.orig/bfd/config.bfd 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/bfd/config.bfd 2006-06-30 09:49:14.000000000 +0200 @@ -307,6 +307,10 @@ case "${targ}" in targ_defvec=bfd_elf32_avr_vec ;; + avr32-*-*) + targ_defvec=bfd_elf32_avr32_vec + ;; + c30-*-*aout* | tic30-*-*aout*) targ_defvec=tic30_aout_vec ;; Index: binutils-2.16.1-avr32/bfd/configure.in =================================================================== --- binutils-2.16.1-avr32.orig/bfd/configure.in 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/bfd/configure.in 2006-06-30 09:49:14.000000000 +0200 @@ -579,6 +579,7 @@ do bfd_efi_app_ia64_vec) tb="$tb efi-app-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;; bfd_elf32_am33lin_vec) tb="$tb elf32-am33lin.lo elf32.lo $elf" ;; bfd_elf32_avr_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;; + bfd_elf32_avr32_vec) tb="$tb elf32-avr32.lo elf32.lo $elf" ;; bfd_elf32_big_generic_vec) tb="$tb elf32-gen.lo elf32.lo $elf" ;; bfd_elf32_bigarc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;; bfd_elf32_bigarm_vec) tb="$tb elf32-arm.lo elf32.lo $elf" ;; Index: binutils-2.16.1-avr32/bfd/cpu-avr32.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/bfd/cpu-avr32.c 2006-07-06 13:03:09.000000000 +0200 @@ -0,0 +1,39 @@ +/* BFD library support routines for AVR32. + Copyright 2003-2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_avr32_arch = { + 32, /* 32 bits in a word */ + 32, /* 32 bits in an address */ + 8, /* 8 bits in a byte */ + bfd_arch_avr32, /* architecture */ + bfd_mach_at32ap7000, /* machine */ + "avr32", /* arch name */ + "avr32:at32ap7000", /* printable name */ + 1, /* 16 bit alignment of sections (?) */ + TRUE, /* This is the default machine */ + bfd_default_compatible, + bfd_default_scan, + 0 /* Next */ +}; Index: binutils-2.16.1-avr32/bfd/elf32-avr32.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/bfd/elf32-avr32.c 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,3818 @@ +/* AVR32-specific support for 32-bit ELF. + Copyright 2003-2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "bfdlink.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/avr32.h" + +#define xDEBUG +#define xRELAX_DEBUG + +#ifdef DEBUG +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args) +#else +# define pr_debug(fmt, args...) do { } while (0) +#endif + +#ifdef RELAX_DEBUG +# define RDBG(fmt, args...) fprintf(stderr, fmt, ##args) +#else +# define RDBG(fmt, args...) do { } while (0) +#endif + +/* When things go wrong, we want it to blow up, damnit! */ +#undef BFD_ASSERT +#undef abort +#define BFD_ASSERT(expr) \ + do \ + { \ + if (!(expr)) \ + { \ + bfd_assert(__FILE__, __LINE__); \ + abort(); \ + } \ + } \ + while (0) + +/* The name of the dynamic interpreter. This is put in the .interp section. */ +#define ELF_DYNAMIC_INTERPRETER "/lib/ld.so.1" + +#define AVR32_GOT_HEADER_SIZE 8 +#define AVR32_FUNCTION_STUB_SIZE 8 + +#define ELF_R_INFO(x, y) ELF32_R_INFO(x, y) +#define ELF_R_TYPE(x) ELF32_R_TYPE(x) +#define ELF_R_SYM(x) ELF32_R_SYM(x) + +#define NOP_OPCODE 0xd703 + + +/* Mapping between BFD relocations and ELF relocations */ + +static reloc_howto_type * +bfd_elf32_bfd_reloc_type_lookup(bfd *abfd, bfd_reloc_code_real_type code); +static void +avr32_info_to_howto (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst); + +/* Generic HOWTO */ +#define GENH(name, align, size, bitsize, pcrel, bitpos, complain, mask) \ + HOWTO(name, align, size, bitsize, pcrel, bitpos, \ + complain_overflow_##complain, bfd_elf_generic_reloc, #name, \ + FALSE, 0, mask, pcrel) + +static reloc_howto_type elf_avr32_howto_table[] = { + /* NAME ALN SZ BSZ PCREL BP COMPLAIN MASK */ + GENH(R_AVR32_NONE, 0, 0, 0, FALSE, 0, dont, 0x00000000), + + GENH(R_AVR32_32, 0, 2, 32, FALSE, 0, dont, 0xffffffff), + GENH(R_AVR32_16, 0, 1, 16, FALSE, 0, bitfield, 0x0000ffff), + GENH(R_AVR32_8, 0, 0, 8, FALSE, 0, bitfield, 0x000000ff), + GENH(R_AVR32_32_PCREL, 0, 2, 32, TRUE, 0, signed, 0xffffffff), + GENH(R_AVR32_16_PCREL, 0, 1, 16, TRUE, 0, signed, 0x0000ffff), + GENH(R_AVR32_8_PCREL, 0, 0, 8, TRUE, 0, signed, 0x000000ff), + + /* Difference between two symbol (sym2 - sym1). The reloc encodes + the value of sym1. The field contains the difference before any + relaxing is done. */ + GENH(R_AVR32_DIFF32, 0, 2, 32, FALSE, 0, dont, 0xffffffff), + GENH(R_AVR32_DIFF16, 0, 1, 16, FALSE, 0, signed, 0x0000ffff), + GENH(R_AVR32_DIFF8, 0, 0, 8, FALSE, 0, signed, 0x000000ff), + + GENH(R_AVR32_GOT32, 0, 2, 32, FALSE, 0, signed, 0xffffffff), + GENH(R_AVR32_GOT16, 0, 1, 16, FALSE, 0, signed, 0x0000ffff), + GENH(R_AVR32_GOT8, 0, 0, 8, FALSE, 0, signed, 0x000000ff), + + GENH(R_AVR32_21S, 0, 2, 21, FALSE, 0, signed, 0x1e10ffff), + GENH(R_AVR32_16U, 0, 2, 16, FALSE, 0, unsigned, 0x0000ffff), + GENH(R_AVR32_16S, 0, 2, 16, FALSE, 0, signed, 0x0000ffff), + GENH(R_AVR32_8S, 0, 1, 8, FALSE, 4, signed, 0x00000ff0), + GENH(R_AVR32_8S_EXT, 0, 2, 8, FALSE, 0, signed, 0x000000ff), + + GENH(R_AVR32_22H_PCREL, 1, 2, 21, TRUE, 0, signed, 0x1e10ffff), + GENH(R_AVR32_18W_PCREL, 2, 2, 16, TRUE, 0, signed, 0x0000ffff), + GENH(R_AVR32_16B_PCREL, 0, 2, 16, TRUE, 0, signed, 0x0000ffff), + GENH(R_AVR32_16N_PCREL, 0, 2, 16, TRUE, 0, signed, 0x0000ffff), + GENH(R_AVR32_14UW_PCREL, 2, 2, 12, TRUE, 0, unsigned, 0x0000f0ff), + GENH(R_AVR32_11H_PCREL, 1, 1, 10, TRUE, 4, signed, 0x00000ff3), + GENH(R_AVR32_10UW_PCREL, 2, 2, 8, TRUE, 0, unsigned, 0x000000ff), + GENH(R_AVR32_9H_PCREL, 1, 1, 8, TRUE, 4, signed, 0x00000ff0), + GENH(R_AVR32_9UW_PCREL, 2, 1, 7, TRUE, 4, unsigned, 0x000007f0), + + GENH(R_AVR32_HI16, 16, 2, 16, FALSE, 0, dont, 0x0000ffff), + GENH(R_AVR32_LO16, 0, 2, 16, FALSE, 0, dont, 0x0000ffff), + + GENH(R_AVR32_GOTPC, 0, 2, 32, FALSE, 0, dont, 0xffffffff), + GENH(R_AVR32_GOTCALL, 2, 2, 21, FALSE, 0, signed, 0x1e10ffff), + GENH(R_AVR32_LDA_GOT, 2, 2, 21, FALSE, 0, signed, 0x1e10ffff), + GENH(R_AVR32_GOT21S, 0, 2, 21, FALSE, 0, signed, 0x1e10ffff), + GENH(R_AVR32_GOT18SW, 2, 2, 16, FALSE, 0, signed, 0x0000ffff), + GENH(R_AVR32_GOT16S, 0, 2, 16, FALSE, 0, signed, 0x0000ffff), + GENH(R_AVR32_GOT7UW, 2, 1, 5, FALSE, 4, unsigned, 0x000001f0), + + GENH(R_AVR32_32_CPENT, 0, 2, 32, FALSE, 0, dont, 0xffffffff), + GENH(R_AVR32_CPCALL, 2, 2, 16, TRUE, 0, signed, 0x0000ffff), + GENH(R_AVR32_16_CP, 0, 2, 16, TRUE, 0, signed, 0x0000ffff), + GENH(R_AVR32_9W_CP, 2, 1, 7, TRUE, 4, unsigned, 0x000007f0), + + GENH(R_AVR32_RELATIVE, 0, 2, 32, FALSE, 0, signed, 0xffffffff), + GENH(R_AVR32_GLOB_DAT, 0, 2, 32, FALSE, 0, dont, 0xffffffff), + GENH(R_AVR32_JMP_SLOT, 0, 2, 32, FALSE, 0, dont, 0xffffffff), + + GENH(R_AVR32_ALIGN, 0, 1, 0, FALSE, 0, unsigned, 0x00000000), +}; + +struct elf_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned char elf_reloc_val; +}; + +static const struct elf_reloc_map avr32_reloc_map[] = +{ + { BFD_RELOC_NONE, R_AVR32_NONE }, + + { BFD_RELOC_32, R_AVR32_32 }, + { BFD_RELOC_16, R_AVR32_16 }, + { BFD_RELOC_8, R_AVR32_8 }, + { BFD_RELOC_32_PCREL, R_AVR32_32_PCREL }, + { BFD_RELOC_16_PCREL, R_AVR32_16_PCREL }, + { BFD_RELOC_8_PCREL, R_AVR32_8_PCREL }, + { BFD_RELOC_AVR32_DIFF32, R_AVR32_DIFF32 }, + { BFD_RELOC_AVR32_DIFF16, R_AVR32_DIFF16 }, + { BFD_RELOC_AVR32_DIFF8, R_AVR32_DIFF8 }, + { BFD_RELOC_AVR32_GOT32, R_AVR32_GOT32 }, + { BFD_RELOC_AVR32_GOT16, R_AVR32_GOT16 }, + { BFD_RELOC_AVR32_GOT8, R_AVR32_GOT8 }, + + { BFD_RELOC_AVR32_21S, R_AVR32_21S }, + { BFD_RELOC_AVR32_16U, R_AVR32_16U }, + { BFD_RELOC_AVR32_16S, R_AVR32_16S }, + { BFD_RELOC_AVR32_SUB5, R_AVR32_16S }, + { BFD_RELOC_AVR32_8S_EXT, R_AVR32_8S_EXT }, + { BFD_RELOC_AVR32_8S, R_AVR32_8S }, + + { BFD_RELOC_AVR32_22H_PCREL, R_AVR32_22H_PCREL }, + { BFD_RELOC_AVR32_18W_PCREL, R_AVR32_18W_PCREL }, + { BFD_RELOC_AVR32_16B_PCREL, R_AVR32_16B_PCREL }, + { BFD_RELOC_AVR32_16N_PCREL, R_AVR32_16N_PCREL }, + { BFD_RELOC_AVR32_11H_PCREL, R_AVR32_11H_PCREL }, + { BFD_RELOC_AVR32_10UW_PCREL, R_AVR32_10UW_PCREL }, + { BFD_RELOC_AVR32_9H_PCREL, R_AVR32_9H_PCREL }, + { BFD_RELOC_AVR32_9UW_PCREL, R_AVR32_9UW_PCREL }, + + { BFD_RELOC_HI16, R_AVR32_HI16 }, + { BFD_RELOC_LO16, R_AVR32_LO16 }, + + { BFD_RELOC_AVR32_GOTPC, R_AVR32_GOTPC }, + { BFD_RELOC_AVR32_GOTCALL, R_AVR32_GOTCALL }, + { BFD_RELOC_AVR32_LDA_GOT, R_AVR32_LDA_GOT }, + { BFD_RELOC_AVR32_GOT21S, R_AVR32_GOT21S }, + { BFD_RELOC_AVR32_GOT18SW, R_AVR32_GOT18SW }, + { BFD_RELOC_AVR32_GOT16S, R_AVR32_GOT16S }, + /* GOT7UW should never be generated by the assembler */ + + { BFD_RELOC_AVR32_32_CPENT, R_AVR32_32_CPENT }, + { BFD_RELOC_AVR32_CPCALL, R_AVR32_CPCALL }, + { BFD_RELOC_AVR32_16_CP, R_AVR32_16_CP }, + { BFD_RELOC_AVR32_9W_CP, R_AVR32_9W_CP }, + + { BFD_RELOC_AVR32_ALIGN, R_AVR32_ALIGN }, +}; + +static reloc_howto_type * +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + unsigned int i; + + for (i = 0; i < sizeof(avr32_reloc_map) / sizeof(struct elf_reloc_map); i++) + { + if (avr32_reloc_map[i].bfd_reloc_val == code) + return &elf_avr32_howto_table[avr32_reloc_map[i].elf_reloc_val]; + } + + return NULL; +} + +static void +avr32_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_AVR32_max); + cache_ptr->howto = &elf_avr32_howto_table[r_type]; +} + + +/* AVR32 ELF linker hash table and associated hash entries. */ + +static struct bfd_hash_entry * +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry, + struct bfd_hash_table *table, + const char *string); +static void +avr32_elf_copy_indirect_symbol(const struct elf_backend_data *bed, + struct elf_link_hash_entry *dir, + struct elf_link_hash_entry *ind); +static struct bfd_link_hash_table * +avr32_elf_link_hash_table_create(bfd *abfd); + +/* + Try to limit memory usage to something reasonable when sorting the + GOT. If we ever get more than this many references to the same + symbol, we may need to do something special. +*/ +#define MAX_NR_GOT_HOLES 8192 + +/* + AVR32 GOT entry. We need to keep track of refcounts and offsets + simultaneously, since we need the offsets during relaxation, and we + also want to be able to drop GOT entries during relaxation. In + addition to this, we want to keep the list of GOT entries sorted so + that we can keep the most-used entries at the lowest offsets. +*/ +struct got_entry +{ + struct got_entry *next; + struct got_entry **pprev; + int refcount; + bfd_signed_vma offset; +}; + +struct elf_avr32_link_hash_entry +{ + struct elf_link_hash_entry root; + + /* Number of runtime relocations against this symbol. */ + unsigned int possibly_dynamic_relocs; + + /* If there are anything but R_AVR32_GOT18 relocations against this + symbol, it means that someone may be taking the address of the + function, and we should therefore not create a stub. */ + bfd_boolean no_fn_stub; + + /* If there is a R_AVR32_32 relocation in a read-only section + against this symbol, we could be in trouble. If we're linking a + shared library or this symbol is defined in one, it means we must + emit a run-time reloc for it and that's not allowed in read-only + sections. */ + asection *readonly_reloc_sec; + bfd_vma readonly_reloc_offset; + + /* Record which frag (if any) contains the symbol. This is used + during relaxation in order to avoid having to update all symbols + whenever we move something. For local symbols, this information + is in the local_sym_frag member of struct elf_obj_tdata. */ + struct fragment *sym_frag; +}; +#define avr32_elf_hash_entry(ent) ((struct elf_avr32_link_hash_entry *)(ent)) + +struct elf_avr32_link_hash_table +{ + struct elf_link_hash_table root; + + /* Shortcuts to get to dynamic linker sections. */ + asection *sgot; + asection *srelgot; + asection *sreldyn; + asection *sstub; + + /* We use a variation of Pigeonhole Sort to sort the GOT. After the + initial refcounts have been determined, we initialize + nr_got_holes to the highest refcount ever seen and allocate an + array of nr_got_holes entries for got_hole. Each GOT entry is + then stored in this array at the index given by its refcount. + + When a GOT entry has its refcount decremented during relaxation, + it is moved to a lower index in the got_hole array. + */ + struct got_entry **got_hole; + int nr_got_holes; + + /* Dynamic relocations to local symbols. Only used when linking a + shared library and -Bsymbolic is not given. */ + unsigned int local_dynamic_relocs; + + bfd_boolean relocations_analyzed; + bfd_boolean symbols_adjusted; + bfd_boolean repeat_pass; + unsigned int relax_iteration; + unsigned int relax_pass; +}; +#define avr32_elf_hash_table(p) \ + ((struct elf_avr32_link_hash_table *)((p)->hash)) + +static struct bfd_hash_entry * +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry, + struct bfd_hash_table *table, + const char *string) +{ + struct elf_avr32_link_hash_entry *ret = avr32_elf_hash_entry(entry); + + /* Allocate the structure if it hasn't already been allocated by a + subclass */ + if (ret == NULL) + ret = (struct elf_avr32_link_hash_entry *) + bfd_hash_allocate(table, sizeof(struct elf_avr32_link_hash_entry)); + + if (ret == NULL) + return NULL; + + memset(ret, 0, sizeof(struct elf_avr32_link_hash_entry)); + + /* Give the superclass a chance */ + ret = (struct elf_avr32_link_hash_entry *) + _bfd_elf_link_hash_newfunc((struct bfd_hash_entry *)ret, table, string); + + return (struct bfd_hash_entry *)ret; +} + +/* Copy data from an indirect symbol to its direct symbol, hiding the + old indirect symbol. Process additional relocation information. + Also called for weakdefs, in which case we just let + _bfd_elf_link_hash_copy_indirect copy the flags for us. */ + +static void +avr32_elf_copy_indirect_symbol(const struct elf_backend_data *bed, + struct elf_link_hash_entry *dir, + struct elf_link_hash_entry *ind) +{ + struct elf_avr32_link_hash_entry *edir, *eind; + + _bfd_elf_link_hash_copy_indirect (bed, dir, ind); + + if (ind->root.type != bfd_link_hash_indirect) + return; + + edir = (struct elf_avr32_link_hash_entry *)dir; + eind = (struct elf_avr32_link_hash_entry *)ind; + + edir->possibly_dynamic_relocs += eind->possibly_dynamic_relocs; + edir->no_fn_stub = edir->no_fn_stub || eind->no_fn_stub; +} + +static struct bfd_link_hash_table * +avr32_elf_link_hash_table_create(bfd *abfd) +{ + struct elf_avr32_link_hash_table *ret; + + ret = bfd_zmalloc(sizeof(*ret)); + if (ret == NULL) + return NULL; + + if (! _bfd_elf_link_hash_table_init(&ret->root, abfd, + avr32_elf_link_hash_newfunc)) + { + free(ret); + return NULL; + } + + /* Prevent the BFD core from creating bogus got_entry pointers */ + ret->root.init_refcount.glist = NULL; + ret->root.init_offset.glist = NULL; + + return &ret->root.root; +} + + +/* Initial analysis and creation of dynamic sections and symbols */ + +static asection * +create_dynamic_section(bfd *dynobj, const char *name, flagword flags, + unsigned int align_power); +static struct elf_link_hash_entry * +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info, + const char *name, asection *sec, + bfd_vma offset); +static bfd_boolean +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info); +static bfd_boolean +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info); +static bfd_boolean +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec, + const Elf_Internal_Rela *relocs); +static bfd_boolean +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info, + struct elf_link_hash_entry *h); + +static asection * +create_dynamic_section(bfd *dynobj, const char *name, flagword flags, + unsigned int align_power) +{ + asection *sec; + + sec = bfd_make_section(dynobj, name); + if (!sec + || !bfd_set_section_flags(dynobj, sec, flags) + || !bfd_set_section_alignment(dynobj, sec, align_power)) + return NULL; + + return sec; +} + +static struct elf_link_hash_entry * +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info, + const char *name, asection *sec, + bfd_vma offset) +{ + struct bfd_link_hash_entry *bh = NULL; + struct elf_link_hash_entry *h; + const struct elf_backend_data *bed = get_elf_backend_data (dynobj); + + if (!(_bfd_generic_link_add_one_symbol + (info, dynobj, name, BSF_GLOBAL, sec, offset, NULL, FALSE, + bed->collect, &bh))) + return NULL; + + h = (struct elf_link_hash_entry *)bh; + h->def_regular = 1; + h->type = STT_OBJECT; + h->other = STV_HIDDEN; + + return h; +} + +static bfd_boolean +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info) +{ + struct elf_avr32_link_hash_table *htab; + flagword flags; + const struct elf_backend_data *bed = get_elf_backend_data (dynobj); + + htab = avr32_elf_hash_table(info); + flags = bed->dynamic_sec_flags; + + if (htab->sgot) + return TRUE; + + htab->sgot = create_dynamic_section(dynobj, ".got", flags, 2); + htab->srelgot = create_dynamic_section(dynobj, ".rela.got", + flags | SEC_READONLY, 2); + + if (!htab->sgot || !htab->srelgot) + return FALSE; + + htab->root.hgot = create_dynamic_symbol(dynobj, info, "_GLOBAL_OFFSET_TABLE_", + htab->sgot, bed->got_symbol_offset); + if (!htab->root.hgot) + return FALSE; + + /* Make room for the GOT header */ + htab->sgot->size += bed->got_header_size + bed->got_symbol_offset; + + return TRUE; +} + +/* (1) Create all dynamic (i.e. linker generated) sections that we may + need during the link */ + +static bfd_boolean +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info) +{ + struct elf_avr32_link_hash_table *htab; + flagword flags; + const struct elf_backend_data *bed = get_elf_backend_data (dynobj); + + pr_debug("(1) create dynamic sections\n"); + + htab = avr32_elf_hash_table(info); + flags = bed->dynamic_sec_flags; + + if (!avr32_elf_create_got_section (dynobj, info)) + return FALSE; + + if (!htab->sreldyn) + htab->sreldyn = create_dynamic_section(dynobj, ".rela.dyn", + flags | SEC_READONLY, 2); + if (!htab->sstub) + htab->sstub = create_dynamic_section(dynobj, ".stub", + flags | SEC_READONLY | SEC_CODE, 2); + + if (!htab->sreldyn || !htab->sstub) + return FALSE; + + return TRUE; +} + +/* (2) Go through all the relocs and count any potential GOT- or + PLT-references to each symbol */ + +static bfd_boolean +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec, + const Elf_Internal_Rela *relocs) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_avr32_link_hash_table *htab; + struct elf_link_hash_entry **sym_hashes; + const Elf_Internal_Rela *rel, *rel_end; + struct got_entry **local_got_ents; + struct got_entry *got; + const struct elf_backend_data *bed = get_elf_backend_data (abfd); + asection *sgot; + bfd *dynobj; + + pr_debug("(2) check relocs for %s:<%s> (size 0x%lx)\n", + abfd->filename, sec->name, sec->size); + + if (info->relocatable) + return TRUE; + + dynobj = elf_hash_table(info)->dynobj; + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes(abfd); + htab = avr32_elf_hash_table(info); + local_got_ents = elf_local_got_ents(abfd); + sgot = htab->sgot; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + unsigned long r_symndx, r_type; + struct elf_avr32_link_hash_entry *h; + + r_symndx = ELF32_R_SYM(rel->r_info); + r_type = ELF32_R_TYPE(rel->r_info); + + /* Local symbols use local_got_ents, while others store the same + information in the hash entry */ + if (r_symndx < symtab_hdr->sh_info) + { + pr_debug(" (2a) processing local symbol %lu\n", r_symndx); + h = NULL; + } + else + { + h = (struct elf_avr32_link_hash_entry *) + sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link; + pr_debug(" (2a) processing symbol %s\n", h->root.root.root.string); + } + + /* Some relocs require special sections to be created. */ + switch (r_type) + { + case R_AVR32_GOT32: + case R_AVR32_GOT16: + case R_AVR32_GOT8: + case R_AVR32_GOT21S: + case R_AVR32_GOT18SW: + case R_AVR32_GOT16S: + case R_AVR32_GOT7UW: + case R_AVR32_LDA_GOT: + case R_AVR32_GOTCALL: + if (rel->r_addend) + { + if (info->callbacks->reloc_dangerous + (info, _("Non-zero addend on GOT-relative relocation"), + abfd, sec, rel->r_offset) == FALSE) + return FALSE; + } + /* fall through */ + case R_AVR32_GOTPC: + if (dynobj == NULL) + elf_hash_table(info)->dynobj = dynobj = abfd; + if (sgot == NULL && !avr32_elf_create_got_section(dynobj, info)) + return FALSE; + break; + case R_AVR32_32: + /* We may need to create .rela.dyn later on. */ + if (dynobj == NULL + && (info->shared || h != NULL) + && (sec->flags & SEC_ALLOC)) + elf_hash_table(info)->dynobj = dynobj = abfd; + break; + } + + if (h != NULL && r_type != R_AVR32_GOT18SW) + h->no_fn_stub = TRUE; + + switch (r_type) + { + case R_AVR32_GOT32: + case R_AVR32_GOT16: + case R_AVR32_GOT8: + case R_AVR32_GOT21S: + case R_AVR32_GOT18SW: + case R_AVR32_GOT16S: + case R_AVR32_GOT7UW: + case R_AVR32_LDA_GOT: + case R_AVR32_GOTCALL: + if (h != NULL) + { + got = h->root.got.glist; + if (!got) + { + got = bfd_zalloc(abfd, sizeof(struct got_entry)); + if (!got) + return FALSE; + h->root.got.glist = got; + } + } + else + { + if (!local_got_ents) + { + bfd_size_type size; + bfd_size_type i; + struct got_entry *tmp_entry; + + size = symtab_hdr->sh_info; + size *= sizeof(struct got_entry *) + sizeof(struct got_entry); + local_got_ents = bfd_zalloc(abfd, size); + if (!local_got_ents) + return FALSE; + + elf_local_got_ents(abfd) = local_got_ents; + + tmp_entry = (struct got_entry *)(local_got_ents + + symtab_hdr->sh_info); + for (i = 0; i < symtab_hdr->sh_info; i++) + local_got_ents[i] = &tmp_entry[i]; + } + + got = local_got_ents[r_symndx]; + } + + got->refcount++; + if (got->refcount > htab->nr_got_holes) + htab->nr_got_holes = got->refcount; + break; + + case R_AVR32_32: + if ((info->shared || h != NULL) + && (sec->flags & SEC_ALLOC)) + { + if (htab->sreldyn == NULL) + { + htab->sreldyn = create_dynamic_section(dynobj, ".rela.dyn", + bed->dynamic_sec_flags + | SEC_READONLY, 2); + if (htab->sreldyn == NULL) + return FALSE; + } + + if (sec->flags & SEC_READONLY + && !h->readonly_reloc_sec) + { + h->readonly_reloc_sec = sec; + h->readonly_reloc_offset = rel->r_offset; + } + + if (h != NULL) + { + pr_debug("Non-GOT reference to symbol %s\n", + h->root.root.root.string); + h->possibly_dynamic_relocs++; + } + else + { + pr_debug("Non-GOT reference to local symbol %lu\n", + r_symndx); + htab->local_dynamic_relocs++; + } + } + + break; + + /* TODO: GNU_VTINHERIT and GNU_VTENTRY */ + } + } + + return TRUE; +} + +/* (3) Adjust a symbol defined by a dynamic object and referenced by a + regular object. The current definition is in some section of the + dynamic object, but we're not including those sections. We have to + change the definition to something the rest of the link can + understand. */ + +static bfd_boolean +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info, + struct elf_link_hash_entry *h) +{ + struct elf_avr32_link_hash_table *htab; + struct elf_avr32_link_hash_entry *havr; + bfd *dynobj; + + pr_debug("(3) adjust dynamic symbol %s\n", h->root.root.string); + + htab = avr32_elf_hash_table(info); + havr = (struct elf_avr32_link_hash_entry *)h; + dynobj = elf_hash_table(info)->dynobj; + + /* Make sure we know what is going on here. */ + BFD_ASSERT (dynobj != NULL + && (h->u.weakdef != NULL + || (h->def_dynamic + && h->ref_regular + && !h->def_regular))); + + /* We don't want dynamic relocations in read-only sections. */ + if (havr->readonly_reloc_sec) + { + if (info->callbacks->reloc_dangerous + (info, _("dynamic relocation in read-only section"), + havr->readonly_reloc_sec->owner, havr->readonly_reloc_sec, + havr->readonly_reloc_offset) == FALSE) + return FALSE; + } + + /* If this is a function, create a stub if possible and set the + symbol to the stub location. */ + if (0 && !havr->no_fn_stub) + { + if (!h->def_regular) + { + asection *s = htab->sstub; + + BFD_ASSERT(s != NULL); + + h->root.u.def.section = s; + h->root.u.def.value = s->size; + h->plt.offset = s->size; + s->size += AVR32_FUNCTION_STUB_SIZE; + + return TRUE; + } + } + else if (h->type == STT_FUNC) + { + /* This will set the entry for this symbol in the GOT to 0, and + the dynamic linker will take care of this. */ + h->root.u.def.value = 0; + return TRUE; + } + + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ + if (h->u.weakdef != NULL) + { + BFD_ASSERT(h->u.weakdef->root.type == bfd_link_hash_defined + || h->u.weakdef->root.type == bfd_link_hash_defweak); + h->root.u.def.section = h->u.weakdef->root.u.def.section; + h->root.u.def.value = h->u.weakdef->root.u.def.value; + return TRUE; + } + + /* This is a reference to a symbol defined by a dynamic object which + is not a function. */ + + return TRUE; +} + + +/* Garbage-collection of unused sections */ + +static asection * +avr32_elf_gc_mark_hook(asection *sec, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rel, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + if (h) + { + switch (ELF32_R_TYPE(rel->r_info)) + { + /* TODO: VTINHERIT/VTENTRY */ + default: + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + + default: + break; + } + } + } + else + return bfd_section_from_elf_index(sec->owner, sym->st_shndx); + + return NULL; +} + +/* Update the GOT entry reference counts for the section being removed. */ +static bfd_boolean +avr32_elf_gc_sweep_hook(bfd *abfd, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *sec, + const Elf_Internal_Rela *relocs) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_avr32_link_hash_entry **sym_hashes; + struct got_entry **local_got_ents; + const Elf_Internal_Rela *rel, *relend; + + if (!(sec->flags & SEC_ALLOC)) + return TRUE; + + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + sym_hashes = (struct elf_avr32_link_hash_entry **)elf_sym_hashes(abfd); + local_got_ents = elf_local_got_ents(abfd); + + relend = relocs + sec->reloc_count; + for (rel = relocs; rel < relend; rel++) + { + unsigned long r_symndx; + unsigned int r_type; + struct elf_avr32_link_hash_entry *h = NULL; + + r_symndx = ELF32_R_SYM(rel->r_info); + if (r_symndx >= symtab_hdr->sh_info) + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.root.type == bfd_link_hash_indirect + || h->root.root.type == bfd_link_hash_warning) + h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link; + } + + r_type = ELF32_R_TYPE(rel->r_info); + + switch (r_type) + { + case R_AVR32_GOT32: + case R_AVR32_GOT16: + case R_AVR32_GOT8: + case R_AVR32_GOT21S: + case R_AVR32_GOT18SW: + case R_AVR32_GOT16S: + case R_AVR32_GOT7UW: + case R_AVR32_LDA_GOT: + case R_AVR32_GOTCALL: + if (h) + h->root.got.glist->refcount--; + else + local_got_ents[r_symndx]->refcount--; + break; + + case R_AVR32_32: + if (info->shared || h) + { + if (h) + h->possibly_dynamic_relocs--; + else + avr32_elf_hash_table(info)->local_dynamic_relocs--; + } + + default: + break; + } + } + + return TRUE; +} + +/* Sizing and refcounting of dynamic sections */ + +static void +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got); +static void +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got); +static void +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got); +static bfd_boolean +assign_got_offsets(struct elf_avr32_link_hash_table *htab); +static bfd_boolean +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info); +static bfd_boolean +avr32_elf_size_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info); + +static void +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got) +{ + /* TODO: Support got_refcount > htab->nr_got_holes by using a + different sort algorithm for those. */ + BFD_ASSERT(got->refcount <= htab->nr_got_holes); + + got->pprev = &htab->got_hole[got->refcount]; + got->next = htab->got_hole[got->refcount]; + if (got->next) + got->next->pprev = &got->next; + + htab->got_hole[got->refcount] = got; +} + +/* Decrement the refcount of a GOT entry and update its position in + the pigeonhole array. */ +static void +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got) +{ + BFD_ASSERT(got->refcount <= htab->nr_got_holes); + BFD_ASSERT(got->refcount > 0); + + if (got->next) + got->next->pprev = got->pprev; + + *(got->pprev) = got->next; + got->refcount--; + insert_got_entry(htab, got); +} + +static void +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got) +{ + if (got->next) + got->next->pprev = got->pprev; + + *(got->pprev) = got->next; + got->refcount++; + insert_got_entry(htab, got); + + BFD_ASSERT(got->refcount > 0); + BFD_ASSERT(got->refcount <= htab->nr_got_holes); +} + +/* Assign offsets to all GOT entries we intend to keep. The entries + that are referenced most often are placed at low offsets so that we + can use compact instructions as much as possible. + + Returns TRUE if any offsets or the total size of the GOT changed. */ + +static bfd_boolean +assign_got_offsets(struct elf_avr32_link_hash_table *htab) +{ + struct got_entry *got; + bfd_size_type got_size = 0; + bfd_boolean changed = FALSE; + bfd_signed_vma offset; + int i; + + /* The GOT header provides the address of the DYNAMIC segment, so + we need that even if the GOT is otherwise empty. */ + if (htab->root.dynamic_sections_created) + got_size = AVR32_GOT_HEADER_SIZE; + + for (i = htab->nr_got_holes; i > 0; i--) + { + got = htab->got_hole[i]; + while (got) + { + if (got->refcount > 0) + { + offset = got_size; + if (got->offset != offset) + { + RDBG("GOT offset changed: %ld -> %ld\n", + got->offset, offset); + changed = TRUE; + } + got->offset = offset; + got_size += 4; + } + got = got->next; + } + } + + if (htab->sgot->size != got_size) + { + RDBG("GOT size changed: %lu -> %lu\n", htab->sgot->size, + got_size); + changed = TRUE; + } + htab->sgot->size = got_size; + + RDBG("assign_got_offsets: total size %lu (%s)\n", + got_size, changed ? "changed" : "no change"); + + return changed; +} + +static bfd_boolean +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info) +{ + struct bfd_link_info *info = _info; + struct elf_avr32_link_hash_table *htab; + struct elf_avr32_link_hash_entry *havr; + struct got_entry *got; + + pr_debug(" (4b) allocate_dynrelocs: %s\n", h->root.root.string); + + if (h->root.type == bfd_link_hash_indirect) + return TRUE; + + if (h->root.type == bfd_link_hash_warning) + /* When warning symbols are created, they **replace** the "real" + entry in the hash table, thus we never get to see the real + symbol in a hash traversal. So look at it now. */ + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + htab = avr32_elf_hash_table(info); + havr = (struct elf_avr32_link_hash_entry *)h; + + got = h->got.glist; + + /* If got is NULL, the symbol is never referenced through the GOT */ + if (got && got->refcount > 0) + { + insert_got_entry(htab, got); + + /* Shared libraries need relocs for all GOT entries unless the + symbol is forced local or -Bsymbolic is used. Others need + relocs for everything that is not guaranteed to be defined in + a regular object. */ + if ((info->shared + && !info->symbolic + && h->dynindx != -1) + || (htab->root.dynamic_sections_created + && h->def_dynamic + && !h->def_regular)) + htab->srelgot->size += sizeof(Elf32_External_Rela); + } + + if (havr->possibly_dynamic_relocs + && (info->shared + || (elf_hash_table(info)->dynamic_sections_created + && h->def_dynamic + && !h->def_regular))) + { + pr_debug("Allocating %d dynamic reloc against symbol %s...\n", + havr->possibly_dynamic_relocs, h->root.root.string); + htab->sreldyn->size += (havr->possibly_dynamic_relocs + * sizeof(Elf32_External_Rela)); + } + + return TRUE; +} + +/* (4) Calculate the sizes of the linker-generated sections and + allocate memory for them. */ + +static bfd_boolean +avr32_elf_size_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info) +{ + struct elf_avr32_link_hash_table *htab; + bfd *dynobj; + asection *s; + bfd *ibfd; + bfd_boolean relocs; + + pr_debug("(4) size dynamic sections\n"); + + htab = avr32_elf_hash_table(info); + dynobj = htab->root.dynobj; + BFD_ASSERT(dynobj != NULL); + + if (htab->root.dynamic_sections_created) + { + /* Initialize the contents of the .interp section to the name of + the dynamic loader */ + if (info->executable) + { + s = bfd_get_section_by_name(dynobj, ".interp"); + BFD_ASSERT(s != NULL); + s->size = sizeof(ELF_DYNAMIC_INTERPRETER); + s->contents = (unsigned char *)ELF_DYNAMIC_INTERPRETER; + } + } + + if (htab->nr_got_holes > 0) + { + /* Allocate holes for the pigeonhole sort algorithm */ + pr_debug("Highest GOT refcount: %d\n", htab->nr_got_holes); + if (htab->nr_got_holes >= MAX_NR_GOT_HOLES) + { + /* TODO: Do something clever (different sorting algorithm) */ + _bfd_error_handler(_("Highest refcount %d too high (max %d)\n"), + htab->nr_got_holes, MAX_NR_GOT_HOLES); + bfd_set_error(bfd_error_no_memory); + return FALSE; + } + htab->got_hole = bfd_zalloc(output_bfd, + sizeof(struct got_entry *) + * (htab->nr_got_holes + 1)); + if (!htab->got_hole) + return FALSE; + + /* Set up .got offsets for local syms. */ + for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next) + { + struct got_entry **local_got; + struct got_entry **end_local_got; + Elf_Internal_Shdr *symtab_hdr; + bfd_size_type locsymcount; + + pr_debug(" (4a) processing file %s...\n", ibfd->filename); + + BFD_ASSERT(bfd_get_flavour(ibfd) == bfd_target_elf_flavour); + + local_got = elf_local_got_ents(ibfd); + if (!local_got) + continue; + + symtab_hdr = &elf_tdata(ibfd)->symtab_hdr; + locsymcount = symtab_hdr->sh_info; + end_local_got = local_got + locsymcount; + + for (; local_got < end_local_got; ++local_got) + insert_got_entry(htab, *local_got); + } + } + + /* Allocate global sym .got entries and space for global sym + dynamic relocs */ + elf_link_hash_traverse(&htab->root, allocate_dynrelocs, info); + + /* Now that we have sorted the GOT entries, we are ready to + assign offsets and determine the initial size of the GOT. */ + if (htab->sgot) + assign_got_offsets(htab); + + /* Allocate space for local sym dynamic relocs */ + BFD_ASSERT(htab->local_dynamic_relocs == 0 || info->shared); + if (htab->local_dynamic_relocs) + htab->sreldyn->size += (htab->local_dynamic_relocs + * sizeof(Elf32_External_Rela)); + + /* We now have determined the sizes of the various dynamic + sections. Allocate memory for them. */ + relocs = FALSE; + for (s = dynobj->sections; s; s = s->next) + { + if ((s->flags & SEC_LINKER_CREATED) == 0) + continue; + + if (s == htab->sgot + || s == htab->sstub) + { + /* Strip this section if we don't need it */ + } + else if (strncmp (bfd_get_section_name(dynobj, s), ".rela", 5) == 0) + { + if (s->size != 0) + relocs = TRUE; + + s->reloc_count = 0; + } + else + { + /* It's not one of our sections */ + continue; + } + + if (s->size == 0) + { + /* Strip unneeded sections */ + pr_debug("Stripping section %s from output...\n", s->name); + _bfd_strip_section_from_output(info, s); + continue; + } + + s->contents = bfd_zalloc(dynobj, s->size); + if (s->contents == NULL) + return FALSE; + } + + if (htab->root.dynamic_sections_created) + { + /* Add some entries to the .dynamic section. We fill in the + values later, in sh_elf_finish_dynamic_sections, but we + must add the entries now so that we get the correct size for + the .dynamic section. The DT_DEBUG entry is filled in by the + dynamic linker and used by the debugger. */ +#define add_dynamic_entry(TAG, VAL) _bfd_elf_add_dynamic_entry(info, TAG, VAL) + + if (!add_dynamic_entry(DT_PLTGOT, 0)) + return FALSE; + if (!add_dynamic_entry(DT_AVR32_GOTSZ, 0)) + return FALSE; + + if (info->executable) + { + if (!add_dynamic_entry(DT_DEBUG, 0)) + return FALSE; + } + if (relocs) + { + if (!add_dynamic_entry(DT_RELA, 0) + || !add_dynamic_entry(DT_RELASZ, 0) + || !add_dynamic_entry(DT_RELAENT, + sizeof(Elf32_External_Rela))) + return FALSE; + } + } +#undef add_dynamic_entry + + return TRUE; +} + + +/* Access to internal relocations, section contents and symbols. + (stolen from the xtensa port) */ + +static Elf_Internal_Rela * +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory); +static void +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs); +static void +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs); +static bfd_byte * +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory); +static void +pin_contents (asection *sec, bfd_byte *contents); +static void +release_contents (asection *sec, bfd_byte *contents); +static Elf_Internal_Sym * +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory); +static void +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf); +static void +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf); + +/* During relaxation, we need to modify relocations, section contents, + and symbol definitions, and we need to keep the original values from + being reloaded from the input files, i.e., we need to "pin" the + modified values in memory. We also want to continue to observe the + setting of the "keep-memory" flag. The following functions wrap the + standard BFD functions to take care of this for us. */ + +static Elf_Internal_Rela * +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory) +{ + /* _bfd_elf_link_read_relocs knows about caching, so no need for us + to be clever here. */ + return _bfd_elf_link_read_relocs(abfd, sec, NULL, NULL, keep_memory); +} + +static void +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs) +{ + elf_section_data (sec)->relocs = internal_relocs; +} + +static void +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs) +{ + if (internal_relocs + && elf_section_data (sec)->relocs != internal_relocs) + free (internal_relocs); +} + +static bfd_byte * +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory) +{ + bfd_byte *contents; + bfd_size_type sec_size; + + sec_size = bfd_get_section_limit (abfd, sec); + contents = elf_section_data (sec)->this_hdr.contents; + + if (contents == NULL && sec_size != 0) + { + if (!bfd_malloc_and_get_section (abfd, sec, &contents)) + { + if (contents) + free (contents); + return NULL; + } + if (keep_memory) + elf_section_data (sec)->this_hdr.contents = contents; + } + return contents; +} + +static void +pin_contents (asection *sec, bfd_byte *contents) +{ + elf_section_data (sec)->this_hdr.contents = contents; +} + +static void +release_contents (asection *sec, bfd_byte *contents) +{ + if (contents && elf_section_data (sec)->this_hdr.contents != contents) + free (contents); +} + +static Elf_Internal_Sym * +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory) +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Sym *isymbuf; + size_t locsymcount; + + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + locsymcount = symtab_hdr->sh_info; + + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; + if (isymbuf == NULL && locsymcount != 0) + { + isymbuf = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, locsymcount, 0, + NULL, NULL, NULL); + if (isymbuf && keep_memory) + symtab_hdr->contents = (unsigned char *) isymbuf; + } + + return isymbuf; +} + +static void +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf) +{ + elf_tdata (input_bfd)->symtab_hdr.contents = (unsigned char *)isymbuf; +} + +static void +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf) +{ + if (isymbuf && (elf_tdata (input_bfd)->symtab_hdr.contents + != (unsigned char *)isymbuf)) + free (isymbuf); +} + + /* Data structures used during relaxation. */ + +enum relax_state_id { + RS_ERROR = -1, + RS_NONE = 0, + RS_ALIGN, + RS_CPENT, + RS_PIC_CALL, + RS_PIC_MCALL, + RS_PIC_RCALL2, + RS_PIC_RCALL1, + RS_PIC_LDA, + RS_PIC_LDW4, + RS_PIC_LDW3, + RS_PIC_SUB5, + RS_NOPIC_MCALL, + RS_NOPIC_RCALL2, + RS_NOPIC_RCALL1, + RS_NOPIC_LDW4, + RS_NOPIC_LDDPC, + RS_NOPIC_SUB5, + RS_RCALL2, + RS_RCALL1, + RS_BRC2, + RS_BRC1, + RS_BRAL, + RS_RJMP, + RS_MAX, +}; + +enum reference_type { + REF_ABSOLUTE, + REF_PCREL, + REF_CPOOL, + REF_GOT, +}; + +struct relax_state +{ + const char *name; + enum relax_state_id id; + enum relax_state_id direct; + enum relax_state_id next; + enum relax_state_id prev; + + enum reference_type reftype; + + unsigned int r_type; + + bfd_vma opcode; + bfd_vma opcode_mask; + + bfd_signed_vma range_min; + bfd_signed_vma range_max; + + unsigned int size; +}; + +/* + * This is for relocs that + * a) has an addend or is of type R_AVR32_DIFF32, and + * b) references a different section than it's in, and + * c) references a section that is relaxable + * + * as well as relocs that references the constant pool, in which case + * the add_frag member points to the frag containing the constant pool + * entry. + * + * Such relocs must be fixed up whenever we delete any code. Sections + * that don't have any relocs with all of the above properties don't + * have any additional reloc data, but sections that do will have + * additional data for all its relocs. + */ +struct avr32_reloc_data +{ + struct fragment *add_frag; + struct fragment *sub_frag; +}; + +/* + * A 'fragment' is a relaxable entity, that is, code may be added or + * deleted at the end of a fragment. When this happens, all subsequent + * fragments in the list will have their offsets updated. + */ +struct fragment +{ + enum relax_state_id state; + enum relax_state_id initial_state; + + Elf_Internal_Rela *rela; + bfd_size_type size; + bfd_vma offset; + int size_adjust; + int offset_adjust; + bfd_boolean has_grown; + + /* Only used by constant pool entries. When this drops to zero, the + frag is discarded (i.e. size_adjust is set to -4.) */ + int refcount; +}; + +struct avr32_relax_data +{ + unsigned int frag_count; + struct fragment *frag; + struct avr32_reloc_data *reloc_data; + + /* TRUE if this section has one or more relaxable relocations */ + bfd_boolean is_relaxable; + unsigned int iteration; +}; + +struct avr32_section_data +{ + struct bfd_elf_section_data elf; + struct avr32_relax_data relax_data; +}; + + /* Relax state definitions */ + +#define PIC_MOV2_OPCODE 0xe0600000 +#define PIC_MOV2_MASK 0xe1e00000 +#define PIC_MOV2_RANGE_MIN (-1048576 * 4) +#define PIC_MOV2_RANGE_MAX (1048575 * 4) +#define PIC_MCALL_OPCODE 0xf0160000 +#define PIC_MCALL_MASK 0xffff0000 +#define PIC_MCALL_RANGE_MIN (-131072) +#define PIC_MCALL_RANGE_MAX (131068) +#define RCALL2_OPCODE 0xe0a00000 +#define RCALL2_MASK 0xe1ef0000 +#define RCALL2_RANGE_MIN (-2097152) +#define RCALL2_RANGE_MAX (2097150) +#define RCALL1_OPCODE 0xc00c0000 +#define RCALL1_MASK 0xf00c0000 +#define RCALL1_RANGE_MIN (-1024) +#define RCALL1_RANGE_MAX (1022) +#define PIC_LDW4_OPCODE 0xecf00000 +#define PIC_LDW4_MASK 0xfff00000 +#define PIC_LDW4_RANGE_MIN (-32768) +#define PIC_LDW4_RANGE_MAX (32767) +#define PIC_LDW3_OPCODE 0x6c000000 +#define PIC_LDW3_MASK 0xfe000000 +#define PIC_LDW3_RANGE_MIN (0) +#define PIC_LDW3_RANGE_MAX (124) +#define SUB5_PC_OPCODE 0xfec00000 +#define SUB5_PC_MASK 0xfff00000 +#define SUB5_PC_RANGE_MIN (-32768) +#define SUB5_PC_RANGE_MAX (32767) +#define NOPIC_MCALL_OPCODE 0xf01f0000 +#define NOPIC_MCALL_MASK 0xffff0000 +#define NOPIC_MCALL_RANGE_MIN PIC_MCALL_RANGE_MIN +#define NOPIC_MCALL_RANGE_MAX PIC_MCALL_RANGE_MAX +#define NOPIC_LDW4_OPCODE 0xfef00000 +#define NOPIC_LDW4_MASK 0xfff00000 +#define NOPIC_LDW4_RANGE_MIN PIC_LDW4_RANGE_MIN +#define NOPIC_LDW4_RANGE_MAX PIC_LDW4_RANGE_MAX +#define LDDPC_OPCODE 0x48000000 +#define LDDPC_MASK 0xf8000000 +#define LDDPC_RANGE_MIN 0 +#define LDDPC_RANGE_MAX 508 + +/* Only brc2 variants with cond[3] == 0 is considered, since the + others are not relaxable. bral is a special case and is handled + separately. */ +#define BRC2_OPCODE 0xe0800000 +#define BRC2_MASK 0xe1e80000 +#define BRC2_RANGE_MIN (-2097152) +#define BRC2_RANGE_MAX (2097150) +#define BRC1_OPCODE 0xc0000000 +#define BRC1_MASK 0xf0080000 +#define BRC1_RANGE_MIN (-256) +#define BRC1_RANGE_MAX (254) +#define BRAL_OPCODE 0xe08f0000 +#define BRAL_MASK 0xe1ef0000 +#define BRAL_RANGE_MIN BRC2_RANGE_MIN +#define BRAL_RANGE_MAX BRC2_RANGE_MAX +#define RJMP_OPCODE 0xc0080000 +#define RJMP_MASK 0xf00c0000 +#define RJMP_RANGE_MIN (-1024) +#define RJMP_RANGE_MAX (1022) + +/* Define a relax state using the GOT */ +#define RG(id, dir, next, prev, r_type, opc, size) \ + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_GOT, \ + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \ + opc##_RANGE_MIN, opc##_RANGE_MAX, size } +/* Define a relax state using the Constant Pool */ +#define RC(id, dir, next, prev, r_type, opc, size) \ + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_CPOOL, \ + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \ + opc##_RANGE_MIN, opc##_RANGE_MAX, size } + +/* Define a relax state using pc-relative direct reference */ +#define RP(id, dir, next, prev, r_type, opc, size) \ + { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_PCREL, \ + R_AVR32_##r_type, opc##_OPCODE, opc##_MASK, \ + opc##_RANGE_MIN, opc##_RANGE_MAX, size } + +/* Define a relax state that will be handled specially */ +#define RS(id, r_type, size) \ + { "RS_"#id, RS_##id, RS_NONE, RS_NONE, RS_NONE, REF_ABSOLUTE, \ + R_AVR32_##r_type, 0, 0, 0, 0, size } + +const struct relax_state relax_state[RS_MAX] = { + RS(NONE, NONE, 0), + RS(ALIGN, ALIGN, 0), + RS(CPENT, 32_CPENT, 4), + + RG(PIC_CALL, PIC_RCALL1, PIC_MCALL, NONE, GOTCALL, PIC_MOV2, 10), + RG(PIC_MCALL, PIC_RCALL1, NONE, PIC_CALL, GOT18SW, PIC_MCALL, 4), + RP(PIC_RCALL2, NONE, PIC_RCALL1, PIC_MCALL, 22H_PCREL, RCALL2, 4), + RP(PIC_RCALL1, NONE, NONE, PIC_RCALL2, 11H_PCREL, RCALL1, 2), + + RG(PIC_LDA, PIC_SUB5, PIC_LDW4, NONE, LDA_GOT, PIC_MOV2, 8), + RG(PIC_LDW4, PIC_SUB5, PIC_LDW3, PIC_LDA, GOT16S, PIC_LDW4, 4), + RG(PIC_LDW3, PIC_SUB5, NONE, PIC_LDW4, GOT7UW, PIC_LDW3, 2), + RP(PIC_SUB5, NONE, NONE, PIC_LDW3, 16N_PCREL, SUB5_PC, 4), + + RC(NOPIC_MCALL, NOPIC_RCALL1, NONE, NONE, CPCALL, NOPIC_MCALL, 4), + RP(NOPIC_RCALL2, NONE, NOPIC_RCALL1, NOPIC_MCALL, 22H_PCREL, RCALL2, 4), + RP(NOPIC_RCALL1, NONE, NONE, NOPIC_RCALL2, 11H_PCREL, RCALL1, 2), + + RC(NOPIC_LDW4, NOPIC_SUB5, NOPIC_LDDPC, NONE, 16_CP, NOPIC_LDW4, 4), + RC(NOPIC_LDDPC, NOPIC_SUB5, NONE, NOPIC_LDW4, 9W_CP, LDDPC, 2), + RP(NOPIC_SUB5, NONE, NONE, NOPIC_LDDPC, 16N_PCREL, SUB5_PC, 4), + + RP(RCALL2, NONE, RCALL1, NONE, 22H_PCREL, RCALL2, 4), + RP(RCALL1, NONE, NONE, RCALL2, 11H_PCREL, RCALL1, 2), + RP(BRC2, NONE, BRC1, NONE, 22H_PCREL, BRC2, 4), + RP(BRC1, NONE, NONE, BRC2, 9H_PCREL, BRC1, 2), + RP(BRAL, NONE, RJMP, NONE, 22H_PCREL, BRAL, 4), + RP(RJMP, NONE, NONE, BRAL, 11H_PCREL, RJMP, 2), +}; + +static bfd_boolean +avr32_elf_new_section_hook(bfd *abfd, asection *sec) +{ + struct avr32_section_data *sdata; + + sdata = bfd_zalloc(abfd, sizeof(struct avr32_section_data)); + if (!sdata) + return FALSE; + + sec->used_by_bfd = sdata; + return _bfd_elf_new_section_hook(abfd, sec); +} + +static struct avr32_relax_data * +avr32_relax_data(asection *sec) +{ + struct avr32_section_data *sdata; + + BFD_ASSERT(sec->used_by_bfd); + + sdata = (struct avr32_section_data *)elf_section_data(sec); + return &sdata->relax_data; +} + + /* Link-time relaxation */ + +static bfd_boolean +avr32_elf_relax_section(bfd *abfd, asection *sec, + struct bfd_link_info *info, bfd_boolean *again); + +enum relax_pass_id { + RELAX_PASS_SIZE_FRAGS, + RELAX_PASS_MOVE_DATA, +}; + +/* Stolen from the xtensa port */ +static int +internal_reloc_compare (const void *ap, const void *bp) +{ + const Elf_Internal_Rela *a = (const Elf_Internal_Rela *) ap; + const Elf_Internal_Rela *b = (const Elf_Internal_Rela *) bp; + + if (a->r_offset != b->r_offset) + return (a->r_offset - b->r_offset); + + /* We don't need to sort on these criteria for correctness, + but enforcing a more strict ordering prevents unstable qsort + from behaving differently with different implementations. + Without the code below we get correct but different results + on Solaris 2.7 and 2.8. We would like to always produce the + same results no matter the host. */ + + if (a->r_info != b->r_info) + return (a->r_info - b->r_info); + + return (a->r_addend - b->r_addend); +} + +static enum relax_state_id +get_pcrel22_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info, + const Elf_Internal_Rela *rela) +{ + bfd_byte *contents; + bfd_vma insn; + enum relax_state_id rs = RS_NONE; + + contents = retrieve_contents(abfd, sec, info->keep_memory); + if (!contents) + return RS_ERROR; + + insn = bfd_get_32(abfd, contents + rela->r_offset); + if ((insn & RCALL2_MASK) == RCALL2_OPCODE) + rs = RS_RCALL2; + else if ((insn & BRAL_MASK) == BRAL_OPCODE) + /* Optimizing bral -> rjmp gets us into all kinds of + trouble with jump tables. Better not do it. */ + rs = RS_NONE; + else if ((insn & BRC2_MASK) == BRC2_OPCODE) + rs = RS_BRC2; + + release_contents(sec, contents); + + return rs; +} + +static enum relax_state_id +get_initial_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info, + const Elf_Internal_Rela *rela) +{ + switch (ELF_R_TYPE(rela->r_info)) + { + case R_AVR32_GOTCALL: + return RS_PIC_CALL; + case R_AVR32_GOT18SW: + return RS_PIC_MCALL; + case R_AVR32_LDA_GOT: + return RS_PIC_LDA; + case R_AVR32_GOT16S: + return RS_PIC_LDW4; + case R_AVR32_CPCALL: + return RS_NOPIC_MCALL; + case R_AVR32_16_CP: + return RS_NOPIC_LDW4; + case R_AVR32_9W_CP: + return RS_NOPIC_LDDPC; + case R_AVR32_ALIGN: + return RS_ALIGN; + case R_AVR32_32_CPENT: + return RS_CPENT; + case R_AVR32_22H_PCREL: + return get_pcrel22_relax_state(abfd, sec, info, rela); + case R_AVR32_9H_PCREL: + return RS_BRC1; + default: + return RS_NONE; + } +} + +static bfd_boolean +reloc_is_cpool_ref(const Elf_Internal_Rela *rela) +{ + switch (ELF_R_TYPE(rela->r_info)) + { + case R_AVR32_CPCALL: + case R_AVR32_16_CP: + case R_AVR32_9W_CP: + return TRUE; + default: + return FALSE; + } +} + +static struct fragment * +new_frag(bfd *abfd ATTRIBUTE_UNUSED, asection *sec, + struct avr32_relax_data *rd, enum relax_state_id state, + Elf_Internal_Rela *rela) +{ + struct fragment *frag; + bfd_size_type r_size; + bfd_vma r_offset; + unsigned int i = rd->frag_count; + + BFD_ASSERT(state >= RS_NONE && state < RS_MAX); + + rd->frag_count++; + frag = bfd_realloc(rd->frag, sizeof(struct fragment) * rd->frag_count); + if (!frag) + return NULL; + rd->frag = frag; + + frag += i; + memset(frag, 0, sizeof(struct fragment)); + + if (state == RS_ALIGN) + r_size = (((rela->r_offset + (1 << rela->r_addend) - 1) + & ~((1 << rela->r_addend) - 1)) - rela->r_offset); + else + r_size = relax_state[state].size; + + if (rela) + r_offset = rela->r_offset; + else + r_offset = sec->size; + + if (i == 0) + { + frag->offset = 0; + frag->size = r_offset + r_size; + } + else + { + frag->offset = rd->frag[i - 1].offset + rd->frag[i - 1].size; + frag->size = r_offset + r_size - frag->offset; + } + + if (state != RS_CPENT) + /* Make sure we don't discard this frag */ + frag->refcount = 1; + + frag->initial_state = frag->state = state; + frag->rela = rela; + + return frag; +} + +static struct fragment * +find_frag(asection *sec, bfd_vma offset) +{ + struct fragment *first, *last; + struct avr32_relax_data *rd = avr32_relax_data(sec); + + if (rd->frag_count == 0) + return NULL; + + first = &rd->frag[0]; + last = &rd->frag[rd->frag_count - 1]; + + /* This may be a reloc referencing the end of a section. The last + frag will never have a reloc associated with it, so its size will + never change, thus the offset adjustment of the last frag will + always be the same as the offset adjustment of the end of the + section. */ + if (offset == sec->size) + { + BFD_ASSERT(last->offset + last->size == sec->size); + BFD_ASSERT(!last->rela); + return last; + } + + while (first <= last) + { + struct fragment *mid; + + mid = (last - first) / 2 + first; + if ((mid->offset + mid->size) <= offset) + first = mid + 1; + else if (mid->offset > offset) + last = mid - 1; + else + return mid; + } + + return NULL; +} + +/* Look through all relocs in a section and determine if any relocs + may be affected by relaxation in other sections. If so, allocate + an array of additional relocation data which links the affected + relocations to the frag(s) where the relaxation may occur. + + This function also links cpool references to cpool entries and + increments the refcount of the latter when this happens. */ + +static bfd_boolean +allocate_reloc_data(bfd *abfd, asection *sec, Elf_Internal_Rela *relocs, + struct bfd_link_info *info) +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Sym *isymbuf = NULL; + struct avr32_relax_data *rd; + unsigned int i; + bfd_boolean ret = FALSE; + + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + rd = avr32_relax_data(sec); + + RDBG("%s<%s>: allocate_reloc_data\n", abfd->filename, sec->name); + + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *rel = &relocs[i]; + asection *sym_sec; + unsigned long r_symndx; + bfd_vma sym_value; + + if (!rel->r_addend && ELF_R_TYPE(rel->r_info) != R_AVR32_DIFF32 + && !reloc_is_cpool_ref(rel)) + continue; + + r_symndx = ELF_R_SYM(rel->r_info); + + if (r_symndx < symtab_hdr->sh_info) + { + Elf_Internal_Sym *isym; + + if (!isymbuf) + isymbuf = retrieve_local_syms(abfd, info->keep_memory); + if (!isymbuf) + return FALSE; + + isym = &isymbuf[r_symndx]; + sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx); + sym_value = isym->st_value; + } + else + { + struct elf_link_hash_entry *h; + + h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *)h->root.u.i.link; + + if (h->root.type != bfd_link_hash_defined + && h->root.type != bfd_link_hash_defweak) + continue; + + sym_sec = h->root.u.def.section; + sym_value = h->root.u.def.value; + } + + if (sym_sec && avr32_relax_data(sym_sec)->is_relaxable) + { + bfd_size_type size; + struct fragment *frag; + + if (!rd->reloc_data) + { + size = sizeof(struct avr32_reloc_data) * sec->reloc_count; + rd->reloc_data = bfd_zalloc(abfd, size); + if (!rd->reloc_data) + goto out; + } + + RDBG("[%3d] 0x%04lx: target: 0x%lx + 0x%lx", + i, rel->r_offset, sym_value, rel->r_addend); + + frag = find_frag(sym_sec, sym_value + rel->r_addend); + BFD_ASSERT(frag); + rd->reloc_data[i].add_frag = frag; + + RDBG(" -> %s<%s>:%04lx\n", sym_sec->owner->filename, sym_sec->name, + frag->rela ? frag->rela->r_offset : sym_sec->size); + + if (reloc_is_cpool_ref(rel)) + { + BFD_ASSERT(ELF_R_TYPE(frag->rela->r_info) == R_AVR32_32_CPENT); + frag->refcount++; + } + + if (ELF_R_TYPE(rel->r_info) == R_AVR32_DIFF32) + { + bfd_byte *contents; + bfd_signed_vma diff; + + contents = retrieve_contents(abfd, sec, info->keep_memory); + if (!contents) + goto out; + + diff = bfd_get_32(abfd, contents + rel->r_offset); + frag = find_frag(sym_sec, sym_value + rel->r_addend + diff); + BFD_ASSERT(frag); + rd->reloc_data[i].sub_frag = frag; + + release_contents(sec, contents); + } + } + } + + ret = TRUE; + + out: + release_local_syms(abfd, isymbuf); + return ret; +} + +static bfd_boolean +global_sym_set_frag(struct elf_avr32_link_hash_entry *havr, + struct bfd_link_info *info ATTRIBUTE_UNUSED) +{ + struct fragment *frag; + asection *sec; + + if (havr->root.root.type != bfd_link_hash_defined + && havr->root.root.type != bfd_link_hash_defweak) + return TRUE; + + sec = havr->root.root.u.def.section; + if (bfd_is_const_section(sec) + || !avr32_relax_data(sec)->is_relaxable) + return TRUE; + + frag = find_frag(sec, havr->root.root.u.def.value); + if (!frag) + { + unsigned int i; + struct avr32_relax_data *rd = avr32_relax_data(sec); + + RDBG("In %s: No frag for %s <%s+%lu> (limit %lu)\n", + sec->owner->filename, havr->root.root.root.string, + sec->name, havr->root.root.u.def.value, sec->size); + for (i = 0; i < rd->frag_count; i++) + RDBG(" %8lu - %8lu\n", rd->frag[i].offset, + rd->frag[i].offset + rd->frag[i].size); + } + BFD_ASSERT(frag); + + havr->sym_frag = frag; + return TRUE; +} + +static bfd_boolean +analyze_relocations(struct bfd_link_info *info) +{ + bfd *abfd; + asection *sec; + + /* Divide all relaxable sections into fragments */ + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next) + { + if (!(elf_elfheader(abfd)->e_flags & EF_AVR32_LINKRELAX)) + { + if (!(*info->callbacks->warning) + (info, _("input is not relaxable"), NULL, abfd, NULL, 0)) + return FALSE; + continue; + } + + for (sec = abfd->sections; sec; sec = sec->next) + { + struct avr32_relax_data *rd; + struct fragment *frag; + Elf_Internal_Rela *relocs; + unsigned int i; + bfd_boolean ret = TRUE; + + if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0) + continue; + + rd = avr32_relax_data(sec); + + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory); + if (!relocs) + return FALSE; + + qsort(relocs, sec->reloc_count, sizeof(Elf_Internal_Rela), + internal_reloc_compare); + + for (i = 0; i < sec->reloc_count; i++) + { + enum relax_state_id state; + + ret = FALSE; + state = get_initial_relax_state(abfd, sec, info, &relocs[i]); + if (state == RS_ERROR) + break; + + if (state) + { + frag = new_frag(abfd, sec, rd, state, &relocs[i]); + if (!frag) + break; + + pin_internal_relocs(sec, relocs); + rd->is_relaxable = TRUE; + } + + ret = TRUE; + } + + release_internal_relocs(sec, relocs); + if (!ret) + return ret; + + if (rd->is_relaxable) + { + frag = new_frag(abfd, sec, rd, RS_NONE, NULL); + if (!frag) + return FALSE; + } + } + } + + /* Link each global symbol to the fragment where it's defined. */ + elf_link_hash_traverse(elf_hash_table(info), global_sym_set_frag, info); + + /* Do the same for local symbols. */ + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next) + { + Elf_Internal_Sym *isymbuf, *isym; + struct fragment **local_sym_frag; + unsigned int i, sym_count; + + sym_count = elf_tdata(abfd)->symtab_hdr.sh_info; + if (sym_count == 0) + continue; + + local_sym_frag = bfd_zalloc(abfd, sym_count * sizeof(struct fragment *)); + if (!local_sym_frag) + return FALSE; + elf_tdata(abfd)->local_sym_frag = local_sym_frag; + + isymbuf = retrieve_local_syms(abfd, info->keep_memory); + if (!isymbuf) + return FALSE; + + for (i = 0; i < sym_count; i++) + { + struct avr32_relax_data *rd; + struct fragment *frag; + asection *sec; + + isym = &isymbuf[i]; + + sec = bfd_section_from_elf_index(abfd, isym->st_shndx); + if (!sec) + continue; + + rd = avr32_relax_data(sec); + if (!rd->is_relaxable) + continue; + + frag = find_frag(sec, isym->st_value); + BFD_ASSERT(frag); + + local_sym_frag[i] = frag; + } + + release_local_syms(abfd, isymbuf); + } + + /* And again for relocs with addends and constant pool references */ + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next) + for (sec = abfd->sections; sec; sec = sec->next) + { + Elf_Internal_Rela *relocs; + bfd_boolean ret; + + if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0) + continue; + + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory); + if (!relocs) + return FALSE; + + ret = allocate_reloc_data(abfd, sec, relocs, info); + + release_internal_relocs(sec, relocs); + if (ret == FALSE) + return ret; + } + + return TRUE; +} + +static bfd_boolean +rs_is_good_enough(const struct relax_state *rs, struct fragment *frag, + bfd_vma symval, bfd_vma addr, struct got_entry *got, + struct avr32_reloc_data *ind_data, + bfd_signed_vma offset_adjust) +{ + bfd_signed_vma target = 0; + + switch (rs->reftype) + { + case REF_ABSOLUTE: + target = symval; + break; + case REF_PCREL: + target = symval - addr; + break; + case REF_CPOOL: + /* cpool frags are always in the same section and always after + all frags referring to it. So it's always correct to add in + offset_adjust here. */ + target = (ind_data->add_frag->offset + ind_data->add_frag->offset_adjust + + offset_adjust - frag->offset - frag->offset_adjust); + break; + case REF_GOT: + target = got->offset; + break; + default: + abort(); + } + + if (target >= rs->range_min && target <= rs->range_max) + return TRUE; + else + return FALSE; +} + +static bfd_boolean +avr32_size_frags(bfd *abfd, asection *sec, struct bfd_link_info *info) +{ + struct elf_avr32_link_hash_table *htab; + struct avr32_relax_data *rd; + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Rela *relocs = NULL; + Elf_Internal_Sym *isymbuf = NULL; + struct got_entry **local_got_ents; + struct fragment **local_sym_frag; + bfd_boolean ret = FALSE; + bfd_signed_vma delta = 0; + unsigned int i; + + htab = avr32_elf_hash_table(info); + rd = avr32_relax_data(sec); + + if (sec == htab->sgot) + { + RDBG("Relaxing GOT section (vma: 0x%lx)\n", + sec->output_section->vma + sec->output_offset); + if (assign_got_offsets(htab)) + htab->repeat_pass = TRUE; + return TRUE; + } + + if (!rd->is_relaxable) + return TRUE; + + if (!sec->rawsize) + sec->rawsize = sec->size; + + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory); + if (!relocs) + goto out; + + isymbuf = retrieve_local_syms(abfd, info->keep_memory); + if (!isymbuf) + goto out; + + local_got_ents = elf_local_got_ents(abfd); + local_sym_frag = elf_tdata(abfd)->local_sym_frag; + + RDBG("size_frags: %s<%s>\n vma: 0x%08lx, size: 0x%08lx\n", + abfd->filename, sec->name, + sec->output_section->vma + sec->output_offset, sec->size); + + for (i = 0; i < rd->frag_count; i++) + { + struct fragment *frag = &rd->frag[i]; + struct avr32_reloc_data *r_data = NULL, *ind_data = NULL; + const struct relax_state *state, *next_state; + struct fragment *target_frag = NULL; + asection *sym_sec; + Elf_Internal_Rela *rela; + struct got_entry *got; + bfd_vma symval, r_offset, addend, addr; + bfd_signed_vma size_adjust = 0, distance; + unsigned long r_symndx; + bfd_boolean defined = TRUE, dynamic = FALSE; + unsigned char sym_type; + + frag->offset_adjust += delta; + state = next_state = &relax_state[frag->state]; + rela = frag->rela; + + BFD_ASSERT(state->id == frag->state); + + RDBG(" 0x%04lx%c%d: %s [size %d]", rela ? rela->r_offset : sec->rawsize, + (frag->offset_adjust < 0)?'-':'+', + abs(frag->offset_adjust), state->name, state->size); + + if (frag->has_grown) + { + /* There's a theoretical possibility that shrinking one frag + may cause another to grow, which may cause the first one to + grow as well, and we're back where we started. Avoid this + scenario by disallowing a frag that has grown to ever + shrink again. */ + RDBG(": has grown, ignoring\n"); + continue; + } + + if (!rela) + { + RDBG(": no reloc, ignoring\n"); + continue; + } + + BFD_ASSERT((unsigned int)(rela - relocs) < sec->reloc_count); + BFD_ASSERT(state != RS_NONE); + + r_offset = rela->r_offset + frag->offset_adjust; + addr = sec->output_section->vma + sec->output_offset + r_offset; + + switch (frag->state) + { + case RS_ALIGN: + size_adjust = ((addr + (1 << rela->r_addend) - 1) + & ~((1 << rela->r_addend) - 1)); + size_adjust -= (sec->output_section->vma + sec->output_offset + + frag->offset + frag->offset_adjust + + frag->size + frag->size_adjust); + + RDBG(": adjusting size %lu -> %lu\n", frag->size + frag->size_adjust, + frag->size + frag->size_adjust + size_adjust); + break; + + case RS_CPENT: + if (frag->refcount == 0 && frag->size_adjust == 0) + { + RDBG(": discarding frag\n"); + size_adjust = -4; + } + else if (frag->refcount > 0 && frag->size_adjust < 0) + { + RDBG(": un-discarding frag\n"); + size_adjust = 4; + } + break; + + default: + if (rd->reloc_data) + r_data = &rd->reloc_data[frag->rela - relocs]; + + /* If this is a cpool reference, we want the symbol that the + cpool entry refers to, not the symbol for the cpool entry + itself, as we already know what frag it's in. */ + if (relax_state[frag->initial_state].reftype == REF_CPOOL) + { + Elf_Internal_Rela *irela = r_data->add_frag->rela; + + r_symndx = ELF_R_SYM(irela->r_info); + addend = irela->r_addend; + + /* The constant pool must be in the same section as the + reloc referring to it. */ + BFD_ASSERT((unsigned long)(irela - relocs) < sec->reloc_count); + + ind_data = r_data; + r_data = &rd->reloc_data[irela - relocs]; + } + else + { + r_symndx = ELF_R_SYM(rela->r_info); + addend = rela->r_addend; + } + + /* Get the value of the symbol referred to by the reloc. */ + if (r_symndx < symtab_hdr->sh_info) + { + Elf_Internal_Sym *isym; + + isym = isymbuf + r_symndx; + symval = 0; + + RDBG(" local sym %lu: ", r_symndx); + + if (isym->st_shndx == SHN_UNDEF) + defined = FALSE; + else if (isym->st_shndx == SHN_ABS) + sym_sec = bfd_abs_section_ptr; + else if (isym->st_shndx == SHN_COMMON) + sym_sec = bfd_com_section_ptr; + else + sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx); + + symval = isym->st_value; + sym_type = ELF_ST_TYPE(isym->st_info); + target_frag = local_sym_frag[r_symndx]; + + if (local_got_ents) + got = local_got_ents[r_symndx]; + else + got = NULL; + } + else + { + /* Global symbol */ + unsigned long index; + struct elf_link_hash_entry *h; + struct elf_avr32_link_hash_entry *havr; + + index = r_symndx - symtab_hdr->sh_info; + h = elf_sym_hashes(abfd)[index]; + BFD_ASSERT(h != NULL); + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *)h->root.u.i.link; + + havr = (struct elf_avr32_link_hash_entry *)h; + got = h->got.glist; + + symval = 0; + + RDBG(" %s: ", h->root.root.string); + + if (h->root.type != bfd_link_hash_defined + && h->root.type != bfd_link_hash_defweak) + { + RDBG("(undef)"); + defined = FALSE; + } + else if ((info->shared && !info->symbolic && h->dynindx != -1) + || (htab->root.dynamic_sections_created + && h->def_dynamic && !h->def_regular)) + { + RDBG("(dynamic)"); + dynamic = TRUE; + sym_sec = h->root.u.def.section; + } + else + { + sym_sec = h->root.u.def.section; + symval = h->root.u.def.value; + target_frag = havr->sym_frag; + } + + sym_type = h->type; + } + + /* Thanks to elf32-ppc for this one. */ + if (sym_sec && sym_sec->sec_info_type == ELF_INFO_TYPE_MERGE) + { + /* At this stage in linking, no SEC_MERGE symbol has been + adjusted, so all references to such symbols need to be + passed through _bfd_merged_section_offset. (Later, in + relocate_section, all SEC_MERGE symbols *except* for + section symbols have been adjusted.) + + SEC_MERGE sections are not relaxed by us, as they + shouldn't contain any code. */ + + BFD_ASSERT(!target_frag && !(r_data && r_data->add_frag)); + + /* gas may reduce relocations against symbols in SEC_MERGE + sections to a relocation against the section symbol when + the original addend was zero. When the reloc is against + a section symbol we should include the addend in the + offset passed to _bfd_merged_section_offset, since the + location of interest is the original symbol. On the + other hand, an access to "sym+addend" where "sym" is not + a section symbol should not include the addend; Such an + access is presumed to be an offset from "sym"; The + location of interest is just "sym". */ + RDBG("\n MERGE: %s: 0x%lx+0x%lx+0x%lx -> ", + (sym_type == STT_SECTION)?"section":"not section", + sym_sec->output_section->vma + sym_sec->output_offset, + symval, addend); + + if (sym_type == STT_SECTION) + symval += addend; + + symval = (_bfd_merged_section_offset + (abfd, &sym_sec, + elf_section_data(sym_sec)->sec_info, symval)); + + if (sym_type != STT_SECTION) + symval += addend; + } + else + symval += addend; + + if (defined && !dynamic) + { + RDBG("0x%lx+0x%lx", + sym_sec->output_section->vma + sym_sec->output_offset, + symval); + symval += sym_sec->output_section->vma + sym_sec->output_offset; + } + + if (r_data && r_data->add_frag) + /* If the add_frag pointer is set, it means that this reloc + has an addend that may be affected by relaxation. */ + target_frag = r_data->add_frag; + + if (target_frag) + { + symval += target_frag->offset_adjust; + + /* If target_frag comes after this frag in the same + section, we should assume that it will be moved by + the same amount we are. */ + if ((target_frag - rd->frag) < (int)rd->frag_count + && target_frag > frag) + symval += delta; + } + + distance = symval - addr; + + /* First, try to make a direct reference. If the symbol is + dynamic or undefined, we must take care not to change its + reference type, that is, we can't make it direct. + + Also, it seems like some sections may actually be resized + after the relaxation code is done, so we can't really + trust that our "distance" is correct. There's really no + easy solution to this problem, so we'll just disallow + direct references to SEC_DATA sections. */ + if (!dynamic && defined + && !(sym_sec->flags & SEC_DATA) + && next_state->direct) + { + next_state = &relax_state[next_state->direct]; + RDBG(" D-> %s", next_state->name); + } + + /* Iterate backwards until we find a state that fits. */ + while (next_state->prev + && !rs_is_good_enough(next_state, frag, symval, addr, + got, ind_data, delta)) + { + next_state = &relax_state[next_state->prev]; + RDBG(" P-> %s", next_state->name); + } + + /* Then try to find the best possible state. */ + while (next_state->next) + { + const struct relax_state *candidate; + + candidate = &relax_state[next_state->next]; + if (!rs_is_good_enough(candidate, frag, symval, addr, got, + ind_data, delta)) + break; + + next_state = candidate; + RDBG(" N-> %s", next_state->name); + } + + RDBG(" [size %d]\n", next_state->size); + + BFD_ASSERT(next_state->id); + BFD_ASSERT(!dynamic || next_state->reftype == REF_GOT); + + if (state->reftype == REF_GOT && next_state->reftype != REF_GOT) + unref_got_entry(htab, got); + else if (state->reftype != REF_GOT && next_state->reftype == REF_GOT) + ref_got_entry(htab, got); + else if (state->reftype == REF_CPOOL + && next_state->reftype != REF_CPOOL) + ind_data->add_frag->refcount--; + else if (state->reftype != REF_CPOOL + && next_state->reftype == REF_CPOOL) + ind_data->add_frag->refcount++; + + size_adjust = next_state->size - state->size; + frag->state = next_state->id; + + break; + } + + if (size_adjust) + htab->repeat_pass = TRUE; + + frag->size_adjust += size_adjust; + sec->size += size_adjust; + delta += size_adjust; + + BFD_ASSERT((frag->offset + frag->offset_adjust + + frag->size + frag->size_adjust) + == (frag[1].offset + frag[1].offset_adjust + delta)); + } + + ret = TRUE; + + out: + release_local_syms(abfd, isymbuf); + release_internal_relocs(sec, relocs); + return ret; +} + +static bfd_boolean +adjust_global_symbol(struct elf_avr32_link_hash_entry *havr, + struct bfd_link_info *info ATTRIBUTE_UNUSED) +{ + struct elf_link_hash_entry *h = &havr->root; + + if (havr->sym_frag && (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak)) + { + RDBG("adjust_global_symbol: %s 0x%08lx -> 0x%08lx\n", + h->root.root.string, h->root.u.def.value, + h->root.u.def.value + havr->sym_frag->offset_adjust); + h->root.u.def.value += havr->sym_frag->offset_adjust; + } + return TRUE; +} + +static bfd_boolean +adjust_syms(struct bfd_link_info *info) +{ + struct elf_avr32_link_hash_table *htab; + bfd *abfd; + + htab = avr32_elf_hash_table(info); + elf_link_hash_traverse(&htab->root, adjust_global_symbol, info); + + for (abfd = info->input_bfds; abfd; abfd = abfd->link_next) + { + Elf_Internal_Sym *isymbuf; + struct fragment **local_sym_frag, *frag; + unsigned int i, sym_count; + + sym_count = elf_tdata(abfd)->symtab_hdr.sh_info; + if (sym_count == 0) + continue; + + isymbuf = retrieve_local_syms(abfd, info->keep_memory); + if (!isymbuf) + return FALSE; + + local_sym_frag = elf_tdata(abfd)->local_sym_frag; + + for (i = 0; i < sym_count; i++) + { + frag = local_sym_frag[i]; + if (frag) + { + RDBG("adjust_local_symbol: %s[%u] 0x%08lx -> 0x%08lx\n", + abfd->filename, i, isymbuf[i].st_value, + isymbuf[i].st_value + frag->offset_adjust); + isymbuf[i].st_value += frag->offset_adjust; + } + } + + release_local_syms(abfd, isymbuf); + } + + htab->symbols_adjusted = TRUE; + return TRUE; +} + +static bfd_boolean +adjust_relocs(bfd *abfd, asection *sec, struct bfd_link_info *info) +{ + struct avr32_relax_data *rd; + Elf_Internal_Rela *relocs; + Elf_Internal_Shdr *symtab_hdr; + unsigned int i; + bfd_boolean ret = FALSE; + + rd = avr32_relax_data(sec); + if (!rd->reloc_data) + return TRUE; + + RDBG("adjust_relocs: %s<%s> (count: %u)\n", abfd->filename, sec->name, + sec->reloc_count); + + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory); + if (!relocs) + return FALSE; + + symtab_hdr = &elf_tdata(abfd)->symtab_hdr; + + for (i = 0; i < sec->reloc_count; i++) + { + Elf_Internal_Rela *rela = &relocs[i]; + struct avr32_reloc_data *r_data = &rd->reloc_data[i]; + struct fragment *sym_frag; + unsigned long r_symndx; + + if (r_data->add_frag) + { + r_symndx = ELF_R_SYM(rela->r_info); + + if (r_symndx < symtab_hdr->sh_info) + sym_frag = elf_tdata(abfd)->local_sym_frag[r_symndx]; + else + { + struct elf_link_hash_entry *h; + + h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *)h->root.u.i.link; + + BFD_ASSERT(h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak); + + sym_frag = ((struct elf_avr32_link_hash_entry *)h)->sym_frag; + } + + RDBG(" addend: 0x%08lx -> 0x%08lx\n", + rela->r_addend, + rela->r_addend + r_data->add_frag->offset_adjust + - (sym_frag ? sym_frag->offset_adjust : 0)); + + /* If this is against a section symbol, we won't find any + sym_frag, so we'll just adjust the addend. */ + rela->r_addend += r_data->add_frag->offset_adjust; + if (sym_frag) + rela->r_addend -= sym_frag->offset_adjust; + + if (r_data->sub_frag) + { + bfd_byte *contents; + bfd_signed_vma diff; + + contents = retrieve_contents(abfd, sec, info->keep_memory); + if (!contents) + goto out; + + /* I realize now that sub_frag is misnamed. It's + actually add_frag which is subtracted in this + case... */ + diff = bfd_get_32(abfd, contents + rela->r_offset); + diff += (r_data->sub_frag->offset_adjust + - r_data->add_frag->offset_adjust); + bfd_put_32(abfd, diff, contents + rela->r_offset); + + RDBG(" 0x%lx: DIFF32 updated: 0x%lx\n", rela->r_offset, diff); + + release_contents(sec, contents); + } + } + else + BFD_ASSERT(!r_data->sub_frag); + } + + ret = TRUE; + + out: + release_internal_relocs(sec, relocs); + return ret; +} + +static bfd_boolean +avr32_move_data(bfd *abfd, asection *sec, struct bfd_link_info *info) +{ + struct elf_avr32_link_hash_table *htab; + struct avr32_relax_data *rd; + struct fragment *frag, *fragend; + Elf_Internal_Rela *relocs = NULL; + bfd_byte *contents = NULL; + unsigned int i; + bfd_boolean ret = FALSE; + + htab = avr32_elf_hash_table(info); + rd = avr32_relax_data(sec); + + if (!htab->symbols_adjusted) + if (!adjust_syms(info)) + return FALSE; + + if (rd->is_relaxable) + { + /* Resize the section first, so that we can be sure that enough + memory is allocated in case the section has grown. */ + if (sec->size > sec->rawsize + && elf_section_data(sec)->this_hdr.contents) + { + /* We must not use cached data if the section has grown. */ + free(elf_section_data(sec)->this_hdr.contents); + elf_section_data(sec)->this_hdr.contents = NULL; + } + + relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory); + if (!relocs) + goto out; + contents = retrieve_contents(abfd, sec, info->keep_memory); + if (!contents) + goto out; + + fragend = rd->frag + rd->frag_count; + + RDBG("move_data: %s<%s>: relocs=%p, contents=%p\n", + abfd->filename, sec->name, relocs, contents); + + /* First, move the data into place. We must take care to move + frags in the right order so that we don't accidentally + overwrite parts of the next frag. */ + for (frag = rd->frag; frag < fragend; frag++) + { + RDBG(" 0x%08lx%c0x%x: size 0x%lx%c0x%x\n", + frag->offset, frag->offset_adjust >= 0 ? '+' : '-', + abs(frag->offset_adjust), + frag->size, frag->size_adjust >= 0 ? '+' : '-', + abs(frag->size_adjust)); + if (frag->offset_adjust > 0) + { + struct fragment *prev = frag - 1; + struct fragment *last; + + for (last = frag; last < fragend && last->offset_adjust > 0; + last++) ; + + if (last == fragend) + last--; + + for (frag = last; frag != prev; frag--) + { + if (frag->offset_adjust + && frag->size + frag->size_adjust > 0) + { + RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n", + frag->offset, frag->offset + frag->offset_adjust, + frag->size + frag->size_adjust); + memmove(contents + frag->offset + frag->offset_adjust, + contents + frag->offset, + frag->size + frag->size_adjust); + } + } + frag = last; + } + else if (frag->offset_adjust && frag->size + frag->size_adjust > 0) + { + RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n", + frag->offset, frag->offset + frag->offset_adjust, + frag->size + frag->size_adjust); + memmove(contents + frag->offset + frag->offset_adjust, + contents + frag->offset, + frag->size + frag->size_adjust); + } + } + + i = 0; + + for (frag = rd->frag; frag < fragend; frag++) + { + const struct relax_state *state, *istate; + struct avr32_reloc_data *r_data = NULL; + + istate = &relax_state[frag->initial_state]; + state = &relax_state[frag->state]; + + if (rd->reloc_data) + r_data = &rd->reloc_data[frag->rela - relocs]; + + BFD_ASSERT((long)(frag->size + frag->size_adjust) >= 0); + BFD_ASSERT(state->reftype != REF_CPOOL + || r_data->add_frag->refcount > 0); + + if (istate->reftype == REF_CPOOL && state->reftype != REF_CPOOL) + { + struct fragment *ifrag; + + /* An indirect reference through the cpool has been + converted to a direct reference. We must update the + reloc to point to the symbol itself instead of the + constant pool entry. The reloc type will be updated + later. */ + ifrag = r_data->add_frag; + frag->rela->r_info = ifrag->rela->r_info; + frag->rela->r_addend = ifrag->rela->r_addend; + + /* Copy the reloc data so the addend will be adjusted + correctly later. */ + *r_data = rd->reloc_data[ifrag->rela - relocs]; + } + + /* Move all relocs covered by this frag. */ + if (frag->rela) + BFD_ASSERT(&relocs[i] <= frag->rela); + else + BFD_ASSERT((frag + 1) == fragend && frag->state == RS_NONE); + + if (frag == rd->frag) + BFD_ASSERT(i == 0); + else + BFD_ASSERT(&relocs[i] > frag[-1].rela); + + /* If non-null, frag->rela is the last relocation in the + fragment. frag->rela can only be null in the last + fragment, so in that case, we'll just do the rest. */ + for (; (i < sec->reloc_count + && (!frag->rela || &relocs[i] <= frag->rela)); i++) + { + RDBG("[%4u] r_offset 0x%08lx -> 0x%08lx\n", i, relocs[i].r_offset, + relocs[i].r_offset + frag->offset_adjust); + relocs[i].r_offset += frag->offset_adjust; + } + + if (frag->refcount == 0) + { + /* If this frag is to be discarded, make sure we won't + relocate it later on. */ + BFD_ASSERT(frag->state == RS_CPENT); + frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info), + R_AVR32_NONE); + } + else if (frag->state == RS_ALIGN) + { + bfd_vma addr, addr_end; + + addr = frag->rela->r_offset; + addr_end = (frag->offset + frag->offset_adjust + + frag->size + frag->size_adjust); + + /* If the section is executable, insert NOPs. + Otherwise, insert zeroes. */ + if (sec->flags & SEC_CODE) + { + if (addr & 1) + { + bfd_put_8(abfd, 0, contents + addr); + addr++; + } + + BFD_ASSERT(!((addr_end - addr) & 1)); + + while (addr < addr_end) + { + bfd_put_16(abfd, NOP_OPCODE, contents + addr); + addr += 2; + } + } + else + memset(contents + addr, 0, addr_end - addr); + } + else if (state->opcode_mask) + { + bfd_vma insn; + + /* Update the opcode and the relocation type unless it's a + "special" relax state (i.e. RS_NONE, RS_ALIGN or + RS_CPENT.), in which case the opcode mask is zero. */ + insn = bfd_get_32(abfd, contents + frag->rela->r_offset); + insn &= ~state->opcode_mask; + insn |= state->opcode; + RDBG(" 0x%lx: inserting insn %08lx\n", + frag->rela->r_offset, insn); + bfd_put_32(abfd, insn, contents + frag->rela->r_offset); + + frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info), + state->r_type); + } + + if ((frag + 1) == fragend) + BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust + + frag->size_adjust) == sec->size); + else + BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust + + frag->size_adjust) + == (frag[1].offset + frag[1].offset_adjust)); + } + } + + /* Adjust reloc addends and DIFF32 differences */ + if (!adjust_relocs(abfd, sec, info)) + return FALSE; + + ret = TRUE; + + out: + release_contents(sec, contents); + release_internal_relocs(sec, relocs); + return ret; +} + +static bfd_boolean +avr32_elf_relax_section(bfd *abfd, asection *sec, + struct bfd_link_info *info, bfd_boolean *again) +{ + struct elf_avr32_link_hash_table *htab; + struct avr32_relax_data *rd; + + *again = FALSE; + if (info->relocatable) + return TRUE; + + htab = avr32_elf_hash_table(info); + if ((!(sec->flags & SEC_RELOC) || sec->reloc_count == 0) + && sec != htab->sgot) + return TRUE; + + if (!htab->relocations_analyzed) + { + if (!analyze_relocations(info)) + return FALSE; + htab->relocations_analyzed = TRUE; + } + + rd = avr32_relax_data(sec); + + if (rd->iteration != htab->relax_iteration) + { + if (!htab->repeat_pass) + htab->relax_pass++; + htab->relax_iteration++; + htab->repeat_pass = FALSE; + } + + rd->iteration++; + + switch (htab->relax_pass) + { + case RELAX_PASS_SIZE_FRAGS: + if (!avr32_size_frags(abfd, sec, info)) + return FALSE; + *again = TRUE; + break; + case RELAX_PASS_MOVE_DATA: + if (!avr32_move_data(abfd, sec, info)) + return FALSE; + break; + } + + return TRUE; +} + + +/* Relocation */ + +static bfd_reloc_status_type +avr32_check_reloc_value(asection *sec, Elf_Internal_Rela *rela, + bfd_signed_vma relocation, reloc_howto_type *howto); +static bfd_reloc_status_type +avr32_final_link_relocate(reloc_howto_type *howto, bfd *input_bfd, + asection *input_section, bfd_byte *contents, + Elf_Internal_Rela *rel, bfd_vma value); +static bfd_boolean +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info, + bfd *input_bfd, asection *input_section, + bfd_byte *contents, Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections); + + +#define symbol_address(symbol) \ + symbol->value + symbol->section->output_section->vma \ + + symbol->section->output_offset + +#define avr32_elf_insert_field(size, field, abfd, reloc_entry, data) \ + do \ + { \ + unsigned long x; \ + x = bfd_get_##size (abfd, data + reloc_entry->address); \ + x &= ~reloc_entry->howto->dst_mask; \ + x |= field & reloc_entry->howto->dst_mask; \ + bfd_put_##size (abfd, (bfd_vma) x, data + reloc_entry->address); \ + } \ + while(0) + +static bfd_reloc_status_type +avr32_check_reloc_value(asection *sec ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rela ATTRIBUTE_UNUSED, + bfd_signed_vma relocation, + reloc_howto_type *howto) +{ + bfd_vma reloc_u; + + /* We take "complain_overflow_dont" to mean "don't complain on + alignment either". This way, we don't have to special-case + R_AVR32_HI16 */ + if (howto->complain_on_overflow == complain_overflow_dont) + return bfd_reloc_ok; + + /* Check if the value is correctly aligned */ + if (relocation & ((1 << howto->rightshift) - 1)) + { + RDBG("misaligned: %s<%s+%lx>: %s: 0x%lx (align %u)\n", + sec->owner->filename, sec->name, rela->r_offset, + howto->name, relocation, howto->rightshift); + return bfd_reloc_overflow; + } + + /* Now, get rid of the unnecessary bits */ + relocation >>= howto->rightshift; + reloc_u = (bfd_vma)relocation; + + switch (howto->complain_on_overflow) + { + case complain_overflow_unsigned: + case complain_overflow_bitfield: + if (reloc_u > (unsigned long)((1 << howto->bitsize) - 1)) + { + RDBG("unsigned overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n", + sec->owner->filename, sec->name, rela->r_offset, + howto->name, reloc_u, howto->bitsize); + RDBG("reloc vma: 0x%lx\n", + sec->output_section->vma + sec->output_offset + rela->r_offset); + + return bfd_reloc_overflow; + } + break; + case complain_overflow_signed: + if (relocation > (1 << (howto->bitsize - 1)) - 1) + { + RDBG("signed overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n", + sec->owner->filename, sec->name, rela->r_offset, + howto->name, reloc_u, howto->bitsize); + RDBG("reloc vma: 0x%lx\n", + sec->output_section->vma + sec->output_offset + rela->r_offset); + + return bfd_reloc_overflow; + } + if (relocation < -(1 << (howto->bitsize - 1))) + { + RDBG("signed overflow: %s<%s+%lx>: %s: -0x%lx (size %u)\n", + sec->owner->filename, sec->name, rela->r_offset, + howto->name, -relocation, howto->bitsize); + RDBG("reloc vma: 0x%lx\n", + sec->output_section->vma + sec->output_offset + rela->r_offset); + + return bfd_reloc_overflow; + } + break; + default: + abort(); + } + + return bfd_reloc_ok; +} + + +static bfd_reloc_status_type +avr32_final_link_relocate(reloc_howto_type *howto, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *rel, + bfd_vma value) +{ + bfd_vma field; + bfd_vma relocation; + bfd_reloc_status_type status; + bfd_byte *p = contents + rel->r_offset; + unsigned long x; + + pr_debug(" (6b) final link relocate\n"); + + /* Sanity check the address */ + if (rel->r_offset > input_section->size) + { + (*_bfd_error_handler) + ("%B: %A+0x%lx: offset out of range (section size: 0x%lx)", + input_bfd, input_section, rel->r_offset, input_section->size); + return bfd_reloc_outofrange; + } + + relocation = value + rel->r_addend; + + if (howto->pc_relative) + { + bfd_vma addr; + + addr = input_section->output_section->vma + + input_section->output_offset + rel->r_offset; + addr &= ~0UL << howto->rightshift; + relocation -= addr; + } + + switch (ELF32_R_TYPE(rel->r_info)) + { + case R_AVR32_16N_PCREL: + /* sub reg, pc, . - (sym + addend) */ + relocation = -relocation; + break; + } + + status = avr32_check_reloc_value(input_section, rel, relocation, howto); + + relocation >>= howto->rightshift; + if (howto->bitsize == 21) + field = (relocation & 0xffff) + | ((relocation & 0x10000) << 4) + | ((relocation & 0x1e0000) << 8); + else if (howto->bitsize == 12) + field = (relocation & 0xff) | ((relocation & 0xf00) << 4); + else if (howto->bitsize == 10) + field = ((relocation & 0xff) << 4) + | ((relocation & 0x300) >> 8); + else + field = relocation << howto->bitpos; + + switch (howto->size) + { + case 0: + x = bfd_get_8 (input_bfd, p); + x &= ~howto->dst_mask; + x |= field & howto->dst_mask; + bfd_put_8 (input_bfd, (bfd_vma) x, p); + break; + case 1: + x = bfd_get_16 (input_bfd, p); + x &= ~howto->dst_mask; + x |= field & howto->dst_mask; + bfd_put_16 (input_bfd, (bfd_vma) x, p); + break; + case 2: + x = bfd_get_32 (input_bfd, p); + x &= ~howto->dst_mask; + x |= field & howto->dst_mask; + bfd_put_32 (input_bfd, (bfd_vma) x, p); + break; + default: + abort(); + } + + return status; +} + +/* (6) Apply relocations to the normal (non-dynamic) sections */ + +static bfd_boolean +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info, + bfd *input_bfd, asection *input_section, + bfd_byte *contents, Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) +{ + struct elf_avr32_link_hash_table *htab; + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Rela *rel, *relend; + struct elf_link_hash_entry **sym_hashes; + struct got_entry **local_got_ents; + asection *sgot; + asection *srelgot; + asection *sreldyn; + + pr_debug("(6) relocate section %s:<%s> (size 0x%lx)\n", + input_bfd->filename, input_section->name, input_section->size); + + /* If we're doing a partial link, we don't have to do anything since + we're using RELA relocations */ + if (info->relocatable) + return TRUE; + + htab = avr32_elf_hash_table(info); + symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes(input_bfd); + local_got_ents = elf_local_got_ents(input_bfd); + sgot = htab->sgot; + srelgot = htab->srelgot; + sreldyn = htab->sreldyn; + + relend = relocs + input_section->reloc_count; + for (rel = relocs; rel < relend; rel++) + { + unsigned long r_type, r_symndx; + reloc_howto_type *howto; + Elf_Internal_Sym *sym = NULL; + struct elf_link_hash_entry *h = NULL; + asection *sec = NULL; + bfd_vma value; + bfd_vma offset; + bfd_reloc_status_type status; + + r_type = ELF32_R_TYPE(rel->r_info); + r_symndx = ELF32_R_SYM(rel->r_info); + + if (r_type == R_AVR32_NONE + || r_type == R_AVR32_ALIGN + || r_type == R_AVR32_DIFF32 + || r_type == R_AVR32_DIFF16 + || r_type == R_AVR32_DIFF8) + continue; + + /* Sanity check */ + if (r_type > R_AVR32_max) + { + bfd_set_error(bfd_error_bad_value); + return FALSE; + } + + howto = &elf_avr32_howto_table[r_type]; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + + pr_debug(" (6a) processing %s against local symbol %lu\n", + howto->name, r_symndx); + + /* The following function changes rel->r_addend behind our back. */ + value = _bfd_elf_rela_local_sym(output_bfd, sym, &sec, rel); + pr_debug(" => value: %lx, addend: %lx\n", value, rel->r_addend); + } + else + { + if (sym_hashes == NULL) + return FALSE; + + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *)h->root.u.i.link; + + pr_debug(" (6a) processing %s against symbol %s\n", + howto->name, h->root.root.string); + + if (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + { + bfd_boolean dyn; + + dyn = htab->root.dynamic_sections_created; + sec = h->root.u.def.section; + + if (sec->output_section) + value = (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset); + else + value = h->root.u.def.value; + } + else if (h->root.type == bfd_link_hash_undefweak) + value = 0; + else if (info->unresolved_syms_in_objects == RM_IGNORE + && ELF_ST_VISIBILITY(h->other) == STV_DEFAULT) + value = 0; + else + { + bfd_boolean err; + err = (info->unresolved_syms_in_objects == RM_GENERATE_ERROR + || ELF_ST_VISIBILITY(h->other) != STV_DEFAULT); + if (!info->callbacks->undefined_symbol + (info, h->root.root.string, input_bfd, + input_section, rel->r_offset, err)) + return FALSE; + value = 0; + } + + pr_debug(" => value: %lx, addend: %lx\n", value, rel->r_addend); + } + + switch (r_type) + { + case R_AVR32_GOT32: + case R_AVR32_GOT16: + case R_AVR32_GOT8: + case R_AVR32_GOT21S: + case R_AVR32_GOT18SW: + case R_AVR32_GOT16S: + case R_AVR32_GOT7UW: + case R_AVR32_LDA_GOT: + case R_AVR32_GOTCALL: + BFD_ASSERT(sgot != NULL); + + if (h != NULL) + { + BFD_ASSERT(h->got.glist->refcount > 0); + offset = h->got.glist->offset; + + BFD_ASSERT(offset < sgot->size); + if (!elf_hash_table(info)->dynamic_sections_created + || (h->def_regular + && (!info->shared + || info->symbolic + || h->dynindx == -1))) + { + /* This is actually a static link, or it is a + -Bsymbolic link and the symbol is defined + locally, or the symbol was forced to be local. */ + bfd_put_32(output_bfd, value, sgot->contents + offset); + } + } + else + { + BFD_ASSERT(local_got_ents && + local_got_ents[r_symndx]->refcount > 0); + offset = local_got_ents[r_symndx]->offset; + + /* Local GOT entries don't have relocs. If this is a + shared library, the dynamic linker will add the load + address to the initial value at startup. */ + BFD_ASSERT(offset < sgot->size); + pr_debug("Initializing GOT entry at offset %lu: 0x%lx\n", + offset, value); + bfd_put_32 (output_bfd, value, sgot->contents + offset); + } + + value = sgot->output_offset + offset; + pr_debug("GOT reference: New value %lx\n", value); + break; + + case R_AVR32_GOTPC: + /* This relocation type is for constant pool entries used in + the calculation "Rd = PC - (PC - GOT)", where the + constant pool supplies the constant (PC - GOT) + offset. The symbol value + addend indicates where the + value of PC is taken. */ + value -= sgot->output_section->vma; + break; + + case R_AVR32_32_PCREL: + /* We must adjust r_offset to account for discarded data in + the .eh_frame section. This is probably not the right + way to do this, since AFAICS all other architectures do + it some other way. I just can't figure out how... */ + { + bfd_vma r_offset; + + r_offset = _bfd_elf_section_offset(output_bfd, info, + input_section, + rel->r_offset); + if (r_offset == (bfd_vma)-1 + || r_offset == (bfd_vma)-2) + continue; + rel->r_offset = r_offset; + } + break; + + case R_AVR32_32: + /* We need to emit a run-time relocation in the following cases: + - we're creating a shared library + - the symbol is not defined in any regular objects + + Of course, sections that aren't going to be part of the + run-time image will not get any relocs, and undefined + symbols won't have any either (only weak undefined + symbols should get this far). */ + if ((info->shared + || (elf_hash_table(info)->dynamic_sections_created + && h != NULL + && h->def_dynamic + && !h->def_regular)) + && r_symndx != 0 + && (input_section->flags & SEC_ALLOC)) + { + Elf_Internal_Rela outrel; + bfd_byte *loc; + bfd_boolean skip, relocate; + struct elf_avr32_link_hash_entry *avrh; + + pr_debug("Going to generate dynamic reloc...\n"); + + skip = FALSE; + relocate = FALSE; + + outrel.r_offset = _bfd_elf_section_offset(output_bfd, info, + input_section, + rel->r_offset); + if (outrel.r_offset == (bfd_vma)-1) + skip = TRUE; + else if (outrel.r_offset == (bfd_vma)-2) + skip = TRUE, relocate = TRUE; + + outrel.r_offset += (input_section->output_section->vma + + input_section->output_offset); + + pr_debug(" ... offset %lx, dynindx %ld\n", + outrel.r_offset, h ? h->dynindx : -1); + + if (skip) + memset(&outrel, 0, sizeof(outrel)); + else + { + avrh = (struct elf_avr32_link_hash_entry *)h; + /* h->dynindx may be -1 if this symbol was marked to + become local. */ + if (h == NULL + || ((info->symbolic || h->dynindx == -1) + && h->def_regular)) + { + relocate = TRUE; + outrel.r_info = ELF32_R_INFO(0, R_AVR32_RELATIVE); + outrel.r_addend = value + rel->r_addend; + pr_debug(" ... R_AVR32_RELATIVE\n"); + } + else + { + BFD_ASSERT(h->dynindx != -1); + relocate = TRUE; + outrel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT); + outrel.r_addend = rel->r_addend; + pr_debug(" ... R_AVR32_GLOB_DAT\n"); + } + } + + pr_debug("sreldyn reloc_count: %d, size %lu\n", + sreldyn->reloc_count, sreldyn->size); + + loc = sreldyn->contents; + loc += sreldyn->reloc_count++ * sizeof(Elf32_External_Rela); + bfd_elf32_swap_reloca_out(output_bfd, &outrel, loc); + + BFD_ASSERT(sreldyn->reloc_count * sizeof(Elf32_External_Rela) + <= sreldyn->size); + + if (!relocate) + continue; + } + break; + } + + status = avr32_final_link_relocate(howto, input_bfd, input_section, + contents, rel, value); + + switch (status) + { + case bfd_reloc_ok: + break; + + case bfd_reloc_overflow: + { + const char *name; + + if (h != NULL) + name = h->root.root.string; + else + { + name = bfd_elf_string_from_elf_section(input_bfd, + symtab_hdr->sh_link, + sym->st_name); + if (name == NULL) + return FALSE; + if (*name == '\0') + name = bfd_section_name(input_bfd, sec); + } + if (!((*info->callbacks->reloc_overflow) + (info, (h ? &h->root : NULL), name, howto->name, + rel->r_addend, input_bfd, input_section, rel->r_offset))) + return FALSE; + } + break; + + case bfd_reloc_outofrange: + default: + abort(); + } + } + + return TRUE; +} + + +/* Additional processing of dynamic sections after relocation */ + +static bfd_boolean +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym); +static bfd_boolean +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info); + + +/* (7) Initialize the contents of a dynamic symbol and/or emit + relocations for it */ + +static bfd_boolean +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + struct elf_avr32_link_hash_table *htab; + struct got_entry *got; + + pr_debug("(7) finish dynamic symbol: %s\n", h->root.root.string); + + htab = avr32_elf_hash_table(info); + got = h->got.glist; + + if (got && got->refcount > 0) + { + asection *sgot; + asection *srelgot; + Elf_Internal_Rela rel; + bfd_byte *loc; + + /* This symbol has an entry in the GOT. Set it up. */ + sgot = htab->sgot; + srelgot = htab->srelgot; + BFD_ASSERT(sgot && srelgot); + + rel.r_offset = (sgot->output_section->vma + + sgot->output_offset + + got->offset); + + /* If this is a static link, or it is a -Bsymbolic link and the + symbol is defined locally or was forced to be local because + of a version file, we just want to emit a RELATIVE reloc. The + entry in the global offset table will already have been + initialized in the relocate_section function. */ + if ((info->shared + && !info->symbolic + && h->dynindx != -1) + || (htab->root.dynamic_sections_created + && h->def_dynamic + && !h->def_regular)) + { + bfd_put_32(output_bfd, 0, sgot->contents + got->offset); + rel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT); + rel.r_addend = 0; + + pr_debug("GOT reloc R_AVR32_GLOB_DAT, dynindx: %ld\n", h->dynindx); + pr_debug(" srelgot reloc_count: %d, size: %lu\n", + srelgot->reloc_count, srelgot->size); + + loc = (srelgot->contents + + srelgot->reloc_count++ * sizeof(Elf32_External_Rela)); + bfd_elf32_swap_reloca_out(output_bfd, &rel, loc); + + BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela) + <= srelgot->size); + } + } + + /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute */ + if (strcmp(h->root.root.string, "_DYNAMIC") == 0 + || strcmp(h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0) + sym->st_shndx = SHN_ABS; + + return TRUE; +} + +/* (8) Do any remaining initialization of the dynamic sections */ + +static bfd_boolean +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info) +{ + struct elf_avr32_link_hash_table *htab; + asection *sgot, *sdyn; + + pr_debug("(8) finish dynamic sections\n"); + + htab = avr32_elf_hash_table(info); + sgot = htab->sgot; + sdyn = bfd_get_section_by_name(htab->root.dynobj, ".dynamic"); + + if (htab->root.dynamic_sections_created) + { + Elf32_External_Dyn *dyncon, *dynconend; + + BFD_ASSERT(sdyn && sgot && sgot->size >= AVR32_GOT_HEADER_SIZE); + + dyncon = (Elf32_External_Dyn *)sdyn->contents; + dynconend = (Elf32_External_Dyn *)(sdyn->contents + sdyn->size); + for (; dyncon < dynconend; dyncon++) + { + Elf_Internal_Dyn dyn; + asection *s; + + bfd_elf32_swap_dyn_in(htab->root.dynobj, dyncon, &dyn); + + switch (dyn.d_tag) + { + default: + break; + + case DT_PLTGOT: + s = sgot->output_section; + BFD_ASSERT(s != NULL); + dyn.d_un.d_ptr = s->vma; + bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon); + break; + + case DT_AVR32_GOTSZ: + s = sgot->output_section; + BFD_ASSERT(s != NULL); + dyn.d_un.d_val = s->size; + bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon); + break; + } + } + + /* Fill in the first two entries in the global offset table */ + bfd_put_32(output_bfd, + sdyn->output_section->vma + sdyn->output_offset, + sgot->contents); + + /* The runtime linker will fill this one in with the address of + the run-time link map */ + bfd_put_32(output_bfd, 0, sgot->contents + 4); + } + + if (sgot) + elf_section_data(sgot->output_section)->this_hdr.sh_entsize = 4; + + return TRUE; +} + + +/* AVR32-specific private ELF data */ + +static bfd_boolean +avr32_elf_set_private_flags(bfd *abfd, flagword flags); +static bfd_boolean +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd); +static bfd_boolean +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd); +static bfd_boolean +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr); + +static bfd_boolean +avr32_elf_set_private_flags(bfd *abfd, flagword flags) +{ + elf_elfheader(abfd)->e_flags = flags; + elf_flags_init(abfd) = TRUE; + + return TRUE; +} + +/* Copy backend specific data from one object module to another. */ + +static bfd_boolean +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd) +{ + elf_elfheader(obfd)->e_flags = elf_elfheader(ibfd)->e_flags; + return TRUE; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static bfd_boolean +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd) +{ + flagword out_flags, in_flags; + + pr_debug("(0) merge_private_bfd_data: %s -> %s\n", + ibfd->filename, obfd->filename); + + in_flags = elf_elfheader(ibfd)->e_flags; + out_flags = elf_elfheader(obfd)->e_flags; + + if (elf_flags_init(obfd)) + { + /* If one of the inputs are non-PIC, the output must be + considered non-PIC. The same applies to linkrelax. */ + if (!(in_flags & EF_AVR32_PIC)) + out_flags &= ~EF_AVR32_PIC; + if (!(in_flags & EF_AVR32_LINKRELAX)) + out_flags &= ~EF_AVR32_LINKRELAX; + } + else + { + elf_flags_init(obfd) = TRUE; + out_flags = in_flags; + } + + elf_elfheader(obfd)->e_flags = out_flags; + + return TRUE; +} + +static bfd_boolean +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr) +{ + FILE *file = (FILE *)ptr; + unsigned long flags; + + BFD_ASSERT(abfd != NULL && ptr != NULL); + + _bfd_elf_print_private_bfd_data(abfd, ptr); + + flags = elf_elfheader(abfd)->e_flags; + + fprintf(file, _("private flags = %lx:"), elf_elfheader(abfd)->e_flags); + + if (flags & EF_AVR32_PIC) + fprintf(file, " [PIC]"); + if (flags & EF_AVR32_LINKRELAX) + fprintf(file, " [linker relaxable]"); + + flags &= ~(EF_AVR32_PIC | EF_AVR32_LINKRELAX); + + if (flags) + fprintf(file, _("")); + + fputc('\n', file); + + return TRUE; +} + + +/* Understanding core dumps */ + +static bfd_boolean +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note); +static bfd_boolean +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note); + +static bfd_boolean +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note) +{ + /* Linux/AVR32B elf_prstatus */ + if (note->descsz != 148) + return FALSE; + + /* pr_cursig */ + elf_tdata(abfd)->core_signal = bfd_get_16(abfd, note->descdata + 12); + + /* pr_pid */ + elf_tdata(abfd)->core_pid = bfd_get_32(abfd, note->descdata + 24); + + /* Make a ".reg/999" section for pr_reg. The size is for 16 + general-purpose registers, SR and r12_orig (18 * 4 = 72). */ + return _bfd_elfcore_make_pseudosection(abfd, ".reg", 72, + note->descpos + 72); +} + +static bfd_boolean +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note) +{ + /* Linux/AVR32B elf_prpsinfo */ + if (note->descsz != 128) + return FALSE; + + elf_tdata(abfd)->core_program + = _bfd_elfcore_strndup(abfd, note->descdata + 32, 16); + elf_tdata(abfd)->core_command + = _bfd_elfcore_strndup(abfd, note->descdata + 48, 80); + + /* Note that for some reason, a spurious space is tacked + onto the end of the args in some (at least one anyway) + implementations, so strip it off if it exists. */ + + { + char *command = elf_tdata (abfd)->core_command; + int n = strlen (command); + + if (0 < n && command[n - 1] == ' ') + command[n - 1] = '\0'; + } + + return TRUE; +} + + +#define ELF_ARCH bfd_arch_avr32 +#define ELF_MACHINE_CODE EM_AVR32 +#define ELF_MAXPAGESIZE 0x1000 + +#define TARGET_BIG_SYM bfd_elf32_avr32_vec +#define TARGET_BIG_NAME "elf32-avr32" + +#define elf_backend_grok_prstatus avr32_elf_grok_prstatus +#define elf_backend_grok_psinfo avr32_elf_grok_psinfo + +/* Only RELA relocations are used */ +#define elf_backend_may_use_rel_p 0 +#define elf_backend_may_use_rela_p 1 +#define elf_backend_default_use_rela_p 1 +#define elf_backend_rela_normal 1 +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto avr32_info_to_howto + +#define bfd_elf32_bfd_copy_private_bfd_data avr32_elf_copy_private_bfd_data +#define bfd_elf32_bfd_merge_private_bfd_data avr32_elf_merge_private_bfd_data +#define bfd_elf32_bfd_set_private_flags avr32_elf_set_private_flags +#define bfd_elf32_bfd_print_private_bfd_data avr32_elf_print_private_bfd_data +#define bfd_elf32_new_section_hook avr32_elf_new_section_hook + +#define elf_backend_gc_mark_hook avr32_elf_gc_mark_hook +#define elf_backend_gc_sweep_hook avr32_elf_gc_sweep_hook +#define elf_backend_relocate_section avr32_elf_relocate_section +#define elf_backend_copy_indirect_symbol avr32_elf_copy_indirect_symbol +#define elf_backend_create_dynamic_sections avr32_elf_create_dynamic_sections +#define bfd_elf32_bfd_link_hash_table_create avr32_elf_link_hash_table_create +#define elf_backend_adjust_dynamic_symbol avr32_elf_adjust_dynamic_symbol +#define elf_backend_size_dynamic_sections avr32_elf_size_dynamic_sections +#define elf_backend_finish_dynamic_symbol avr32_elf_finish_dynamic_symbol +#define elf_backend_finish_dynamic_sections avr32_elf_finish_dynamic_sections + +#define bfd_elf32_bfd_relax_section avr32_elf_relax_section + +/* Find out which symbols need an entry in .got. */ +#define elf_backend_check_relocs avr32_check_relocs +#define elf_backend_can_refcount 1 +#define elf_backend_can_gc_sections 1 +#define elf_backend_plt_readonly 1 +#define elf_backend_plt_not_loaded 1 +#define elf_backend_want_plt_sym 0 +#define elf_backend_plt_alignment 2 +#define elf_backend_want_dynbss 0 +#define elf_backend_want_got_plt 0 +#define elf_backend_want_got_sym 1 +#define elf_backend_got_header_size AVR32_GOT_HEADER_SIZE + +#include "elf32-target.h" Index: binutils-2.16.1-avr32/bfd/reloc.c =================================================================== --- binutils-2.16.1-avr32.orig/bfd/reloc.c 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/bfd/reloc.c 2006-06-30 09:49:14.000000000 +0200 @@ -3455,6 +3455,129 @@ ENUMDOC instructions ENUM + BFD_RELOC_AVR32_DIFF32 +ENUMX + BFD_RELOC_AVR32_DIFF16 +ENUMX + BFD_RELOC_AVR32_DIFF8 +ENUMDOC + Difference between two labels: L2 - L1. The value of L1 is encoded + as sym + addend, while the initial difference after assembly is + inserted into the object file by the assembler. +ENUM + BFD_RELOC_AVR32_GOT32 +ENUMX + BFD_RELOC_AVR32_GOT16 +ENUMX + BFD_RELOC_AVR32_GOT8 +ENUMDOC + Reference to a symbol through the Global Offset Table. The linker + will allocate an entry for symbol in the GOT and insert the offset + of this entry as the relocation value. +ENUM + BFD_RELOC_AVR32_21S +ENUMX + BFD_RELOC_AVR32_16U +ENUMX + BFD_RELOC_AVR32_16S +ENUMX + BFD_RELOC_AVR32_SUB5 +ENUMX + BFD_RELOC_AVR32_8S_EXT +ENUMX + BFD_RELOC_AVR32_8S +ENUMDOC + Normal (non-pc-relative) code relocations. Alignment and signedness + is indicated by the suffixes. S means signed, U means unsigned. W + means word-aligned, H means halfword-aligned, neither means + byte-aligned (no alignment.) SUB5 is the same relocation as 16S. +ENUM + BFD_RELOC_AVR32_22H_PCREL +ENUMX + BFD_RELOC_AVR32_18W_PCREL +ENUMX + BFD_RELOC_AVR32_16B_PCREL +ENUMX + BFD_RELOC_AVR32_16N_PCREL +ENUMX + BFD_RELOC_AVR32_14UW_PCREL +ENUMX + BFD_RELOC_AVR32_11H_PCREL +ENUMX + BFD_RELOC_AVR32_10UW_PCREL +ENUMX + BFD_RELOC_AVR32_9H_PCREL +ENUMX + BFD_RELOC_AVR32_9UW_PCREL +ENUMDOC + PC-relative relocations are signed if neither 'U' nor 'S' is + specified. However, we explicitly tack on a 'B' to indicate no + alignment, to avoid confusion with data relocs. All of these resolve + to sym + addend - offset, except the one with 'N' (negated) suffix. + This particular one resolves to offset - sym - addend. +ENUM + BFD_RELOC_AVR32_GOTPC +ENUMDOC + Subtract the link-time address of the GOT from (symbol + addend) + and insert the result. +ENUM + BFD_RELOC_AVR32_GOTCALL +ENUMX + BFD_RELOC_AVR32_LDA_GOT +ENUMX + BFD_RELOC_AVR32_GOT21S +ENUMX + BFD_RELOC_AVR32_GOT18SW +ENUMX + BFD_RELOC_AVR32_GOT16S +ENUMDOC + Reference to a symbol through the GOT. The linker will allocate an + entry for symbol in the GOT and insert the offset of this entry as + the relocation value. addend must be zero. As usual, 'S' means + signed, 'W' means word-aligned, etc. +ENUM + BFD_RELOC_AVR32_32_CPENT +ENUMDOC + 32-bit constant pool entry. I don't think 8- and 16-bit entries make + a whole lot of sense. +ENUM + BFD_RELOC_AVR32_CPCALL +ENUMX + BFD_RELOC_AVR32_16_CP +ENUMX + BFD_RELOC_AVR32_9W_CP +ENUMDOC + Constant pool references. Some of these relocations are signed, + others are unsigned. It doesn't really matter, since the constant + pool always comes after the code that references it. +ENUM + BFD_RELOC_AVR32_ALIGN +ENUMDOC + sym must be the absolute symbol. The addend specifies the alignment + order, e.g. if addend is 2, the linker must add padding so that the + next address is aligned to a 4-byte boundary. +ENUM + BFD_RELOC_AVR32_14UW +ENUMX + BFD_RELOC_AVR32_10UW +ENUMX + BFD_RELOC_AVR32_10SW +ENUMX + BFD_RELOC_AVR32_STHH_W +ENUMX + BFD_RELOC_AVR32_7UW +ENUMX + BFD_RELOC_AVR32_6S +ENUMX + BFD_RELOC_AVR32_6UW +ENUMX + BFD_RELOC_AVR32_4UH +ENUMX + BFD_RELOC_AVR32_3U +ENUMDOC + Code relocations that will never make it to the output file. + +ENUM BFD_RELOC_390_12 ENUMDOC Direct 12 bit. Index: binutils-2.16.1-avr32/bfd/targets.c =================================================================== --- binutils-2.16.1-avr32.orig/bfd/targets.c 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/bfd/targets.c 2006-06-30 09:49:14.000000000 +0200 @@ -540,6 +540,7 @@ extern const bfd_target b_out_vec_little extern const bfd_target bfd_efi_app_ia32_vec; extern const bfd_target bfd_efi_app_ia64_vec; extern const bfd_target bfd_elf32_avr_vec; +extern const bfd_target bfd_elf32_avr32_vec; extern const bfd_target bfd_elf32_big_generic_vec; extern const bfd_target bfd_elf32_bigarc_vec; extern const bfd_target bfd_elf32_bigarm_vec; @@ -834,6 +835,7 @@ static const bfd_target * const _bfd_tar &bfd_efi_app_ia64_vec, #endif &bfd_elf32_avr_vec, + &bfd_elf32_avr32_vec, /* This, and other vectors, may not be used in any *.mt configuration. But that does not mean they are unnecessary. If configured with Index: binutils-2.16.1-avr32/include/elf/avr32.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/include/elf/avr32.h 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,95 @@ +/* AVR32 ELF support for BFD. + Copyright 2003-2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "elf/reloc-macros.h" + +/* CPU-specific flags for the ELF header e_flags field */ +#define EF_AVR32_LINKRELAX 0x01 +#define EF_AVR32_PIC 0x02 + +START_RELOC_NUMBERS (elf_avr32_reloc_type) + RELOC_NUMBER (R_AVR32_NONE, 0) + + /* Data Relocations */ + RELOC_NUMBER (R_AVR32_32, 1) + RELOC_NUMBER (R_AVR32_16, 2) + RELOC_NUMBER (R_AVR32_8, 3) + RELOC_NUMBER (R_AVR32_32_PCREL, 4) + RELOC_NUMBER (R_AVR32_16_PCREL, 5) + RELOC_NUMBER (R_AVR32_8_PCREL, 6) + RELOC_NUMBER (R_AVR32_DIFF32, 7) + RELOC_NUMBER (R_AVR32_DIFF16, 8) + RELOC_NUMBER (R_AVR32_DIFF8, 9) + RELOC_NUMBER (R_AVR32_GOT32, 10) + RELOC_NUMBER (R_AVR32_GOT16, 11) + RELOC_NUMBER (R_AVR32_GOT8, 12) + + /* Normal Code Relocations */ + RELOC_NUMBER (R_AVR32_21S, 13) + RELOC_NUMBER (R_AVR32_16U, 14) + RELOC_NUMBER (R_AVR32_16S, 15) + RELOC_NUMBER (R_AVR32_8S, 16) + RELOC_NUMBER (R_AVR32_8S_EXT, 17) + + /* PC-Relative Code Relocations */ + RELOC_NUMBER (R_AVR32_22H_PCREL, 18) + RELOC_NUMBER (R_AVR32_18W_PCREL, 19) + RELOC_NUMBER (R_AVR32_16B_PCREL, 20) + RELOC_NUMBER (R_AVR32_16N_PCREL, 21) + RELOC_NUMBER (R_AVR32_14UW_PCREL, 22) + RELOC_NUMBER (R_AVR32_11H_PCREL, 23) + RELOC_NUMBER (R_AVR32_10UW_PCREL, 24) + RELOC_NUMBER (R_AVR32_9H_PCREL, 25) + RELOC_NUMBER (R_AVR32_9UW_PCREL, 26) + + /* Special Code Relocations */ + RELOC_NUMBER (R_AVR32_HI16, 27) + RELOC_NUMBER (R_AVR32_LO16, 28) + + /* PIC Relocations */ + RELOC_NUMBER (R_AVR32_GOTPC, 29) + RELOC_NUMBER (R_AVR32_GOTCALL, 30) + RELOC_NUMBER (R_AVR32_LDA_GOT, 31) + RELOC_NUMBER (R_AVR32_GOT21S, 32) + RELOC_NUMBER (R_AVR32_GOT18SW, 33) + RELOC_NUMBER (R_AVR32_GOT16S, 34) + RELOC_NUMBER (R_AVR32_GOT7UW, 35) + + /* Constant Pool Relocations */ + RELOC_NUMBER (R_AVR32_32_CPENT, 36) + RELOC_NUMBER (R_AVR32_CPCALL, 37) + RELOC_NUMBER (R_AVR32_16_CP, 38) + RELOC_NUMBER (R_AVR32_9W_CP, 39) + + /* Dynamic Relocations */ + RELOC_NUMBER (R_AVR32_RELATIVE, 40) + RELOC_NUMBER (R_AVR32_GLOB_DAT, 41) + RELOC_NUMBER (R_AVR32_JMP_SLOT, 42) + + /* Linkrelax Information */ + RELOC_NUMBER (R_AVR32_ALIGN, 43) +END_RELOC_NUMBERS (R_AVR32_max) + +/* Processor specific dynamic array tags. */ + +/* The total size in bytes of the Global Offset Table */ +#define DT_AVR32_GOTSZ 0x70000001 Index: binutils-2.16.1-avr32/include/elf/common.h =================================================================== --- binutils-2.16.1-avr32.orig/include/elf/common.h 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/include/elf/common.h 2006-06-30 09:49:14.000000000 +0200 @@ -241,6 +241,9 @@ Written in the absense of an ABI. */ #define EM_AVR_OLD 0x1057 +/* AVR32 magic number, picked by IAR Systems. */ +#define EM_AVR32 0x18ad + /* OpenRISC magic number Written in the absense of an ABI. */ #define EM_OPENRISC_OLD 0x3426 Index: binutils-2.16.1-avr32/include/dis-asm.h =================================================================== --- binutils-2.16.1-avr32.orig/include/dis-asm.h 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/include/dis-asm.h 2006-06-30 09:49:14.000000000 +0200 @@ -221,6 +221,7 @@ extern int print_insn_sparc (bfd_vma, d extern int print_insn_big_a29k (bfd_vma, disassemble_info *); extern int print_insn_little_a29k (bfd_vma, disassemble_info *); extern int print_insn_avr (bfd_vma, disassemble_info *); +extern int print_insn_avr32 (bfd_vma, disassemble_info *); extern int print_insn_d10v (bfd_vma, disassemble_info *); extern int print_insn_d30v (bfd_vma, disassemble_info *); extern int print_insn_dlx (bfd_vma, disassemble_info *); @@ -270,7 +271,9 @@ extern disassembler_ftype cris_get_disas extern void print_mips_disassembler_options (FILE *); extern void print_ppc_disassembler_options (FILE *); extern void print_arm_disassembler_options (FILE *); +extern void print_avr32_disassembler_options (FILE *); extern void parse_arm_disassembler_option (char *); +extern void parse_avr32_disassembler_option (char *); extern int get_arm_regname_num_options (void); extern int set_arm_regname_option (int); extern int get_arm_regnames (int, const char **, const char **, const char ***); Index: binutils-2.16.1-avr32/opcodes/Makefile.am =================================================================== --- binutils-2.16.1-avr32.orig/opcodes/Makefile.am 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/opcodes/Makefile.am 2006-06-30 09:49:14.000000000 +0200 @@ -25,6 +25,7 @@ LIBIBERTY = ../libiberty/libiberty.a # Header files. HFILES = \ arm-opc.h \ + avr32-asm.h avr32-opc.h \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ h8500-opc.h \ @@ -52,6 +53,9 @@ CFILES = \ arc-ext.c \ arm-dis.c \ avr-dis.c \ + avr32-asm.c \ + avr32-dis.c \ + avr32-opc.c \ cgen-asm.c \ cgen-dis.c \ cgen-opc.c \ @@ -177,6 +181,9 @@ ALL_MACHINES = \ arc-ext.lo \ arm-dis.lo \ avr-dis.lo \ + avr32-asm.lo \ + avr32-dis.lo \ + avr32-opc.lo \ cgen-asm.lo \ cgen-dis.lo \ cgen-opc.lo \ @@ -539,6 +546,15 @@ arm-dis.lo: arm-dis.c sysdep.h config.h avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ $(INCDIR)/libiberty.h $(INCDIR)/opcode/avr.h +avr32-asm.lo: avr32-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h avr32-opc.h opintl.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +avr32-dis.lo: avr32-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + avr32-opc.h opintl.h +avr32-opc.lo: avr32-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h avr32-opc.h $(INCDIR)/libiberty.h cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h opintl.h Index: binutils-2.16.1-avr32/opcodes/avr32-asm.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/opcodes/avr32-asm.c 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,233 @@ +/* Assembler interface for AVR32. + Copyright 2005, 2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This file is part of libopcodes. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include + +#include "avr32-opc.h" +#include "avr32-asm.h" + +/* Structure for a register hash table entry. */ +struct reg_entry +{ + const char *name; + int number; +}; + +/* Integer Registers. */ +static const struct reg_entry reg_table[] = + { + /* Primary names (used by the disassembler) */ + { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 }, + { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 }, + { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 }, + { "r12", 12 }, { "sp", 13 }, { "lr", 14 }, { "pc", 15 }, + /* Alternatives to sp, lr and pc. */ + { "r13", 13 }, { "r14", 14 }, { "r15", 15 }, + }; +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0])) + +/* Coprocessor Registers. */ +static const struct reg_entry cr_table[] = + { + { "cr0", 0 }, { "cr1", 1 }, { "cr2", 2 }, { "cr3", 3 }, + { "cr4", 4 }, { "cr5", 5 }, { "cr6", 6 }, { "cr7", 7 }, + { "cr8", 8 }, { "cr9", 9 }, { "cr10", 10 }, { "cr11", 11 }, + { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 }, + }; +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0])) + +/* Floating-point Registers. */ +static const struct reg_entry fr_table[] = + { + { "fr0", 0 }, { "fr1", 1 }, { "fr2", 2 }, { "fr3", 3 }, + { "fr4", 4 }, { "fr5", 5 }, { "fr6", 6 }, { "fr7", 7 }, + { "fr8", 8 }, { "fr9", 9 }, { "fr10", 10 }, { "fr11", 11 }, + { "fr12", 12 }, { "fr13", 13 }, { "fr14", 14 }, { "fr15", 15 }, + }; +#define AVR32_NR_FPREGS (sizeof(fr_table)/sizeof(fr_table[0])) + +int +avr32_parse_intreg(const char *str) +{ + unsigned int i; + + for (i = 0; i < AVR32_NR_INTREGS; i++) + { + if (strcasecmp(reg_table[i].name, str) == 0) + return reg_table[i].number; + } + + return -1; +} + +int +avr32_parse_cpreg(const char *str) +{ + unsigned int i; + + for (i = 0; i < AVR32_NR_CPREGS; i++) + { + if (strcasecmp(cr_table[i].name, str) == 0) + return cr_table[i].number; + } + + return -1; +} + +int avr32_parse_fpreg(const char *str) +{ + unsigned int i; + + for (i = 0; i < AVR32_NR_FPREGS; i++) + { + if (strcasecmp(fr_table[i].name, str) == 0) + return fr_table[i].number; + } + + return -1; +} + +static unsigned long +parse_reglist(char *str, char **endptr, int (*parse_reg)(const char *)) +{ + int reg_from, reg_to; + unsigned long result = 0; + char *p1, *p2, c; + + while (*str) + { + for (p1 = str; *p1; p1++) + if (*p1 == ',' || *p1 == '-') + break; + + c = *p1, *p1 = 0; + reg_from = parse_reg(str); + *p1 = c; + + if (reg_from < 0) + break; + + if (*p1 == '-') + { + for (p2 = ++p1; *p2; p2++) + if (*p2 == ',') + break; + + c = *p2, *p2 = 0; + /* printf("going to parse reg_to from `%s'\n", p1); */ + reg_to = parse_reg(p1); + *p2 = c; + + if (reg_to < 0) + break; + + while (reg_from <= reg_to) + result |= (1 << reg_from++); + p1 = p2; + } + else + result |= (1 << reg_from); + + str = p1; + if (*str) ++str; + } + + if (endptr) + *endptr = str; + + return result; +} + +unsigned long +avr32_parse_reglist(char *str, char **endptr) +{ + return parse_reglist(str, endptr, avr32_parse_intreg); +} + +unsigned long +avr32_parse_cpreglist(char *str, char **endptr) +{ + return parse_reglist(str, endptr, avr32_parse_cpreg); +} + +int +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8) +{ + unsigned long result = 0; + + /* printf("convert regmask16 0x%04lx\n", regmask16); */ + + if (regmask16 & 0xf) + { + if ((regmask16 & 0xf) == 0xf) + result |= 1 << 0; + else + return -1; + } + if (regmask16 & 0xf0) + { + if ((regmask16 & 0xf0) == 0xf0) + result |= 1 << 1; + else + return -1; + } + if (regmask16 & 0x300) + { + if ((regmask16 & 0x300) == 0x300) + result |= 1 << 2; + else + return -1; + } + if (regmask16 & (1 << 13)) + return -1; + + if (regmask16 & (1 << 10)) + result |= 1 << 3; + if (regmask16 & (1 << 11)) + result |= 1 << 4; + if (regmask16 & (1 << 12)) + result |= 1 << 5; + if (regmask16 & (1 << 14)) + result |= 1 << 6; + if (regmask16 & (1 << 15)) + result |= 1 << 7; + + *regmask8 = result; + + return 0; +} + +#if 0 +struct reg_map +{ + const struct reg_entry *names; + int nr_regs; + struct hash_control *htab; + const char *errmsg; +}; + +struct reg_map all_reg_maps[] = + { + { reg_table, AVR32_NR_INTREGS, NULL, N_("integral register expected") }, + { cr_table, AVR32_NR_CPREGS, NULL, N_("coprocessor register expected") }, + }; +#endif Index: binutils-2.16.1-avr32/opcodes/avr32-asm.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/opcodes/avr32-asm.h 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,38 @@ +/* Assembler interface for AVR32. + Copyright 2005, 2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This file is part of libopcodes. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ +#ifndef __OPCODES_AVR32_ASM_H +#define __OPCODES_AVR32_ASM_H + +extern int +avr32_parse_intreg(const char *str); +extern int +avr32_parse_cpreg(const char *str); +extern int +avr32_parse_fpreg(const char *str); +extern unsigned long +avr32_parse_reglist(char *str, char **endptr); +extern unsigned long +avr32_parse_cpreglist(char *str, char **endptr); +extern int +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8); + +#endif /* __OPCODES_AVR32_ASM_H */ Index: binutils-2.16.1-avr32/opcodes/avr32-dis.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/opcodes/avr32-dis.c 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,891 @@ +/* Print AVR32 instructions for GDB and objdump. + Copyright 2005, 2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This file is part of libopcodes. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "avr32-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +/* TODO: Share this with -asm */ + +/* Structure for a register hash table entry. */ +struct reg_entry +{ + const char *name; + int number; +}; + +#ifndef strneq +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) +#endif + + +static const struct reg_entry reg_table[] = + { + /* Primary names (used by the disassembler) */ + { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 }, + { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 }, + { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 }, + { "r12", 12 }, { "sp", 13 }, { "lr", 14 }, { "pc", 15 }, + /* Alternatives to sp, lr and pc. */ + { "r13", 13 }, { "r14", 14 }, { "r15", 15 }, + }; +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0])) + +/* Coprocessor Registers. */ +static const struct reg_entry cr_table[] = + { + { "cr0", 0 }, { "cr1", 1 }, { "cr2", 2 }, { "cr3", 3 }, + { "cr4", 4 }, { "cr5", 5 }, { "cr6", 6 }, { "cr7", 7 }, + { "cr8", 8 }, { "cr9", 9 }, { "cr10", 10 }, { "cr11", 11 }, + { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 }, + }; +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0])) + +static const char bparts[4] = { 'b', 'l', 'u', 't' }; +static bfd_vma current_pc; + +struct avr32_field_value +{ + const struct avr32_ifield *ifield; + unsigned long value; +}; + +struct avr32_operand +{ + int id; + int is_pcrel; + int align_order; + int (*print)(struct avr32_operand *op, struct disassemble_info *info, + struct avr32_field_value *ifields); +}; + +static signed long +get_signed_value(const struct avr32_field_value *fv) +{ + signed long value = fv->value; + + if (fv->value & (1 << (fv->ifield->bitsize - 1))) + value |= (~0UL << fv->ifield->bitsize); + + return value; +} + +static void +print_reglist_range(unsigned int first, unsigned int last, + const struct reg_entry *reg_names, + int need_comma, + struct disassemble_info *info) +{ + if (need_comma) + info->fprintf_func(info->stream, ","); + + if (first == last) + info->fprintf_func(info->stream, "%s", + reg_names[first].name); + else + info->fprintf_func(info->stream, "%s-%s", + reg_names[first].name, reg_names[last].name); +} + +static int +print_intreg(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + unsigned long regid = ifields[0].value << op->align_order; + + info->fprintf_func(info->stream, "%s", + reg_table[regid].name); + return 1; +} + +static int +print_intreg_predec(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "--%s", + reg_table[ifields[0].value].name); + return 1; +} + +static int +print_intreg_postinc(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "%s++", + reg_table[ifields[0].value].name); + return 1; +} + +static int +print_intreg_lsl(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + const char *rp = reg_table[ifields[0].value].name; + unsigned long sa = ifields[1].value; + + if (sa) + info->fprintf_func(info->stream, "%s<<0x%lx", rp, sa); + else + info->fprintf_func(info->stream, "%s", rp); + + return 2; +} + +static int +print_intreg_lsr(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + const char *rp = reg_table[ifields[0].value].name; + unsigned long sa = ifields[1].value; + + if (sa) + info->fprintf_func(info->stream, "%s>>0x%lx", rp, sa); + else + info->fprintf_func(info->stream, "%s", rp); + + return 2; +} + +static int +print_intreg_bpart(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "%s:%c", + reg_table[ifields[0].value].name, + bparts[ifields[1].value]); + return 2; +} + +static int +print_intreg_hpart(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "%s:%c", + reg_table[ifields[0].value].name, + ifields[1].value ? 't' : 'b'); + return 2; +} + +static int +print_intreg_sdisp(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + signed long disp; + + disp = get_signed_value(&ifields[1]) << op->align_order; + + info->fprintf_func(info->stream, "%s[%ld]", + reg_table[ifields[0].value].name, disp); + return 2; +} + +static int +print_intreg_udisp(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "%s[0x%lx]", + reg_table[ifields[0].value].name, + ifields[1].value << op->align_order); + return 2; +} + +static int +print_intreg_index(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + const char *rb, *ri; + unsigned long sa = ifields[2].value; + + rb = reg_table[ifields[0].value].name; + ri = reg_table[ifields[1].value].name; + + if (sa) + info->fprintf_func(info->stream, "%s[%s<<0x%lx]", rb, ri, sa); + else + info->fprintf_func(info->stream, "%s[%s]", rb, ri); + + return 3; +} + +static int +print_intreg_xindex(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "%s[%s:%c<<2]", + reg_table[ifields[0].value].name, + reg_table[ifields[1].value].name, + bparts[ifields[2].value]); + return 3; +} + +static int +print_jmplabel(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + bfd_vma address, offset; + + offset = get_signed_value(ifields) << op->align_order; + address = (current_pc & (~0UL << op->align_order)) + offset; + + info->print_address_func(address, info); + + return 1; +} + +static int +print_pc_disp(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + bfd_vma address, offset; + + offset = ifields[0].value << op->align_order; + address = (current_pc & (~0UL << op->align_order)) + offset; + + info->print_address_func(address, info); + + return 1; +} + +static int +print_sp(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields ATTRIBUTE_UNUSED) +{ + info->fprintf_func(info->stream, "sp"); + return 1; +} + +static int +print_sp_disp(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "sp[0x%lx]", + ifields[0].value << op->align_order); + return 1; +} + +static int +print_cpno(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "cp%lu", ifields[0].value); + return 1; +} + +static int +print_cpreg(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "cr%lu", + ifields[0].value << op->align_order); + return 1; +} + +static int +print_uconst(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "0x%lx", + ifields[0].value << op->align_order); + return 1; +} + +static int +print_sconst(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + info->fprintf_func(info->stream, "%ld", + get_signed_value(ifields) << op->align_order); + return 1; +} + +static int +print_reglist8_head(unsigned long regmask, int *commap, + struct disassemble_info *info) +{ + int first = -1, last, i = 0; + int need_comma = 0; + + while (i < 12) + { + if (first == -1 && (regmask & 1)) + { + first = i; + } + else if (first != -1 && !(regmask & 1)) + { + last = i - 1; + + print_reglist_range(first, last, reg_table, need_comma, info); + need_comma = 1; + first = -1; + } + + if (i < 8) + i += 4; + else if (i < 10) + i += 2; + else + i++; + regmask >>= 1; + } + + *commap = need_comma; + return first; +} + +static void +print_reglist8_tail(unsigned long regmask, int first, int need_comma, + struct disassemble_info *info) +{ + int last = 11; + + if (regmask & 0x20) + { + if (first == -1) + first = 12; + last = 12; + } + + if (first != -1) + { + print_reglist_range(first, last, reg_table, need_comma, info); + need_comma = 1; + first = -1; + } + + if (regmask & 0x40) + { + if (first == -1) + first = 14; + last = 14; + } + + if (regmask & 0x80) + { + if (first == -1) + first = 15; + last = 15; + } + + if (first != -1) + print_reglist_range(first, last, reg_table, need_comma, info); +} + +static int +print_reglist8(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + unsigned long regmask = ifields[0].value; + int first, need_comma; + + first = print_reglist8_head(regmask, &need_comma, info); + print_reglist8_tail(regmask, first, need_comma, info); + + return 1; +} + +static int +print_reglist9(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + unsigned long regmask = ifields[0].value >> 1; + int first, last, need_comma; + + first = print_reglist8_head(regmask, &need_comma, info); + + if ((ifields[0].value & 0x101) == 0x101) + { + if (first != -1) + { + last = 11; + + print_reglist_range(first, last, reg_table, need_comma, info); + need_comma = 1; + first = -1; + } + + print_reglist_range(15, 15, reg_table, need_comma, info); + + regmask >>= 5; + + if ((regmask & 3) == 0) + info->fprintf_func(info->stream, ",r12=0"); + else if ((regmask & 3) == 1) + info->fprintf_func(info->stream, ",r12=1"); + else + info->fprintf_func(info->stream, ",r12=-1"); + } + else + print_reglist8_tail(regmask, first, need_comma, info); + + return 1; +} + +static int +print_reglist16(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + unsigned long regmask = ifields[0].value; + unsigned int i = 0, first, last; + int need_comma = 0; + + while (i < 16) + { + if (regmask & 1) + { + first = i; + while (i < 16) + { + i++; + regmask >>= 1; + if (!(regmask & 1)) + break; + } + last = i - 1; + print_reglist_range(first, last, reg_table, need_comma, info); + need_comma = 1; + } + else + { + i++; + regmask >>= 1; + } + } + + return 1; +} + +static int +print_reglist_ldm(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + int rp, w_bit; + int i, first, last; + unsigned long regmask; + + rp = ifields[0].value; + w_bit = ifields[1].value; + regmask = ifields[2].value; + + if (regmask & (1 << AVR32_REG_PC) && rp == AVR32_REG_PC) + { + if (w_bit) + info->fprintf_func(info->stream, "sp++"); + else + info->fprintf_func(info->stream, "sp"); + + for (i = 0; i < 12; ) + { + if (regmask & (1 << i)) + { + first = i; + while (i < 12) + { + i++; + if (!(regmask & (1 << i))) + break; + } + last = i - 1; + print_reglist_range(first, last, reg_table, 1, info); + } + else + i++; + } + + info->fprintf_func(info->stream, ",pc"); + if (regmask & (1 << AVR32_REG_LR)) + info->fprintf_func(info->stream, ",r12=-1"); + else if (regmask & (1 << AVR32_REG_R12)) + info->fprintf_func(info->stream, ",r12=1"); + else + info->fprintf_func(info->stream, ",r12=0"); + } + else + { + if (w_bit) + info->fprintf_func(info->stream, "%s++,", reg_table[rp].name); + else + info->fprintf_func(info->stream, "%s,", reg_table[rp].name); + + print_reglist16(op, info, ifields + 2); + } + + return 3; +} + +static int +print_reglist_cp8(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + unsigned long regmask = ifields[0].value; + unsigned int i = 0, first, last, offset = 0; + int need_comma = 0; + + if (ifields[1].value) + offset = 8; + + while (i < 8) + { + if (regmask & 1) + { + first = i; + while (i < 8) + { + i++; + regmask >>= 1; + if (!(regmask & 1)) + break; + } + last = i - 1; + print_reglist_range(offset + first, offset + last, + cr_table, need_comma, info); + need_comma = 1; + } + else + { + i++; + regmask >>= 1; + } + } + + return 2; +} + +static int +print_reglist_cpd8(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + unsigned long regmask = ifields[0].value; + unsigned int i = 0, first, last; + int need_comma = 0; + + while (i < 8) + { + if (regmask & 1) + { + first = 2 * i; + while (i < 8) + { + i++; + regmask >>= 1; + if (!(regmask & 1)) + break; + } + last = 2 * (i - 1) + 1; + print_reglist_range(first, last, cr_table, need_comma, info); + need_comma = 1; + } + else + { + i++; + regmask >>= 1; + } + } + + return 1; +} + +static int +print_retval(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + unsigned long regid = ifields[0].value; + const char *retval; + + if (regid < AVR32_REG_SP) + retval = reg_table[regid].name; + else if (regid == AVR32_REG_SP) + retval = "0"; + else if (regid == AVR32_REG_LR) + retval = "-1"; + else + retval = "1"; + + info->fprintf_func(info->stream, "%s", retval); + + return 1; +} + +static int +print_mcall(struct avr32_operand *op, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + unsigned long regid = ifields[0].value; + + if (regid == AVR32_REG_PC) + print_jmplabel(op, info, ifields + 1); + else + print_intreg_sdisp(op, info, ifields); + + return 2; +} + +static int +print_jospinc(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields) +{ + signed long value = ifields[0].value; + + if (value >= 4) + value -= 8; + else + value += 1; + + info->fprintf_func(info->stream, "%ld", value); + + return 1; +} + +static int +print_coh(struct avr32_operand *op ATTRIBUTE_UNUSED, + struct disassemble_info *info, + struct avr32_field_value *ifields ATTRIBUTE_UNUSED) +{ + info->fprintf_func(info->stream, "COH"); + return 0; +} + +#define OP(name, sgn, pcrel, align, func) \ + { AVR32_OPERAND_##name, pcrel, align, print_##func } + +struct avr32_operand operand[AVR32_NR_OPERANDS] = + { + OP(INTREG, 0, 0, 0, intreg), + OP(INTREG_PREDEC, 0, 0, 0, intreg_predec), + OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc), + OP(INTREG_LSL, 0, 0, 0, intreg_lsl), + OP(INTREG_LSR, 0, 0, 0, intreg_lsr), + OP(INTREG_BSEL, 0, 0, 0, intreg_bpart), + OP(INTREG_HSEL, 0, 0, 1, intreg_hpart), + OP(INTREG_SDISP, 1, 0, 0, intreg_sdisp), + OP(INTREG_SDISP_H, 1, 0, 1, intreg_sdisp), + OP(INTREG_SDISP_W, 1, 0, 2, intreg_sdisp), + OP(INTREG_UDISP, 0, 0, 0, intreg_udisp), + OP(INTREG_UDISP_H, 0, 0, 1, intreg_udisp), + OP(INTREG_UDISP_W, 0, 0, 2, intreg_udisp), + OP(INTREG_INDEX, 0, 0, 0, intreg_index), + OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex), + OP(DWREG, 0, 0, 1, intreg), + OP(PC_UDISP_W, 0, 1, 2, pc_disp), + OP(SP, 0, 0, 0, sp), + OP(SP_UDISP_W, 0, 0, 2, sp_disp), + OP(CPNO, 0, 0, 0, cpno), + OP(CPREG, 0, 0, 0, cpreg), + OP(CPREG_D, 0, 0, 1, cpreg), + OP(UNSIGNED_CONST, 0, 0, 0, uconst), + OP(UNSIGNED_CONST_W, 0, 0, 2, uconst), + OP(SIGNED_CONST, 1, 0, 0, sconst), + OP(SIGNED_CONST_W, 1, 0, 2, sconst), + OP(JMPLABEL, 1, 1, 1, jmplabel), + OP(UNSIGNED_NUMBER, 0, 0, 0, uconst), + OP(UNSIGNED_NUMBER_W, 0, 0, 2, uconst), + OP(REGLIST8, 0, 0, 0, reglist8), + OP(REGLIST9, 0, 0, 0, reglist9), + OP(REGLIST16, 0, 0, 0, reglist16), + OP(REGLIST_LDM, 0, 0, 0, reglist_ldm), + OP(REGLIST_CP8, 0, 0, 0, reglist_cp8), + OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8), + OP(RETVAL, 0, 0, 0, retval), + OP(MCALL, 1, 0, 2, mcall), + OP(JOSPINC, 0, 0, 0, jospinc), + OP(COH, 0, 0, 0, coh), + }; + +static void +print_opcode(bfd_vma insn_word, const struct avr32_opcode *opc, + bfd_vma pc, struct disassemble_info *info) +{ + const struct avr32_syntax *syntax = opc->syntax; + struct avr32_field_value fields[AVR32_MAX_FIELDS]; + unsigned int i, next_field = 0, nr_operands; + + for (i = 0; i < opc->nr_fields; i++) + { + opc->fields[i]->extract(opc->fields[i], &insn_word, &fields[i].value); + fields[i].ifield = opc->fields[i]; + } + + current_pc = pc; + info->fprintf_func(info->stream, "%s", syntax->mnemonic->name); + + if (syntax->nr_operands < 0) + nr_operands = (unsigned int) -syntax->nr_operands; + else + nr_operands = (unsigned int) syntax->nr_operands; + + for (i = 0; i < nr_operands; i++) + { + struct avr32_operand *op = &operand[syntax->operand[i]]; + + if (i) + info->fprintf_func(info->stream, ","); + else + info->fprintf_func(info->stream, " "); + next_field += op->print(op, info, &fields[next_field]); + } +} + +static const struct avr32_opcode * +find_opcode(bfd_vma insn_word) +{ + int i; + + for (i = 0; i < AVR32_NR_OPCODES; i++) + { + const struct avr32_opcode *opc = &avr32_opc_table[i]; + + if ((insn_word & opc->mask) == opc->value) + return opc; + } + + return NULL; +} + +static int +read_insn_word(bfd_vma pc, bfd_vma *valuep, + struct disassemble_info *info) +{ + bfd_byte b[4]; + int status; + + status = info->read_memory_func(pc, b, 4, info); + if (status) + { + status = info->read_memory_func(pc, b, 2, info); + if (status) + { + info->memory_error_func(status, pc, info); + return -1; + } + b[3] = b[2] = 0; + } + + *valuep = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; + return 0; +} + +/* Parse an individual disassembler option. */ + +void +parse_avr32_disassembler_option (option) + char * option; +{ + if (option == NULL) + return; + + /* XXX - should break 'option' at following delimiter. */ + fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); + + return; +} + +/* Parse the string of disassembler options, spliting it at whitespaces + or commas. (Whitespace separators supported for backwards compatibility). */ + +static void +parse_disassembler_options (char *options) +{ + if (options == NULL) + return; + + while (*options) + { + parse_avr32_disassembler_option (options); + + /* Skip forward to next seperator. */ + while ((*options) && (! ISSPACE (*options)) && (*options != ',')) + ++ options; + /* Skip forward past seperators. */ + while (ISSPACE (*options) || (*options == ',')) + ++ options; + } +} + +int +print_insn_avr32(bfd_vma pc, struct disassemble_info *info) +{ + bfd_vma insn_word; + const struct avr32_opcode *opc; + + if (info->disassembler_options) + { + parse_disassembler_options (info->disassembler_options); + + /* To avoid repeated parsing of these options, we remove them here. */ + info->disassembler_options = NULL; + } + + info->bytes_per_chunk = 1; + info->display_endian = BFD_ENDIAN_BIG; + + if (read_insn_word(pc, &insn_word, info)) + return -1; + + opc = find_opcode(insn_word); + if (opc) + { + print_opcode(insn_word, opc, pc, info); + return opc->size; + } + else + { + info->fprintf_func(info->stream, _("*unknown*")); + return 2; + } + +} + +void +print_avr32_disassembler_options (FILE *stream ATTRIBUTE_UNUSED) +{ + +} Index: binutils-2.16.1-avr32/opcodes/avr32-opc.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/opcodes/avr32-opc.c 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,5356 @@ +/* Opcode tables for AVR32. + Copyright 2005, 2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This file is part of libopcodes. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include + +#include "avr32-opc.h" + +void +avr32_insert_simple(const struct avr32_ifield *field, + void *buf, unsigned long value) +{ + bfd_vma word; + + word = bfd_getb32(buf); + word &= ~field->mask; + word |= (value << field->shift) & field->mask; + bfd_putb32(word, buf); +} + +void +avr32_insert_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED, + void *buf, unsigned long value) +{ + char *opcode = buf; + + opcode[0] = (opcode[0] & 0xe1) | (value & 0x1e); + opcode[1] = (opcode[1] & 0xef) | ((value & 1) << 4); +} + +void +avr32_insert_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED, + void *buf, unsigned long value) +{ + char *opcode = buf; + + opcode[0] = (opcode[0] & 0xf0) | ((value & 0xf0) >> 4); + opcode[1] = ((opcode[1] & 0x0c) | ((value & 0x0f) << 4) + | ((value & 0x300) >> 8)); +} + +void +avr32_insert_k21(const struct avr32_ifield *field, + void *buf, unsigned long value) +{ + bfd_vma word; + bfd_vma k21; + + word = bfd_getb32(buf); + word &= ~field->mask; + k21 = ((value & 0xffff) | ((value & 0x10000) << 4) + | ((value & 0x1e0000) << 8)); + assert(!(k21 & ~field->mask)); + word |= k21; + bfd_putb32(word, buf); +} + +void +avr32_insert_cpop(const struct avr32_ifield *field, + void *buf, unsigned long value) +{ + bfd_vma word; + + word = bfd_getb32(buf); + word &= ~field->mask; + word |= (((value & 0x1e) << 15) | ((value & 0x60) << 20) + | ((value & 0x01) << 12)); + bfd_putb32(word, buf); +} + +void +avr32_insert_k12cp(const struct avr32_ifield *field, + void *buf, unsigned long value) +{ + bfd_vma word; + + word = bfd_getb32(buf); + word &= ~field->mask; + word |= ((value & 0xf00) << 4) | (value & 0xff); + bfd_putb32(word, buf); +} + +void avr32_extract_simple(const struct avr32_ifield *field, + void *buf, unsigned long *value) +{ + /* XXX: The disassembler has done any necessary byteswapping already */ + bfd_vma word = *(bfd_vma *)buf; + + *value = (word & field->mask) >> field->shift; +} + +void avr32_extract_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED, + void *buf, unsigned long *value) +{ + bfd_vma word = *(bfd_vma *)buf; + + *value = ((word >> 20) & 1) | ((word >> 24) & 0x1e); +} + +void avr32_extract_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED, + void *buf, unsigned long *value) +{ + bfd_vma word = *(bfd_vma *)buf; + + *value = ((word >> 8) & 0x300) | ((word >> 20) & 0xff); +} + +void avr32_extract_k21(const struct avr32_ifield *field ATTRIBUTE_UNUSED, + void *buf, unsigned long *value) +{ + bfd_vma word = *(bfd_vma *)buf; + + *value = ((word & 0xffff) | ((word >> 4) & 0x10000) + | ((word >> 8) & 0x1e0000)); +} + +void avr32_extract_cpop(const struct avr32_ifield *field ATTRIBUTE_UNUSED, + void *buf, unsigned long *value) +{ + bfd_vma word = *(bfd_vma *)buf; + + *value = (((word >> 12) & 1) | ((word >> 15) & 0x1e) + | ((word >> 20) & 0x60)); +} + +void avr32_extract_k12cp(const struct avr32_ifield *field ATTRIBUTE_UNUSED, + void *buf, unsigned long *value) +{ + bfd_vma word = *(bfd_vma *)buf; + + *value = ((word >> 4) & 0xf00) | (word & 0xff); +} + +#define IFLD(id, bitsz, shift, mask, func) \ + { AVR32_IFIELD_##id, bitsz, shift, mask, \ + avr32_insert_##func, avr32_extract_##func } + +const struct avr32_ifield avr32_ifield_table[] = + { + IFLD(RX, 4, 25, 0x1e000000, simple), + IFLD(RY, 4, 16, 0x000f0000, simple), + IFLD(COND4C, 4, 20, 0x00f00000, simple), + IFLD(K8C, 8, 20, 0x0ff00000, simple), + IFLD(K7C, 7, 20, 0x07f00000, simple), + IFLD(K5C, 5, 20, 0x01f00000, simple), + IFLD(K3, 3, 20, 0x00700000, simple), + IFLD(RY_DW, 3, 17, 0x000e0000, simple), + IFLD(COND4E, 4, 8, 0x00000f00, simple), + IFLD(K8E, 8, 0, 0x000000ff, simple), + IFLD(BIT5C, 5, 20, 0x1e100000, bit5c), + IFLD(COND3, 3, 16, 0x00070000, simple), + IFLD(K10, 10, 16, 0x0ff30000, k10), + IFLD(POPM, 9, 19, 0x0ff80000, simple), + IFLD(K2, 2, 4, 0x00000030, simple), + IFLD(RD_E, 4, 0, 0x0000000f, simple), + IFLD(RD_DW, 3, 1, 0x0000000e, simple), + IFLD(X, 1, 5, 0x00000020, simple), + IFLD(Y, 1, 4, 0x00000010, simple), + IFLD(X2, 1, 13, 0x00002000, simple), + IFLD(Y2, 1, 12, 0x00001000, simple), + IFLD(K5E, 5, 0, 0x0000001f, simple), + IFLD(PART2, 2, 0, 0x00000003, simple), + IFLD(PART1, 1, 0, 0x00000001, simple), + IFLD(K16, 16, 0, 0x0000ffff, simple), + IFLD(CACHEOP, 5, 11, 0x0000f800, simple), + IFLD(K11, 11, 0, 0x000007ff, simple), + IFLD(K21, 21, 0, 0x1e10ffff, k21), + IFLD(CPOP, 7, 12, 0x060f1000, cpop), + IFLD(CPNO, 3, 13, 0x0000e000, simple), + IFLD(CRD_RI, 4, 8, 0x00000f00, simple), + IFLD(CRX, 4, 4, 0x000000f0, simple), + IFLD(CRY, 4, 0, 0x0000000f, simple), + IFLD(K7E, 7, 0, 0x0000007f, simple), + IFLD(CRD_DW, 3, 9, 0x00000e00, simple), + IFLD(PART1_K12, 1, 12, 0x00001000, simple), + IFLD(PART2_K12, 2, 12, 0x00003000, simple), + IFLD(K12, 12, 0, 0x00000fff, simple), + IFLD(S5, 5, 5, 0x000003e0, simple), + IFLD(K5E2, 5, 4, 0x000001f0, simple), + IFLD(K4, 4, 20, 0x00f00000, simple), + IFLD(COND4E2, 4, 4, 0x000000f0, simple), + IFLD(K8E2, 8, 4, 0x00000ff0, simple), + IFLD(K6, 6, 20, 0x03f00000, simple), + IFLD(MEM15, 15, 0, 0x00007fff, simple), + IFLD(MEMB5, 5, 15, 0x000f8000, simple), + IFLD(W, 1, 25, 0x02000000, simple), + /* Coprocessor Multiple High/Low */ + IFLD(CM_HL, 1, 8, 0x00000100, simple), + IFLD(K12CP, 12 ,0, 0x0000f0ff, k12cp), + }; +#undef IFLD + + +struct avr32_opcode avr32_opc_table[] = + { + { + AVR32_OPC_ABS, 2, 0x5c400000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ABS], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_ACALL, 2, 0xd0000000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_ACALL], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_ACR, 2, 0x5c000000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ACR], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ADC, 4, 0xe0000040, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_ADC], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ADD1, 2, 0x00000000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ADD1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_ADD2, 4, 0xe0000000, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_ADD2], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_ADDABS, 4, 0xe0000e40, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_ADDABS], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ADDHH_W, 4, 0xe0000e00, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_ADDHH_W], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_AND1, 2, 0x00600000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_AND1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_AND2, 4, 0xe1e00000, 0xe1f0fe00, + &avr32_syntax_table[AVR32_SYNTAX_AND2], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E2], + }, + }, + { + AVR32_OPC_AND3, 4, 0xe1e00200, 0xe1f0fe00, + &avr32_syntax_table[AVR32_SYNTAX_AND3], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E2], + }, + }, + { + AVR32_OPC_ANDH, 4, 0xe4100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ANDH], + BFD_RELOC_AVR32_16U, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_ANDH_COH, 4, 0xe6100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ANDH_COH], + BFD_RELOC_AVR32_16U, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_ANDL, 4, 0xe0100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ANDL], + BFD_RELOC_AVR32_16U, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_ANDL_COH, 4, 0xe2100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ANDL_COH], + BFD_RELOC_AVR32_16U, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_ANDN, 2, 0x00800000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ANDN], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_ASR1, 4, 0xe0000840, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_ASR1], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ASR3, 4, 0xe0001400, 0xe1f0ffe0, + &avr32_syntax_table[AVR32_SYNTAX_ASR3], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K5E], + }, + }, + { + AVR32_OPC_ASR2, 2, 0xa1400000, 0xe1e00000, + &avr32_syntax_table[AVR32_SYNTAX_ASR2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_BIT5C], + }, + }, + { + AVR32_OPC_BLD, 4, 0xedb00000, 0xfff0ffe0, + &avr32_syntax_table[AVR32_SYNTAX_BLD], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E], + }, + }, + { + AVR32_OPC_BREQ1, 2, 0xc0000000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_BREQ1], + BFD_RELOC_AVR32_9H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_BRNE1, 2, 0xc0010000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_BRNE1], + BFD_RELOC_AVR32_9H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_BRCC1, 2, 0xc0020000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_BRCC1], + BFD_RELOC_AVR32_9H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_BRCS1, 2, 0xc0030000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_BRCS1], + BFD_RELOC_AVR32_9H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_BRGE1, 2, 0xc0040000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_BRGE1], + BFD_RELOC_AVR32_9H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_BRLT1, 2, 0xc0050000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_BRLT1], + BFD_RELOC_AVR32_9H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_BRMI1, 2, 0xc0060000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_BRMI1], + BFD_RELOC_AVR32_9H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_BRPL1, 2, 0xc0070000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_BRPL1], + BFD_RELOC_AVR32_9H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_BREQ2, 4, 0xe0800000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BREQ2], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRNE2, 4, 0xe0810000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRNE2], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRCC2, 4, 0xe0820000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRHS2], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRCS2, 4, 0xe0830000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRLO2], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRGE2, 4, 0xe0840000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRGE2], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRLT2, 4, 0xe0850000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRLT2], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRMI2, 4, 0xe0860000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRMI2], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRPL2, 4, 0xe0870000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRPL2], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRLS, 4, 0xe0880000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRLS], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRGT, 4, 0xe0890000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRGT], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRLE, 4, 0xe08a0000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRLE], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRHI, 4, 0xe08b0000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRHI], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRVS, 4, 0xe08c0000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRVS], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRVC, 4, 0xe08d0000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRVC], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRQS, 4, 0xe08e0000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRQS], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BRAL, 4, 0xe08f0000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_BRAL], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_BREAKPOINT, 2, 0xd6730000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_BREAKPOINT], + BFD_RELOC_UNUSED, 0, -1, { NULL }, + }, + { + AVR32_OPC_BREV, 2, 0x5c900000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_BREV], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_BST, 4, 0xefb00000, 0xfff0ffe0, + &avr32_syntax_table[AVR32_SYNTAX_BST], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E], + }, + }, + { + AVR32_OPC_CACHE, 4, 0xf4100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_CACHE], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K11], + &avr32_ifield_table[AVR32_IFIELD_CACHEOP], + }, + }, + { + AVR32_OPC_CASTS_B, 2, 0x5c600000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_CASTS_B], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_CASTS_H, 2, 0x5c800000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_CASTS_H], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_CASTU_B, 2, 0x5c500000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_CASTU_B], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_CASTU_H, 2, 0x5c700000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_CASTU_H], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_CBR, 2, 0xa1c00000, 0xe1e00000, + &avr32_syntax_table[AVR32_SYNTAX_CBR], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_BIT5C], + }, + }, + { + AVR32_OPC_CLZ, 4, 0xe0001200, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_CLZ], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_COM, 2, 0x5cd00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_COM], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_COP, 4, 0xe1a00000, 0xf9f00000, + &avr32_syntax_table[AVR32_SYNTAX_COP], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + &avr32_ifield_table[AVR32_IFIELD_CRX], + &avr32_ifield_table[AVR32_IFIELD_CRY], + &avr32_ifield_table[AVR32_IFIELD_CPOP], + }, + }, + { + AVR32_OPC_CP_B, 4, 0xe0001800, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_CP_B], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_CP_H, 4, 0xe0001900, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_CP_H], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_CP_W1, 2, 0x00300000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_CP_W1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_CP_W2, 2, 0x58000000, 0xfc000000, + &avr32_syntax_table[AVR32_SYNTAX_CP_W2], + BFD_RELOC_AVR32_6S, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K6], + }, + }, + { + AVR32_OPC_CP_W3, 4, 0xe0400000, 0xe1e00000, + &avr32_syntax_table[AVR32_SYNTAX_CP_W3], + BFD_RELOC_AVR32_21S, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_CPC1, 4, 0xe0001300, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_CPC1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_CPC2, 2, 0x5c200000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_CPC2], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_CSRF, 2, 0xd4030000, 0xfe0f0000, + &avr32_syntax_table[AVR32_SYNTAX_CSRF], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_K5C], + }, + }, + { + AVR32_OPC_CSRFCZ, 2, 0xd0030000, 0xfe0f0000, + &avr32_syntax_table[AVR32_SYNTAX_CSRFCZ], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_K5C], + }, + }, + { + AVR32_OPC_DIVS, 4, 0xe0000c00, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_DIVS], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_DIVU, 4, 0xe0000d00, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_DIVU], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_EOR1, 2, 0x00500000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_EOR1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_EOR2, 4, 0xe1e02000, 0xe1f0fe00, + &avr32_syntax_table[AVR32_SYNTAX_EOR2], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E2], + } + }, + { + AVR32_OPC_EOR3, 4, 0xe1e02200, 0xe1f0fe00, + &avr32_syntax_table[AVR32_SYNTAX_EOR3], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E2], + } + }, + { + AVR32_OPC_EORL, 4, 0xec100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_EORL], + BFD_RELOC_AVR32_16U, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_EORH, 4, 0xee100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_EORH], + BFD_RELOC_AVR32_16U, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_FRS, 2, 0xd7430000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_FRS], + BFD_RELOC_UNUSED, 0, -1, { NULL }, + }, + { + AVR32_OPC_ICALL, 2, 0x5d100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ICALL], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_INCJOSP, 2, 0xd6830000, 0xff8f0000, + &avr32_syntax_table[AVR32_SYNTAX_INCJOSP], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_K3], + }, + }, + { + AVR32_OPC_LD_D1, 2, 0xa1010000, 0xe1f10000, + &avr32_syntax_table[AVR32_SYNTAX_LD_D1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_D2, 2, 0xa1100000, 0xe1f10000, + &avr32_syntax_table[AVR32_SYNTAX_LD_D2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_D3, 2, 0xa1000000, 0xe1f10000, + &avr32_syntax_table[AVR32_SYNTAX_LD_D3], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_D5, 4, 0xe0000200, 0xe1f0ffc1, + &avr32_syntax_table[AVR32_SYNTAX_LD_D5], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_DW], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_LD_D4, 4, 0xe0e00000, 0xe1f10000, + &avr32_syntax_table[AVR32_SYNTAX_LD_D4], + BFD_RELOC_AVR32_16S, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LD_SB2, 4, 0xe0000600, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_LD_SB2], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_LD_SB1, 4, 0xe1200000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_SB1], + BFD_RELOC_AVR32_16S, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LD_UB1, 2, 0x01300000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_UB1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_UB2, 2, 0x01700000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_UB2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_UB5, 4, 0xe0000700, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_LD_UB5], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_LD_UB3, 2, 0x01800000, 0xe1800000, + &avr32_syntax_table[AVR32_SYNTAX_LD_UB3], + BFD_RELOC_AVR32_3U, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K3], + }, + }, + { + AVR32_OPC_LD_UB4, 4, 0xe1300000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_UB4], + BFD_RELOC_AVR32_16S, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LD_SH1, 2, 0x01100000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_SH1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_SH2, 2, 0x01500000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_SH2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_SH5, 4, 0xe0000400, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_LD_SH5], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_LD_SH3, 2, 0x80000000, 0xe1800000, + &avr32_syntax_table[AVR32_SYNTAX_LD_SH3], + BFD_RELOC_AVR32_4UH, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K3], + }, + }, + { + AVR32_OPC_LD_SH4, 4, 0xe1000000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_SH4], + BFD_RELOC_AVR32_16S, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LD_UH1, 2, 0x01200000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_UH1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_UH2, 2, 0x01600000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_UH2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_UH5, 4, 0xe0000500, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_LD_UH5], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_LD_UH3, 2, 0x80800000, 0xe1800000, + &avr32_syntax_table[AVR32_SYNTAX_LD_UH3], + BFD_RELOC_AVR32_4UH, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K3], + }, + }, + { + AVR32_OPC_LD_UH4, 4, 0xe1100000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_UH4], + BFD_RELOC_AVR32_16S, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LD_W1, 2, 0x01000000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_W1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_W2, 2, 0x01400000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_W2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_LD_W5, 4, 0xe0000300, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_LD_W5], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_LD_W6, 4, 0xe0000f80, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_LD_W6], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_LD_W3, 2, 0x60000000, 0xe0000000, + &avr32_syntax_table[AVR32_SYNTAX_LD_W3], + BFD_RELOC_AVR32_7UW, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K5C], + }, + }, + { + AVR32_OPC_LD_W4, 4, 0xe0f00000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_LD_W4], + BFD_RELOC_AVR32_16S, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LDC_D1, 4, 0xe9a01000, 0xfff01100, + &avr32_syntax_table[AVR32_SYNTAX_LDC_D1], + BFD_RELOC_AVR32_10UW, 4, 3, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_LDC_D2, 4, 0xefa00050, 0xfff011ff, + &avr32_syntax_table[AVR32_SYNTAX_LDC_D2], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_LDC_D3, 4, 0xefa01040, 0xfff011c0, + &avr32_syntax_table[AVR32_SYNTAX_LDC_D3], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_LDC_W1, 4, 0xe9a00000, 0xfff01000, + &avr32_syntax_table[AVR32_SYNTAX_LDC_W1], + BFD_RELOC_AVR32_10UW, 4, 3, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_LDC_W2, 4, 0xefa00040, 0xfff010ff, + &avr32_syntax_table[AVR32_SYNTAX_LDC_W2], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_LDC_W3, 4, 0xefa01000, 0xfff010c0, + &avr32_syntax_table[AVR32_SYNTAX_LDC_W3], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_LDC0_D, 4, 0xf3a00000, 0xfff00100, + &avr32_syntax_table[AVR32_SYNTAX_LDC0_D], + BFD_RELOC_AVR32_14UW, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K12CP], + }, + }, + { + AVR32_OPC_LDC0_W, 4, 0xf1a00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_LDC0_W], + BFD_RELOC_AVR32_14UW, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K12CP], + }, + }, + { + AVR32_OPC_LDCM_D, 4, 0xeda00400, 0xfff01f00, + &avr32_syntax_table[AVR32_SYNTAX_LDCM_D], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_LDCM_D_PU, 4, 0xeda01400, 0xfff01f00, + &avr32_syntax_table[AVR32_SYNTAX_LDCM_D_PU], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_LDCM_W, 4, 0xeda00000, 0xfff01e00, + &avr32_syntax_table[AVR32_SYNTAX_LDCM_W], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + &avr32_ifield_table[AVR32_IFIELD_CM_HL], + }, + }, + { + AVR32_OPC_LDCM_W_PU, 4, 0xeda01000, 0xfff01e00, + &avr32_syntax_table[AVR32_SYNTAX_LDCM_W_PU], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + &avr32_ifield_table[AVR32_IFIELD_CM_HL], + }, + }, + { + AVR32_OPC_LDDPC, 2, 0x48000000, 0xf8000000, + &avr32_syntax_table[AVR32_SYNTAX_LDDPC], + BFD_RELOC_AVR32_9UW_PCREL, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K7C], + }, + }, + { + AVR32_OPC_LDDPC_EXT, 4, 0xfef00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_LDDPC_EXT], + BFD_RELOC_AVR32_16B_PCREL, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LDDSP, 2, 0x40000000, 0xf8000000, + &avr32_syntax_table[AVR32_SYNTAX_LDDSP], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K7C], + }, + }, + { + AVR32_OPC_LDINS_B, 4, 0xe1d04000, 0xe1f0c000, + &avr32_syntax_table[AVR32_SYNTAX_LDINS_B], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_PART2_K12], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K12], + }, + }, + { + AVR32_OPC_LDINS_H, 4, 0xe1d00000, 0xe1f0e000, + &avr32_syntax_table[AVR32_SYNTAX_LDINS_H], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_PART1_K12], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K12], + }, + }, + { + AVR32_OPC_LDM, 4, 0xe1c00000, 0xfdf00000, + &avr32_syntax_table[AVR32_SYNTAX_LDM], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_W], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LDMTS, 4, 0xe5c00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_LDMTS], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LDMTS_PU, 4, 0xe7c00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_LDMTS_PU], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_LDSWP_SH, 4, 0xe1d02000, 0xe1f0f000, + &avr32_syntax_table[AVR32_SYNTAX_LDSWP_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K12], + }, + }, + { + AVR32_OPC_LDSWP_UH, 4, 0xe1d03000, 0xe1f0f000, + &avr32_syntax_table[AVR32_SYNTAX_LDSWP_UH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K12], + }, + }, + { + AVR32_OPC_LDSWP_W, 4, 0xe1d08000, 0xe1f0f000, + &avr32_syntax_table[AVR32_SYNTAX_LDSWP_W], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K12], + }, + }, + { + AVR32_OPC_LSL1, 4, 0xe0000940, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_LSL1], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_LSL3, 4, 0xe0001500, 0xe1f0ffe0, + &avr32_syntax_table[AVR32_SYNTAX_LSL3], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K5E], + }, + }, + { + AVR32_OPC_LSL2, 2, 0xa1600000, 0xe1e00000, + &avr32_syntax_table[AVR32_SYNTAX_LSL2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_BIT5C], + }, + }, + { + AVR32_OPC_LSR1, 4, 0xe0000a40, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_LSR1], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_LSR3, 4, 0xe0001600, 0xe1f0ffe0, + &avr32_syntax_table[AVR32_SYNTAX_LSR3], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K5E], + }, + }, + { + AVR32_OPC_LSR2, 2, 0xa1800000, 0xe1e00000, + &avr32_syntax_table[AVR32_SYNTAX_LSR2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_BIT5C], + }, + }, + { + AVR32_OPC_MAC, 4, 0xe0000340, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_MAC], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MACHH_D, 4, 0xe0000580, 0xe1f0ffc1, + &avr32_syntax_table[AVR32_SYNTAX_MACHH_D], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MACHH_W, 4, 0xe0000480, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_MACHH_W], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MACS_D, 4, 0xe0000540, 0xe1f0fff1, + &avr32_syntax_table[AVR32_SYNTAX_MACS_D], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MACSATHH_W, 4, 0xe0000680, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_MACSATHH_W], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MACUD, 4, 0xe0000740, 0xe1f0fff1, + &avr32_syntax_table[AVR32_SYNTAX_MACUD], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MACWH_D, 4, 0xe0000c80, 0xe1f0ffe1, + &avr32_syntax_table[AVR32_SYNTAX_MACWH_D], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MAX, 4, 0xe0000c40, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_MAX], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MCALL, 4, 0xf0100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_MCALL], + BFD_RELOC_AVR32_18W_PCREL, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_MFDR, 4, 0xe5b00000, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MFDR], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MFSR, 4, 0xe1b00000, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MFSR], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MIN, 4, 0xe0000d40, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_MIN], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MOV3, 2, 0x00900000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_MOV3], + BFD_RELOC_NONE, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOV1, 2, 0x30000000, 0xf0000000, + &avr32_syntax_table[AVR32_SYNTAX_MOV1], + BFD_RELOC_AVR32_8S, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_MOV2, 4, 0xe0600000, 0xe1e00000, + &avr32_syntax_table[AVR32_SYNTAX_MOV2], + BFD_RELOC_AVR32_21S, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_MOVEQ1, 4, 0xe0001700, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVEQ1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVNE1, 4, 0xe0001710, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVNE1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVCC1, 4, 0xe0001720, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVHS1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVCS1, 4, 0xe0001730, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVLO1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVGE1, 4, 0xe0001740, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVGE1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVLT1, 4, 0xe0001750, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVLT1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVMI1, 4, 0xe0001760, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVMI1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVPL1, 4, 0xe0001770, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVPL1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVLS1, 4, 0xe0001780, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVLS1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVGT1, 4, 0xe0001790, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVGT1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVLE1, 4, 0xe00017a0, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVLE1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVHI1, 4, 0xe00017b0, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVHI1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVVS1, 4, 0xe00017c0, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVVS1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVVC1, 4, 0xe00017d0, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVVC1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVQS1, 4, 0xe00017e0, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVQS1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVAL1, 4, 0xe00017f0, 0xe1f0ffff, + &avr32_syntax_table[AVR32_SYNTAX_MOVAL1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MOVEQ2, 4, 0xf9b00000, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVEQ2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVNE2, 4, 0xf9b00100, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVNE2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVCC2, 4, 0xf9b00200, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVHS2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVCS2, 4, 0xf9b00300, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVLO2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVGE2, 4, 0xf9b00400, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVGE2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVLT2, 4, 0xf9b00500, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVLT2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVMI2, 4, 0xf9b00600, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVMI2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVPL2, 4, 0xf9b00700, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVPL2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVLS2, 4, 0xf9b00800, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVLS2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVGT2, 4, 0xf9b00900, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVGT2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVLE2, 4, 0xf9b00a00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVLE2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVHI2, 4, 0xf9b00b00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVHI2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVVS2, 4, 0xf9b00c00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVVS2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVVC2, 4, 0xf9b00d00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVVC2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVQS2, 4, 0xf9b00e00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVQS2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MOVAL2, 4, 0xf9b00f00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MOVAL2], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MTDR, 4, 0xe7b00000, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MTDR], + BFD_RELOC_AVR32_8S_EXT, 2, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8E], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MTSR, 4, 0xe3b00000, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MTSR], + BFD_RELOC_AVR32_8S_EXT, 2, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8E], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MUL1, 2, 0xa1300000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_MUL1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_MUL2, 4, 0xe0000240, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_MUL2], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MUL3, 4, 0xe0001000, 0xe1f0ff00, + &avr32_syntax_table[AVR32_SYNTAX_MUL3], + BFD_RELOC_AVR32_8S_EXT, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_MULHH_W, 4, 0xe0000780, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_MULHH_W], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MULNHH_W, 4, 0xe0000180, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_MULNHH_W], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MULNWH_D, 4, 0xe0000280, 0xe1f0ffe1, + &avr32_syntax_table[AVR32_SYNTAX_MULNWH_D], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MULSD, 4, 0xe0000440, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_MULSD], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MULSATHH_H, 4, 0xe0000880, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_H], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MULSATHH_W, 4, 0xe0000980, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_W], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MULSATRNDHH_H, 4, 0xe0000a80, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDHH_H], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MULSATRNDWH_W, 4, 0xe0000b80, 0xe1f0ffe0, + &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDWH_W], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MULSATWH_W, 4, 0xe0000e80, 0xe1f0ffe0, + &avr32_syntax_table[AVR32_SYNTAX_MULSATWH_W], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MULU_D, 4, 0xe0000640, 0xe1f0fff1, + &avr32_syntax_table[AVR32_SYNTAX_MULU_D], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MULWH_D, 4, 0xe0000d80, 0xe1f0ffe1, + &avr32_syntax_table[AVR32_SYNTAX_MULWH_D], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_MUSFR, 2, 0x5d300000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_MUSFR], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_MUSTR, 2, 0x5d200000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_MUSTR], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_MVCR_D, 4, 0xefa00010, 0xfff111ff, + &avr32_syntax_table[AVR32_SYNTAX_MVCR_D], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + }, + }, + { + AVR32_OPC_MVCR_W, 4, 0xefa00000, 0xfff010ff, + &avr32_syntax_table[AVR32_SYNTAX_MVCR_W], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + }, + }, + { + AVR32_OPC_MVRC_D, 4, 0xefa00030, 0xfff111ff, + &avr32_syntax_table[AVR32_SYNTAX_MVRC_D], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + }, + }, + { + AVR32_OPC_MVRC_W, 4, 0xefa00020, 0xfff010ff, + &avr32_syntax_table[AVR32_SYNTAX_MVRC_W], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_NEG, 2, 0x5c300000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_NEG], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_NOP, 2, 0xd7030000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_NOP], + BFD_RELOC_UNUSED, 0, -1, { NULL }, + }, + { + AVR32_OPC_OR1, 2, 0x00400000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_OR1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_OR2, 4, 0xe1e01000, 0xe1f0fe00, + &avr32_syntax_table[AVR32_SYNTAX_OR2], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E2], + }, + }, + { + AVR32_OPC_OR3, 4, 0xe1e01200, 0xe1f0fe00, + &avr32_syntax_table[AVR32_SYNTAX_OR3], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E2], + }, + }, + { + AVR32_OPC_ORH, 4, 0xea100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ORH], + BFD_RELOC_AVR32_16U, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_ORL, 4, 0xe8100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ORL], + BFD_RELOC_AVR32_16U, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_PABS_SB, 4, 0xe00023e0, 0xfff0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PABS_SB], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PABS_SH, 4, 0xe00023f0, 0xfff0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PABS_SH], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PACKSH_SB, 4, 0xe00024d0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PACKSH_SB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PACKSH_UB, 4, 0xe00024c0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PACKSH_UB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PACKW_SH, 4, 0xe0002470, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PACKW_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADD_B, 4, 0xe0002300, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADD_B], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADD_H, 4, 0xe0002000, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADD_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDH_SH, 4, 0xe00020c0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDH_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDH_UB, 4, 0xe0002360, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDH_UB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDS_SB, 4, 0xe0002320, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDS_SB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDS_SH, 4, 0xe0002040, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDS_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDS_UB, 4, 0xe0002340, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDS_UB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDS_UH, 4, 0xe0002080, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDS_UH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDSUB_H, 4, 0xe0002100, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_PADDSUB_H], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PADDSUBH_SH, 4, 0xe0002280, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_PADDSUBH_SH], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PADDSUBS_SH, 4, 0xe0002180, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_SH], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PADDSUBS_UH, 4, 0xe0002200, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_UH], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PADDX_H, 4, 0xe0002020, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDX_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDXH_SH, 4, 0xe00020e0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDXH_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDXS_SH, 4, 0xe0002060, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDXS_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PADDXS_UH, 4, 0xe00020a0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PADDXS_UH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PASR_B, 4, 0xe0002410, 0xe1f8fff0, + &avr32_syntax_table[AVR32_SYNTAX_PASR_B], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_COND3], + }, + }, + { + AVR32_OPC_PASR_H, 4, 0xe0002440, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PASR_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PAVG_SH, 4, 0xe00023d0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PAVG_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PAVG_UB, 4, 0xe00023c0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PAVG_UB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PLSL_B, 4, 0xe0002420, 0xe1f8fff0, + &avr32_syntax_table[AVR32_SYNTAX_PLSL_B], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_COND3], + }, + }, + { + AVR32_OPC_PLSL_H, 4, 0xe0002450, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PLSL_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PLSR_B, 4, 0xe0002430, 0xe1f8fff0, + &avr32_syntax_table[AVR32_SYNTAX_PLSR_B], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_COND3], + }, + }, + { + AVR32_OPC_PLSR_H, 4, 0xe0002460, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PLSR_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PMAX_SH, 4, 0xe0002390, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PMAX_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PMAX_UB, 4, 0xe0002380, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PMAX_UB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PMIN_SH, 4, 0xe00023b0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PMIN_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PMIN_UB, 4, 0xe00023a0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PMIN_UB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_POPJC, 2, 0xd7130000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_POPJC], + BFD_RELOC_UNUSED, 0, -1, { NULL }, + }, + { + AVR32_OPC_POPM, 2, 0xd0020000, 0xf0070000, + &avr32_syntax_table[AVR32_SYNTAX_POPM], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_POPM], + }, + }, + { + AVR32_OPC_POPM_E, 4, 0xe3cd0000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_POPM_E], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_PREF, 4, 0xf2100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_PREF], + BFD_RELOC_AVR32_16S, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_PSAD, 4, 0xe0002400, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSAD], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUB_B, 4, 0xe0002310, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUB_B], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUB_H, 4, 0xe0002010, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUB_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBADD_H, 4, 0xe0002140, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBADD_H], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PSUBADDH_SH, 4, 0xe00022c0, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBADDH_SH], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PSUBADDS_SH, 4, 0xe00021c0, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_SH], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PSUBADDS_UH, 4, 0xe0002240, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_UH], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PSUBH_SH, 4, 0xe00020d0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBH_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBH_UB, 4, 0xe0002370, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBH_UB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBS_SB, 4, 0xe0002330, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBS_SH, 4, 0xe0002050, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBS_UB, 4, 0xe0002350, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UB], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBS_UH, 4, 0xe0002090, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBX_H, 4, 0xe0002030, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBX_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBXH_SH, 4, 0xe00020f0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBXH_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBXS_SH, 4, 0xe0002070, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_SH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PSUBXS_UH, 4, 0xe00020b0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_UH], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_PUNPCKSB_H, 4, 0xe00024a0, 0xe1ffffe0, + &avr32_syntax_table[AVR32_SYNTAX_PUNPCKSB_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PUNPCKUB_H, 4, 0xe0002480, 0xe1ffffe0, + &avr32_syntax_table[AVR32_SYNTAX_PUNPCKUB_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_PUSHJC, 2, 0xd7230000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_PUSHJC], + BFD_RELOC_UNUSED, 0, -1, { NULL }, + }, + { + AVR32_OPC_PUSHM, 2, 0xd0010000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_PUSHM], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_PUSHM_E, 4, 0xebcd0000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_PUSHM_E], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_RCALL1, 2, 0xc00c0000, 0xf00c0000, + &avr32_syntax_table[AVR32_SYNTAX_RCALL1], + BFD_RELOC_AVR32_11H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K10], + }, + }, + { + AVR32_OPC_RCALL2, 4, 0xe0a00000, 0xe1ef0000, + &avr32_syntax_table[AVR32_SYNTAX_RCALL2], + BFD_RELOC_AVR32_22H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_RETEQ, 2, 0x5e000000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETEQ], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETNE, 2, 0x5e100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETNE], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETCC, 2, 0x5e200000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETHS], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETCS, 2, 0x5e300000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETLO], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETGE, 2, 0x5e400000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETGE], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETLT, 2, 0x5e500000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETLT], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETMI, 2, 0x5e600000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETMI], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETPL, 2, 0x5e700000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETPL], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETLS, 2, 0x5e800000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETLS], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETGT, 2, 0x5e900000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETGT], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETLE, 2, 0x5ea00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETLE], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETHI, 2, 0x5eb00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETHI], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETVS, 2, 0x5ec00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETVS], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETVC, 2, 0x5ed00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETVC], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETQS, 2, 0x5ee00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETQS], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETAL, 2, 0x5ef00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_RETAL], + BFD_RELOC_NONE, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_RETD, 2, 0xd6230000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_RETD], + BFD_RELOC_NONE, 0, -1, { NULL }, + }, + { + AVR32_OPC_RETE, 2, 0xd6030000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_RETE], + BFD_RELOC_NONE, 0, -1, { NULL }, + }, + { + AVR32_OPC_RETJ, 2, 0xd6330000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_RETJ], + BFD_RELOC_NONE, 0, -1, { NULL }, + }, + { + AVR32_OPC_RETS, 2, 0xd6130000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_RETS], + BFD_RELOC_NONE, 0, -1, { NULL }, + }, + { + AVR32_OPC_RJMP, 2, 0xc0080000, 0xf00c0000, + &avr32_syntax_table[AVR32_SYNTAX_RJMP], + BFD_RELOC_AVR32_11H_PCREL, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K10], + }, + }, + { + AVR32_OPC_ROL, 2, 0x5cf00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ROL], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_ROR, 2, 0x5d000000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_ROR], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_RSUB1, 2, 0x00200000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_RSUB1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_RSUB2, 4, 0xe0001100, 0xe1f0ff00, + &avr32_syntax_table[AVR32_SYNTAX_RSUB2], + BFD_RELOC_AVR32_8S_EXT, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SATADD_H, 4, 0xe00002c0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_SATADD_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SATADD_W, 4, 0xe00000c0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_SATADD_W], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SATRNDS, 4, 0xf3b00000, 0xfff0fc00, + &avr32_syntax_table[AVR32_SYNTAX_SATRNDS], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E], + &avr32_ifield_table[AVR32_IFIELD_S5], + }, + }, + { + AVR32_OPC_SATRNDU, 4, 0xf3b00400, 0xfff0fc00, + &avr32_syntax_table[AVR32_SYNTAX_SATRNDU], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E], + &avr32_ifield_table[AVR32_IFIELD_S5], + }, + }, + { + AVR32_OPC_SATS, 4, 0xf1b00000, 0xfff0fc00, + &avr32_syntax_table[AVR32_SYNTAX_SATS], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E], + &avr32_ifield_table[AVR32_IFIELD_S5], + }, + }, + { + AVR32_OPC_SATSUB_H, 4, 0xe00003c0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_SATSUB_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SATSUB_W1, 4, 0xe00001c0, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W1], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SATSUB_W2, 4, 0xe0d00000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W2], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_SATU, 4, 0xf1b00400, 0xfff0fc00, + &avr32_syntax_table[AVR32_SYNTAX_SATU], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K5E], + &avr32_ifield_table[AVR32_IFIELD_S5], + }, + }, + { + AVR32_OPC_SBC, 4, 0xe0000140, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_SBC], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SBR, 2, 0xa1a00000, 0xe1e00000, + &avr32_syntax_table[AVR32_SYNTAX_SBR], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_BIT5C], + }, + }, + { + AVR32_OPC_SCALL, 2, 0xd7330000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_SCALL], + BFD_RELOC_UNUSED, 0, -1, { NULL }, + }, + { + AVR32_OPC_SCR, 2, 0x5c100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SCR], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SLEEP, 4, 0xe9b00000, 0xffffff00, + &avr32_syntax_table[AVR32_SYNTAX_SLEEP], + BFD_RELOC_AVR32_8S_EXT, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SREQ, 2, 0x5f000000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SREQ], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRNE, 2, 0x5f100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRNE], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRCC, 2, 0x5f200000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRHS], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRCS, 2, 0x5f300000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRLO], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRGE, 2, 0x5f400000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRGE], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRLT, 2, 0x5f500000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRLT], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRMI, 2, 0x5f600000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRMI], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRPL, 2, 0x5f700000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRPL], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRLS, 2, 0x5f800000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRLS], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRGT, 2, 0x5f900000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRGT], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRLE, 2, 0x5fa00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRLE], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRHI, 2, 0x5fb00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRHI], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRVS, 2, 0x5fc00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRVS], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRVC, 2, 0x5fd00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRVC], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRQS, 2, 0x5fe00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRQS], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SRAL, 2, 0x5ff00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SRAL], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SSRF, 2, 0xd2030000, 0xfe0f0000, + &avr32_syntax_table[AVR32_SYNTAX_SSRF], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_K5C], + }, + }, + { + AVR32_OPC_ST_B1, 2, 0x00c00000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ST_B1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_B2, 2, 0x00f00000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ST_B2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_B5, 4, 0xe0000b00, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_ST_B5], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + &avr32_ifield_table[AVR32_IFIELD_RD_E], + }, + }, + { + AVR32_OPC_ST_B3, 2, 0xa0800000, 0xe1800000, + &avr32_syntax_table[AVR32_SYNTAX_ST_B3], + BFD_RELOC_AVR32_3U, 3, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K3], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_B4, 4, 0xe1600000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ST_B4], + BFD_RELOC_AVR32_16S, 3, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_D1, 2, 0xa1200000, 0xe1f10000, + &avr32_syntax_table[AVR32_SYNTAX_ST_D1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + }, + }, + { + AVR32_OPC_ST_D2, 2, 0xa1210000, 0xe1f10000, + &avr32_syntax_table[AVR32_SYNTAX_ST_D2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + }, + }, + { + AVR32_OPC_ST_D3, 2, 0xa1110000, 0xe1f10000, + &avr32_syntax_table[AVR32_SYNTAX_ST_D3], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + }, + }, + { + AVR32_OPC_ST_D5, 4, 0xe0000800, 0xe1f0ffc1, + &avr32_syntax_table[AVR32_SYNTAX_ST_D5], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + &avr32_ifield_table[AVR32_IFIELD_RD_DW], + }, + }, + { + AVR32_OPC_ST_D4, 4, 0xe0e10000, 0xe1f10000, + &avr32_syntax_table[AVR32_SYNTAX_ST_D4], + BFD_RELOC_AVR32_16S, 3, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + &avr32_ifield_table[AVR32_IFIELD_RY_DW], + }, + }, + { + AVR32_OPC_ST_H1, 2, 0x00b00000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ST_H1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_H2, 2, 0x00e00000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ST_H2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_H5, 4, 0xe0000a00, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_ST_H5], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + &avr32_ifield_table[AVR32_IFIELD_RD_E], + }, + }, + { + AVR32_OPC_ST_H3, 2, 0xa0000000, 0xe1800000, + &avr32_syntax_table[AVR32_SYNTAX_ST_H3], + BFD_RELOC_AVR32_4UH, 3, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K3], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_H4, 4, 0xe1500000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ST_H4], + BFD_RELOC_AVR32_16S, 3, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_W1, 2, 0x00a00000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ST_W1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_W2, 2, 0x00d00000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ST_W2], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_W5, 4, 0xe0000900, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_ST_W5], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + &avr32_ifield_table[AVR32_IFIELD_RD_E], + }, + }, + { + AVR32_OPC_ST_W3, 2, 0x81000000, 0xe1000000, + &avr32_syntax_table[AVR32_SYNTAX_ST_W3], + BFD_RELOC_AVR32_6UW, 3, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K4], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_ST_W4, 4, 0xe1400000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_ST_W4], + BFD_RELOC_AVR32_16S, 3, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_STC_D1, 4, 0xeba01000, 0xfff01100, + &avr32_syntax_table[AVR32_SYNTAX_STC_D1], + BFD_RELOC_AVR32_10UW, 4, 2, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + }, + }, + { + AVR32_OPC_STC_D2, 4, 0xefa00070, 0xfff011f0, + &avr32_syntax_table[AVR32_SYNTAX_STC_D2], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + }, + }, + { + AVR32_OPC_STC_D3, 4, 0xefa010c0, 0xfff011c0, + &avr32_syntax_table[AVR32_SYNTAX_STC_D3], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_K2], + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + }, + }, + { + AVR32_OPC_STC_W1, 4, 0xeba00000, 0xfff01000, + &avr32_syntax_table[AVR32_SYNTAX_STC_W1], + BFD_RELOC_AVR32_10UW, 4, 2, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + }, + }, + { + AVR32_OPC_STC_W2, 4, 0xefa00060, 0xfff010ff, + &avr32_syntax_table[AVR32_SYNTAX_STC_W2], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + }, + }, + { + AVR32_OPC_STC_W3, 4, 0xefa01080, 0xfff010c0, + &avr32_syntax_table[AVR32_SYNTAX_STC_W3], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_K2], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + }, + }, + { + AVR32_OPC_STC0_D, 4, 0xf7a00000, 0xfff00100, + &avr32_syntax_table[AVR32_SYNTAX_STC0_D], + BFD_RELOC_AVR32_14UW, 3, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K12CP], + &avr32_ifield_table[AVR32_IFIELD_CRD_DW], + }, + }, + { + AVR32_OPC_STC0_W, 4, 0xf5a00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_STC0_W], + BFD_RELOC_AVR32_14UW, 3, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K12CP], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + }, + }, + { + AVR32_OPC_STCM_D, 4, 0xeda00500, 0xfff01f00, + &avr32_syntax_table[AVR32_SYNTAX_STCM_D], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_STCM_D_PU, 4, 0xeda01500, 0xfff01f00, + &avr32_syntax_table[AVR32_SYNTAX_STCM_D_PU], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_STCM_W, 4, 0xeda00200, 0xfff01e00, + &avr32_syntax_table[AVR32_SYNTAX_STCM_W], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + &avr32_ifield_table[AVR32_IFIELD_CM_HL], + }, + }, + { + AVR32_OPC_STCM_W_PU, 4, 0xeda01200, 0xfff01e00, + &avr32_syntax_table[AVR32_SYNTAX_STCM_W_PU], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_CPNO], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + &avr32_ifield_table[AVR32_IFIELD_CM_HL], + }, + }, + { + AVR32_OPC_STCOND, 4, 0xe1700000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_STCOND], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_STDSP, 2, 0x50000000, 0xf8000000, + &avr32_syntax_table[AVR32_SYNTAX_STDSP], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_K7C], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_STHH_W2, 4, 0xe1e08000, 0xe1f0c0c0, + &avr32_syntax_table[AVR32_SYNTAX_STHH_W2], + BFD_RELOC_UNUSED, 7, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_CRD_RI], + &avr32_ifield_table[AVR32_IFIELD_K2], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X2], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y2], + }, + }, + { + AVR32_OPC_STHH_W1, 4, 0xe1e0c000, 0xe1f0c000, + &avr32_syntax_table[AVR32_SYNTAX_STHH_W1], + BFD_RELOC_AVR32_STHH_W, 6, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_K8E2], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X2], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y2], + }, + }, + { + AVR32_OPC_STM, 4, 0xe9c00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_STM], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_STM_PU, 4, 0xebc00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_STM_PU], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_STMTS, 4, 0xedc00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_STMTS], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_STMTS_PU, 4, 0xefc00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_STMTS_PU], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_STSWP_H, 4, 0xe1d09000, 0xe1f0f000, + &avr32_syntax_table[AVR32_SYNTAX_STSWP_H], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K12], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_STSWP_W, 4, 0xe1d0a000, 0xe1f0f000, + &avr32_syntax_table[AVR32_SYNTAX_STSWP_W], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K12], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_SUB1, 2, 0x00100000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_SUB1], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_SUB2, 4, 0xe0000100, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_SUB2], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K2], + }, + }, + { + AVR32_OPC_SUB5, 4, 0xe0c00000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_SUB5], + BFD_RELOC_AVR32_SUB5, 3, 2, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_K16], + }, + }, + { + AVR32_OPC_SUB3_SP, 2, 0x200d0000, 0xf00f0000, + &avr32_syntax_table[AVR32_SYNTAX_SUB3_SP], + BFD_RELOC_AVR32_10SW, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_SUB3, 2, 0x20000000, 0xf0000000, + &avr32_syntax_table[AVR32_SYNTAX_SUB3], + BFD_RELOC_AVR32_8S, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8C], + }, + }, + { + AVR32_OPC_SUB4, 4, 0xe0200000, 0xe1e00000, + &avr32_syntax_table[AVR32_SYNTAX_SUB4], + BFD_RELOC_AVR32_21S, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K21], + }, + }, + { + AVR32_OPC_SUBEQ, 4, 0xf7b00000, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBEQ], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBNE, 4, 0xf7b00100, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBNE], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBCC, 4, 0xf7b00200, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBHS], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBCS, 4, 0xf7b00300, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBLO], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBGE, 4, 0xf7b00400, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBGE], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBLT, 4, 0xf7b00500, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBLT], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBMI, 4, 0xf7b00600, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBMI], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBPL, 4, 0xf7b00700, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBPL], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBLS, 4, 0xf7b00800, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBLS], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBGT, 4, 0xf7b00900, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBGT], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBLE, 4, 0xf7b00a00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBLE], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBHI, 4, 0xf7b00b00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBHI], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBVS, 4, 0xf7b00c00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBVS], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBVC, 4, 0xf7b00d00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBVC], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBQS, 4, 0xf7b00e00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBQS], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBAL, 4, 0xf7b00f00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBAL], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFEQ, 4, 0xf5b00000, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFEQ], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFNE, 4, 0xf5b00100, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFNE], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFCC, 4, 0xf5b00200, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFHS], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFCS, 4, 0xf5b00300, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFLO], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFGE, 4, 0xf5b00400, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFGE], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFLT, 4, 0xf5b00500, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFLT], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFMI, 4, 0xf5b00600, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFMI], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFPL, 4, 0xf5b00700, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFPL], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFLS, 4, 0xf5b00800, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFLS], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFGT, 4, 0xf5b00900, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFGT], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFLE, 4, 0xf5b00a00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFLE], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFHI, 4, 0xf5b00b00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFHI], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFVS, 4, 0xf5b00c00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFVS], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFVC, 4, 0xf5b00d00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFVC], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFQS, 4, 0xf5b00e00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFQS], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBFAL, 4, 0xf5b00f00, 0xfff0ff00, + &avr32_syntax_table[AVR32_SYNTAX_SUBFAL], + BFD_RELOC_AVR32_8S_EXT, 2, 1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_K8E], + }, + }, + { + AVR32_OPC_SUBHH_W, 4, 0xe0000f00, 0xe1f0ffc0, + &avr32_syntax_table[AVR32_SYNTAX_SUBHH_W], + BFD_RELOC_UNUSED, 5, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_X], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_Y], + }, + }, + { + AVR32_OPC_SWAP_B, 2, 0x5cb00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SWAP_B], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_SWAP_BH, 2, 0x5cc00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SWAP_BH], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_SWAP_H, 2, 0x5ca00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_SWAP_H], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_SYNC, 4, 0xebb00000, 0xffffff00, + &avr32_syntax_table[AVR32_SYNTAX_SYNC], + BFD_RELOC_AVR32_8S_EXT, 1, 0, + { + &avr32_ifield_table[AVR32_IFIELD_K8E], + } + }, + { + AVR32_OPC_TLBR, 2, 0xd6430000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_TLBR], + BFD_RELOC_UNUSED, 0, -1, { NULL }, + }, + { + AVR32_OPC_TLBS, 2, 0xd6530000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_TLBS], + BFD_RELOC_UNUSED, 0, -1, { NULL }, + }, + { + AVR32_OPC_TLBW, 2, 0xd6630000, 0xffff0000, + &avr32_syntax_table[AVR32_SYNTAX_TLBW], + BFD_RELOC_UNUSED, 0, -1, { NULL }, + }, + { + AVR32_OPC_TNBZ, 2, 0x5ce00000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_TNBZ], + BFD_RELOC_UNUSED, 1, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + } + }, + { + AVR32_OPC_TST, 2, 0x00700000, 0xe1f00000, + &avr32_syntax_table[AVR32_SYNTAX_TST], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_RX], + }, + }, + { + AVR32_OPC_XCHG, 4, 0xe0000b40, 0xe1f0fff0, + &avr32_syntax_table[AVR32_SYNTAX_XCHG], + BFD_RELOC_UNUSED, 3, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RD_E], + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + }, + }, + { + AVR32_OPC_MEMC, 4, 0xf6100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_MEMC], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_MEM15], + &avr32_ifield_table[AVR32_IFIELD_MEMB5], + }, + }, + { + AVR32_OPC_MEMS, 4, 0xf8100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_MEMS], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_MEM15], + &avr32_ifield_table[AVR32_IFIELD_MEMB5], + }, + }, + { + AVR32_OPC_MEMT, 4, 0xfa100000, 0xfff00000, + &avr32_syntax_table[AVR32_SYNTAX_MEMT], + BFD_RELOC_UNUSED, 2, -1, + { + &avr32_ifield_table[AVR32_IFIELD_MEM15], + &avr32_ifield_table[AVR32_IFIELD_MEMB5], + }, + }, + { + AVR32_OPC_BFEXTS, 4, 0xe1d0b000, 0xe1f0fc00, + &avr32_syntax_table[AVR32_SYNTAX_BFEXTS], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_S5], + &avr32_ifield_table[AVR32_IFIELD_K5E], + }, + }, + { + AVR32_OPC_BFEXTU, 4, 0xe1d0c000, 0xe1f0fc00, + &avr32_syntax_table[AVR32_SYNTAX_BFEXTU], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_S5], + &avr32_ifield_table[AVR32_IFIELD_K5E], + }, + }, + { + AVR32_OPC_BFINS, 4, 0xe1d0d000, 0xe1f0fc00, + &avr32_syntax_table[AVR32_SYNTAX_BFINS], + BFD_RELOC_UNUSED, 4, -1, + { + &avr32_ifield_table[AVR32_IFIELD_RX], + &avr32_ifield_table[AVR32_IFIELD_RY], + &avr32_ifield_table[AVR32_IFIELD_S5], + &avr32_ifield_table[AVR32_IFIELD_K5E], + }, + }, + }; + +#define FPALIAS_DXY(name, opcode) \ + { \ + AVR32_ALIAS_##name##_S, \ + &avr32_opc_table[AVR32_OPC_COP], \ + { \ + { 0, 0 }, \ + { 1, 0 }, { 1, 1 }, { 1, 2 }, \ + { 0, opcode }, \ + }, \ + }, { \ + AVR32_ALIAS_##name##_D, \ + &avr32_opc_table[AVR32_OPC_COP], \ + { \ + { 0, 0 }, \ + { 1, 0 }, { 1, 1 }, { 1, 2 }, \ + { 0, (opcode) | 0x40 }, \ + }, \ + } +#define FPALIAS_DX(name, opcode) \ + { \ + AVR32_ALIAS_##name##_S, \ + &avr32_opc_table[AVR32_OPC_COP], \ + { \ + { 0, 0 }, \ + { 1, 0 }, { 1, 1 }, { 0, 0 }, \ + { 0, opcode }, \ + }, \ + }, { \ + AVR32_ALIAS_##name##_D, \ + &avr32_opc_table[AVR32_OPC_COP], \ + { \ + { 0, 0 }, \ + { 1, 0 }, { 1, 1 }, { 0, 0 }, \ + { 0, (opcode) | 0x40 }, \ + }, \ + } +#define FPALIAS_XY(name, opcode) \ + { \ + AVR32_ALIAS_##name##_S, \ + &avr32_opc_table[AVR32_OPC_COP], \ + { \ + { 0, 0 }, \ + { 0, 0 }, { 1, 0 }, { 1, 1 }, \ + { 0, opcode }, \ + }, \ + }, { \ + AVR32_ALIAS_##name##_D, \ + &avr32_opc_table[AVR32_OPC_COP], \ + { \ + { 0, 0 }, \ + { 0, 0 }, { 1, 0 }, { 1, 1 }, \ + { 0, (opcode) | 0x40 }, \ + }, \ + } + +const struct avr32_alias avr32_alias_table[] = + { + FPALIAS_DXY(FMAC, 0x00), + FPALIAS_DXY(FNMAC, 0x01), + FPALIAS_DXY(FMSC, 0x02), + FPALIAS_DXY(FNMSC, 0x03), + FPALIAS_DXY(FADD, 0x04), + FPALIAS_DXY(FSUB, 0x05), + FPALIAS_DXY(FMUL, 0x06), + FPALIAS_DXY(FNMUL, 0x07), + FPALIAS_DX(FNEG, 0x08), + FPALIAS_DX(FABS, 0x09), + FPALIAS_XY(FCMP, 0x0d), + FPALIAS_DX(FMOV1, 0x0a), + { + AVR32_ALIAS_FMOV2_S, + &avr32_opc_table[AVR32_OPC_MVCR_W], + { { 0, 0 }, { 1, 0 }, { 1, 1 }, }, + }, + { + AVR32_ALIAS_FMOV2_D, + &avr32_opc_table[AVR32_OPC_MVCR_D], + { { 0, 0 }, { 1, 0 }, { 1, 1 }, }, + }, + { + AVR32_ALIAS_FMOV3_S, + &avr32_opc_table[AVR32_OPC_MVRC_W], + { { 0, 0 }, { 1, 0 }, { 1, 1 }, }, + }, + { + AVR32_ALIAS_FMOV3_D, + &avr32_opc_table[AVR32_OPC_MVRC_D], + { { 0, 0 }, { 1, 0 }, { 1, 1 }, }, + }, + { + AVR32_ALIAS_FCASTS_D, + &avr32_opc_table[AVR32_OPC_COP], + { + { 0, 0 }, + { 1, 0 }, { 1, 1 }, { 0, 0 }, + { 0, 0x0f }, + }, + }, + { + AVR32_ALIAS_FCASTD_S, + &avr32_opc_table[AVR32_OPC_COP], + { + { 0, 0 }, + { 1, 0 }, { 1, 1 }, { 0, 0 }, + { 0, 0x10 }, + }, + }, + }; + + +#define SYNTAX_NORMAL0(id, mne, opc, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + NULL, 0, { } \ + } +#define SYNTAX_NORMAL1(id, mne, opc, op0, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + NULL, 1, \ + { \ + AVR32_OPERAND_##op0, \ + } \ + } +#define SYNTAX_NORMALM1(id, mne, opc, op0, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + NULL, -1, \ + { \ + AVR32_OPERAND_##op0, \ + } \ + } +#define SYNTAX_NORMAL2(id, mne, opc, op0, op1, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + NULL, 2, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + } \ + } +#define SYNTAX_NORMALM2(id, mne, opc, op0, op1, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + NULL, -2, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + } \ + } +#define SYNTAX_NORMAL3(id, mne, opc, op0, op1, op2, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + NULL, 3, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + AVR32_OPERAND_##op2, \ + } \ + } +#define SYNTAX_NORMALM3(id, mne, opc, op0, op1, op2, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + NULL, -3, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + AVR32_OPERAND_##op2, \ + } \ + } +#define SYNTAX_NORMAL4(id, mne, opc, op0, op1, op2, op3, arch)\ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + NULL, 4, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + AVR32_OPERAND_##op2, AVR32_OPERAND_##op3, \ + } \ + } +#define SYNTAX_NORMAL5(id, mne, opc, op0, op1, op2, op3, op4, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + NULL, 5, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + AVR32_OPERAND_##op2, AVR32_OPERAND_##op3, \ + AVR32_OPERAND_##op4, \ + } \ + } + +#define SYNTAX_NORMAL_C1(id, mne, opc, nxt, op0, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + &avr32_syntax_table[AVR32_SYNTAX_##nxt], 1, \ + { \ + AVR32_OPERAND_##op0, \ + } \ + } +#define SYNTAX_NORMAL_CM1(id, mne, opc, nxt, op0, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + &avr32_syntax_table[AVR32_SYNTAX_##nxt], -1, \ + { \ + AVR32_OPERAND_##op0, \ + } \ + } +#define SYNTAX_NORMAL_C2(id, mne, opc, nxt, op0, op1, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + &avr32_syntax_table[AVR32_SYNTAX_##nxt], 2, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + } \ + } +#define SYNTAX_NORMAL_CM2(id, mne, opc, nxt, op0, op1, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + &avr32_syntax_table[AVR32_SYNTAX_##nxt], -2, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + } \ + } +#define SYNTAX_NORMAL_C3(id, mne, opc, nxt, op0, op1, op2, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + &avr32_syntax_table[AVR32_SYNTAX_##nxt], 3, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + AVR32_OPERAND_##op2, \ + } \ + } +#define SYNTAX_NORMAL_CM3(id, mne, opc, nxt, op0, op1, op2, arch) \ + { \ + AVR32_SYNTAX_##id, arch, \ + &avr32_mnemonic_table[AVR32_MNEMONIC_##mne], \ + AVR32_PARSER_NORMAL, \ + { &avr32_opc_table[AVR32_OPC_##opc], }, \ + &avr32_syntax_table[AVR32_SYNTAX_##nxt], -3, \ + { \ + AVR32_OPERAND_##op0, AVR32_OPERAND_##op1, \ + AVR32_OPERAND_##op2, \ + } \ + } + +#define SYNTAX_FP(name, nr_ops) \ + { \ + AVR32_SYNTAX_##name##_S, \ + AVR32_FP, NULL, AVR32_PARSER_ALIAS, \ + { .alias = &avr32_alias_table[AVR32_ALIAS_##name##_S] }, \ + NULL, nr_ops, \ + { \ + AVR32_OPERAND_FPREG_S, \ + AVR32_OPERAND_FPREG_S, \ + AVR32_OPERAND_FPREG_S, \ + }, \ + }, \ + { \ + AVR32_SYNTAX_##name##_D, \ + AVR32_FP, NULL, AVR32_PARSER_ALIAS, \ + { .alias = &avr32_alias_table[AVR32_ALIAS_##name##_D] }, \ + NULL, nr_ops, \ + { \ + AVR32_OPERAND_FPREG_D, \ + AVR32_OPERAND_FPREG_D, \ + AVR32_OPERAND_FPREG_D, \ + }, \ + } + +const struct avr32_syntax avr32_syntax_table[] = + { + SYNTAX_NORMAL1(ABS, ABS, ABS, INTREG, AVR32_V1), + SYNTAX_NORMAL1(ACALL, ACALL, ACALL, UNSIGNED_CONST_W, AVR32_V1), + SYNTAX_NORMAL1(ACR, ACR, ACR, INTREG,AVR32_V1), + SYNTAX_NORMAL3(ADC, ADC, ADC, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ADD1, ADD, ADD1, ADD2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(ADD2, ADD, ADD2, INTREG, INTREG, INTREG_LSL, AVR32_V1), + SYNTAX_NORMAL3(ADDABS, ADDABS, ADDABS, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(ADDHH_W, ADDHH_W, ADDHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL_C2(AND1, AND, AND1, AND2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(AND2, AND, AND2, AND3, INTREG, INTREG, INTREG_LSL, AVR32_V1), + SYNTAX_NORMAL3(AND3, AND, AND3, INTREG, INTREG, INTREG_LSR, AVR32_V1), + SYNTAX_NORMAL_C2(ANDH, ANDH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL3(ANDH_COH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1), + SYNTAX_NORMAL_C2(ANDL, ANDL, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL3(ANDL_COH, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1), + SYNTAX_NORMAL2(ANDN, ANDN, ANDN, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(ASR1, ASR, ASR1, ASR3, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(ASR3, ASR, ASR3, ASR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL2(ASR2, ASR, ASR2, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL4(BFEXTS, BFEXTS, BFEXTS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL4(BFEXTU, BFEXTU, BFEXTU, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL4(BFINS, BFINS, BFINS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL2(BLD, BLD, BLD, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL_C1(BREQ1, BREQ, BREQ1, BREQ2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL_C1(BRNE1, BRNE, BRNE1, BRNE2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL_C1(BRCC1, BRCC, BRCC1, BRCC2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL_C1(BRCS1, BRCS, BRCS1, BRCS2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL_C1(BRGE1, BRGE, BRGE1, BRGE2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL_C1(BRLT1, BRLT, BRLT1, BRLT2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL_C1(BRMI1, BRMI, BRMI1, BRMI2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL_C1(BRPL1, BRPL, BRPL1, BRPL2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL_C1(BRHS1, BRHS, BRCC1, BRHS2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL_C1(BRLO1, BRLO, BRCS1, BRLO2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BREQ2, BREQ, BREQ2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRNE2, BRNE, BRNE2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRCC2, BRCC, BRCC2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRCS2, BRCS, BRCS2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRGE2, BRGE, BRGE2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRLT2, BRLT, BRLT2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRMI2, BRMI, BRMI2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRPL2, BRPL, BRPL2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRLS, BRLS, BRLS, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRGT, BRGT, BRGT, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRLE, BRLE, BRLE, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRHI, BRHI, BRHI, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRVS, BRVS, BRVS, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRVC, BRVC, BRVC, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRQS, BRQS, BRQS, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRAL, BRAL, BRAL, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRHS2, BRHS, BRCC2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(BRLO2, BRLO, BRCS2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL0(BREAKPOINT, BREAKPOINT, BREAKPOINT, AVR32_V1), + SYNTAX_NORMAL1(BREV, BREV, BREV, INTREG, AVR32_V1), + SYNTAX_NORMAL2(BST, BST, BST, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL2(CACHE, CACHE, CACHE, INTREG_SDISP, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL1(CASTS_B, CASTS_B, CASTS_B, INTREG, AVR32_V1), + SYNTAX_NORMAL1(CASTS_H, CASTS_H, CASTS_H, INTREG, AVR32_V1), + SYNTAX_NORMAL1(CASTU_B, CASTU_B, CASTU_B, INTREG, AVR32_V1), + SYNTAX_NORMAL1(CASTU_H, CASTU_H, CASTU_H, INTREG, AVR32_V1), + SYNTAX_NORMAL2(CBR, CBR, CBR, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL2(CLZ, CLZ, CLZ, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL1(COM, COM, COM, INTREG, AVR32_V1), + SYNTAX_NORMAL5(COP, COP, COP, CPNO, CPREG, CPREG, CPREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL2(CP_B, CP_B, CP_B, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL2(CP_H, CP_H, CP_H, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(CP_W1, CP_W, CP_W1, CP_W2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(CP_W2, CP_W, CP_W2, CP_W3, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(CP_W3, CP_W, CP_W3, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL_C2(CPC1, CPC, CPC1, CPC2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL1(CPC2, CPC, CPC2, INTREG, AVR32_V1), + SYNTAX_NORMAL1(CSRF, CSRF, CSRF, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL1(CSRFCZ, CSRFCZ, CSRFCZ, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL3(DIVS, DIVS, DIVS, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(DIVU, DIVU, DIVU, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(EOR1, EOR, EOR1, EOR2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(EOR2, EOR, EOR2, EOR3, INTREG, INTREG, INTREG_LSL, AVR32_V1), + SYNTAX_NORMAL3(EOR3, EOR, EOR3, INTREG, INTREG, INTREG_LSR, AVR32_V1), + SYNTAX_NORMAL2(EORL, EORL, EORL, INTREG, UNSIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(EORH, EORH, EORH, INTREG, UNSIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL0(FRS, FRS, FRS, AVR32_V1), + SYNTAX_NORMAL1(ICALL, ICALL, ICALL, INTREG, AVR32_V1), + SYNTAX_NORMAL1(INCJOSP, INCJOSP, INCJOSP, JOSPINC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_D1, LD_D, LD_D1, LD_D2, DWREG, INTREG_POSTINC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_D2, LD_D, LD_D2, LD_D3, DWREG, INTREG_PREDEC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_D3, LD_D, LD_D3, LD_D5, DWREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(LD_D5, LD_D, LD_D5, LD_D4, DWREG, INTREG_INDEX, AVR32_V1), + SYNTAX_NORMAL2(LD_D4, LD_D, LD_D4, DWREG, INTREG_SDISP, AVR32_V1), + SYNTAX_NORMAL_C2(LD_SB2, LD_SB, LD_SB2, LD_SB1, INTREG, INTREG_INDEX, AVR32_V1), + SYNTAX_NORMAL2(LD_SB1, LD_SB, LD_SB1, INTREG, INTREG_SDISP, AVR32_V1), + SYNTAX_NORMAL_C2(LD_UB1, LD_UB, LD_UB1, LD_UB2, INTREG, INTREG_POSTINC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_UB2, LD_UB, LD_UB2, LD_UB5, INTREG, INTREG_PREDEC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_UB5, LD_UB, LD_UB5, LD_UB3, INTREG, INTREG_INDEX, AVR32_V1), + SYNTAX_NORMAL_C2(LD_UB3, LD_UB, LD_UB3, LD_UB4, INTREG, INTREG_UDISP, AVR32_V1), + SYNTAX_NORMAL2(LD_UB4, LD_UB, LD_UB4, INTREG, INTREG_SDISP, AVR32_V1), + SYNTAX_NORMAL_C2(LD_SH1, LD_SH, LD_SH1, LD_SH2, INTREG, INTREG_POSTINC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_SH2, LD_SH, LD_SH2, LD_SH5, INTREG, INTREG_PREDEC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_SH5, LD_SH, LD_SH5, LD_SH3, INTREG, INTREG_INDEX, AVR32_V1), + SYNTAX_NORMAL_C2(LD_SH3, LD_SH, LD_SH3, LD_SH4, INTREG, INTREG_UDISP_H, AVR32_V1), + SYNTAX_NORMAL2(LD_SH4, LD_SH, LD_SH4, INTREG, INTREG_SDISP, AVR32_V1), + SYNTAX_NORMAL_C2(LD_UH1, LD_UH, LD_UH1, LD_UH2, INTREG, INTREG_POSTINC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_UH2, LD_UH, LD_UH2, LD_UH5, INTREG, INTREG_PREDEC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_UH5, LD_UH, LD_UH5, LD_UH3, INTREG, INTREG_INDEX, AVR32_V1), + SYNTAX_NORMAL_C2(LD_UH3, LD_UH, LD_UH3, LD_UH4, INTREG, INTREG_UDISP_H, AVR32_V1), + SYNTAX_NORMAL2(LD_UH4, LD_UH, LD_UH4, INTREG, INTREG_SDISP, AVR32_V1), + SYNTAX_NORMAL_C2(LD_W1, LD_W, LD_W1, LD_W2, INTREG, INTREG_POSTINC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_W2, LD_W, LD_W2, LD_W5, INTREG, INTREG_PREDEC, AVR32_V1), + SYNTAX_NORMAL_C2(LD_W5, LD_W, LD_W5, LD_W6, INTREG, INTREG_INDEX, AVR32_V1), + SYNTAX_NORMAL_C2(LD_W6, LD_W, LD_W6, LD_W3, INTREG, INTREG_XINDEX, AVR32_V1), + SYNTAX_NORMAL_C2(LD_W3, LD_W, LD_W3, LD_W4, INTREG, INTREG_UDISP_W, AVR32_V1), + SYNTAX_NORMAL2(LD_W4, LD_W, LD_W4, INTREG, INTREG_SDISP, AVR32_V1), + SYNTAX_NORMAL3(LDC_D1, LDC_D, LDC_D1, CPNO, CPREG_D, INTREG_UDISP_W, AVR32_V1), + SYNTAX_NORMAL_C3(LDC_D2, LDC_D, LDC_D2, LDC_D1, CPNO, CPREG_D, INTREG_PREDEC, AVR32_V1), + SYNTAX_NORMAL_C3(LDC_D3, LDC_D, LDC_D3, LDC_D2, CPNO, CPREG_D, INTREG_INDEX, AVR32_V1), + SYNTAX_NORMAL3(LDC_W1, LDC_W, LDC_W1, CPNO, CPREG, INTREG_UDISP_W, AVR32_V1), + SYNTAX_NORMAL_C3(LDC_W2, LDC_W, LDC_W2, LDC_W1, CPNO, CPREG, INTREG_PREDEC, AVR32_V1), + SYNTAX_NORMAL_C3(LDC_W3, LDC_W, LDC_W3, LDC_W2, CPNO, CPREG, INTREG_INDEX, AVR32_V1), + SYNTAX_NORMAL2(LDC0_D, LDC0_D, LDC0_D, CPREG_D, INTREG_UDISP_W, AVR32_V1), + SYNTAX_NORMAL2(LDC0_W, LDC0_W, LDC0_W, CPREG, INTREG_UDISP_W, AVR32_V1), + SYNTAX_NORMAL_CM3(LDCM_D, LDCM_D, LDCM_D, LDCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1), + SYNTAX_NORMALM3(LDCM_D_PU, LDCM_D, LDCM_D_PU, CPNO, INTREG_POSTINC, REGLIST_CPD8, AVR32_V1), + SYNTAX_NORMAL_CM3(LDCM_W, LDCM_W, LDCM_W, LDCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1), + SYNTAX_NORMALM3(LDCM_W_PU, LDCM_W, LDCM_W_PU, CPNO, INTREG_POSTINC, REGLIST_CP8, AVR32_V1), + SYNTAX_NORMAL2(LDDPC, LDDPC, LDDPC, INTREG, PC_UDISP_W, AVR32_V1), + SYNTAX_NORMAL2(LDDPC_EXT, LDDPC, LDDPC_EXT, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(LDDSP, LDDSP, LDDSP, INTREG, SP_UDISP_W, AVR32_V1), + SYNTAX_NORMAL2(LDINS_B, LDINS_B, LDINS_B, INTREG_BSEL, INTREG_SDISP, AVR32_V1), + SYNTAX_NORMAL2(LDINS_H, LDINS_H, LDINS_H, INTREG_HSEL, INTREG_SDISP_H, AVR32_V1), + SYNTAX_NORMALM1(LDM, LDM, LDM, REGLIST_LDM, AVR32_V1), + SYNTAX_NORMAL_CM2(LDMTS, LDMTS, LDMTS, LDMTS_PU, INTREG, REGLIST16, AVR32_V1), + SYNTAX_NORMALM2(LDMTS_PU, LDMTS, LDMTS_PU, INTREG_POSTINC, REGLIST16, AVR32_V1), + SYNTAX_NORMAL2(LDSWP_SH, LDSWP_SH, LDSWP_SH, INTREG, INTREG_SDISP_H, AVR32_V1), + SYNTAX_NORMAL2(LDSWP_UH, LDSWP_UH, LDSWP_UH, INTREG, INTREG_SDISP_H, AVR32_V1), + SYNTAX_NORMAL2(LDSWP_W, LDSWP_W, LDSWP_W, INTREG, INTREG_SDISP_W, AVR32_V1), + SYNTAX_NORMAL_C3(LSL1, LSL, LSL1, LSL3, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(LSL3, LSL, LSL3, LSL2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL2(LSL2, LSL, LSL2, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL_C3(LSR1, LSR, LSR1, LSR3, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(LSR3, LSR, LSR3, LSR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL2(LSR2, LSR, LSR2, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL3(MAC, MAC, MAC, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(MACHH_D, MACHH_D, MACHH_D, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MACHH_W, MACHH_W, MACHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MACS_D, MACS_D, MACS_D, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(MACSATHH_W, MACSATHH_W, MACSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MACUD, MACU_D, MACUD, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(MACWH_D, MACWH_D, MACWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MAX, MAX, MAX, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL1(MCALL, MCALL, MCALL, MCALL, AVR32_V1), + SYNTAX_NORMAL2(MFDR, MFDR, MFDR, INTREG, UNSIGNED_CONST_W, AVR32_V1), + SYNTAX_NORMAL2(MFSR, MFSR, MFSR, INTREG, UNSIGNED_CONST_W, AVR32_V1), + SYNTAX_NORMAL3(MIN, MIN, MIN, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOV3, MOV, MOV3, MOV1, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOV1, MOV, MOV1, MOV2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOV2, MOV, MOV2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL_C2(MOVEQ1, MOVEQ, MOVEQ1, MOVEQ2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVNE1, MOVNE, MOVNE1, MOVNE2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVCC1, MOVCC, MOVCC1, MOVCC2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVCS1, MOVCS, MOVCS1, MOVCS2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVGE1, MOVGE, MOVGE1, MOVGE2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVLT1, MOVLT, MOVLT1, MOVLT2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVMI1, MOVMI, MOVMI1, MOVMI2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVPL1, MOVPL, MOVPL1, MOVPL2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVLS1, MOVLS, MOVLS1, MOVLS2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVGT1, MOVGT, MOVGT1, MOVGT2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVLE1, MOVLE, MOVLE1, MOVLE2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVHI1, MOVHI, MOVHI1, MOVHI2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVVS1, MOVVS, MOVVS1, MOVVS2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVVC1, MOVVC, MOVVC1, MOVVC2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVQS1, MOVQS, MOVQS1, MOVQS2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVAL1, MOVAL, MOVAL1, MOVAL2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVHS1, MOVHS, MOVCC1, MOVHS2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MOVLO1, MOVLO, MOVCS1, MOVLO2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL2(MOVEQ2, MOVEQ, MOVEQ2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVNE2, MOVNE, MOVNE2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVCC2, MOVCC, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVCS2, MOVCS, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVGE2, MOVGE, MOVGE2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVLT2, MOVLT, MOVLT2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVMI2, MOVMI, MOVMI2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVPL2, MOVPL, MOVPL2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVLS2, MOVLS, MOVLS2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVGT2, MOVGT, MOVGT2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVLE2, MOVLE, MOVLE2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVHI2, MOVHI, MOVHI2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVVS2, MOVVS, MOVVS2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVVC2, MOVVC, MOVVC2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVQS2, MOVQS, MOVQS2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVAL2, MOVAL, MOVAL2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVHS2, MOVHS, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MOVLO2, MOVLO, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(MTDR, MTDR, MTDR, UNSIGNED_CONST_W, INTREG, AVR32_V1), + SYNTAX_NORMAL2(MTSR, MTSR, MTSR, UNSIGNED_CONST_W, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(MUL1, MUL, MUL1, MUL2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(MUL2, MUL, MUL2, MUL3, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(MUL3, MUL, MUL3, INTREG, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL3(MULHH_W, MULHH_W, MULHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MULNHH_W, MULNHH_W, MULNHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MULNWH_D, MULNWH_D, MULNWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MULSD, MULS_D, MULSD, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(MULSATHH_H, MULSATHH_H, MULSATHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MULSATHH_W, MULSATHH_W, MULSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MULSATRNDHH_H, MULSATRNDHH_H, MULSATRNDHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MULSATRNDWH_W, MULSATRNDWH_W, MULSATRNDWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MULSATWH_W, MULSATWH_W, MULSATWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL3(MULU_D, MULU_D, MULU_D, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(MULWH_D, MULWH_D, MULWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL1(MUSFR, MUSFR, MUSFR, INTREG, AVR32_V1), + SYNTAX_NORMAL1(MUSTR, MUSTR, MUSTR, INTREG, AVR32_V1), + SYNTAX_NORMAL3(MVCR_D, MVCR_D, MVCR_D, CPNO, DWREG, CPREG_D, AVR32_V1), + SYNTAX_NORMAL3(MVCR_W, MVCR_W, MVCR_W, CPNO, INTREG, CPREG, AVR32_V1), + SYNTAX_NORMAL3(MVRC_D, MVRC_D, MVRC_D, CPNO, CPREG_D, DWREG, AVR32_V1), + SYNTAX_NORMAL3(MVRC_W, MVRC_W, MVRC_W, CPNO, CPREG, INTREG, AVR32_V1), + SYNTAX_NORMAL1(NEG, NEG, NEG, INTREG, AVR32_V1), + SYNTAX_NORMAL0(NOP, NOP, NOP, AVR32_V1), + SYNTAX_NORMAL_C2(OR1, OR, OR1, OR2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(OR2, OR, OR2, OR3, INTREG, INTREG, INTREG_LSL, AVR32_V1), + SYNTAX_NORMAL3(OR3, OR, OR3, INTREG, INTREG, INTREG_LSR, AVR32_V1), + SYNTAX_NORMAL2(ORH, ORH, ORH, INTREG, UNSIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(ORL, ORL, ORL, INTREG, UNSIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(PABS_SB, PABS_SB, PABS_SB, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL2(PABS_SH, PABS_SH, PABS_SH, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PACKSH_SB, PACKSH_SB, PACKSH_SB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PACKSH_UB, PACKSH_UB, PACKSH_UB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PACKW_SH, PACKW_SH, PACKW_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADD_B, PADD_B, PADD_B, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADD_H, PADD_H, PADD_H, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDH_SH, PADDH_SH, PADDH_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDH_UB, PADDH_UB, PADDH_UB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDS_SB, PADDS_SB, PADDS_SB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDS_SH, PADDS_SH, PADDS_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDS_UB, PADDS_UB, PADDS_UB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDS_UH, PADDS_UH, PADDS_UH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDSUB_H, PADDSUB_H, PADDSUB_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL3(PADDSUBH_SH, PADDSUBH_SH, PADDSUBH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL3(PADDSUBS_SH, PADDSUBS_SH, PADDSUBS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL3(PADDSUBS_UH, PADDSUBS_UH, PADDSUBS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL3(PADDX_H, PADDX_H, PADDX_H, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDXH_SH, PADDXH_SH, PADDXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDXS_SH, PADDXS_SH, PADDXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PADDXS_UH, PADDXS_UH, PADDXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PASR_B, PASR_B, PASR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD), + SYNTAX_NORMAL3(PASR_H, PASR_H, PASR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD), + SYNTAX_NORMAL3(PAVG_SH, PAVG_SH, PAVG_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PAVG_UB, PAVG_UB, PAVG_UB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PLSL_B, PLSL_B, PLSL_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD), + SYNTAX_NORMAL3(PLSL_H, PLSL_H, PLSL_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD), + SYNTAX_NORMAL3(PLSR_B, PLSR_B, PLSR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD), + SYNTAX_NORMAL3(PLSR_H, PLSR_H, PLSR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD), + SYNTAX_NORMAL3(PMAX_SH, PMAX_SH, PMAX_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PMAX_UB, PMAX_UB, PMAX_UB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PMIN_SH, PMIN_SH, PMIN_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PMIN_UB, PMIN_UB, PMIN_UB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL0(POPJC, POPJC, POPJC, AVR32_V1), + SYNTAX_NORMAL_CM1(POPM, POPM, POPM, POPM_E, REGLIST9, AVR32_V1), + SYNTAX_NORMALM1(POPM_E, POPM, POPM_E, REGLIST16, AVR32_V1), + SYNTAX_NORMAL1(PREF, PREF, PREF, INTREG_SDISP, AVR32_V1), + SYNTAX_NORMAL3(PSAD, PSAD, PSAD, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUB_B, PSUB_B, PSUB_B, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUB_H, PSUB_H, PSUB_H, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBADD_H, PSUBADD_H, PSUBADD_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBADDH_SH, PSUBADDH_SH, PSUBADDH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBADDS_SH, PSUBADDS_SH, PSUBADDS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBADDS_UH, PSUBADDS_UH, PSUBADDS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBH_SH, PSUBH_SH, PSUBH_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBH_UB, PSUBH_UB, PSUBH_UB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBS_SB, PSUBS_SB, PSUBS_SB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBS_SH, PSUBS_SH, PSUBS_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBS_UB, PSUBS_UB, PSUBS_UB, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBS_UH, PSUBS_UH, PSUBS_UH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBX_H, PSUBX_H, PSUBX_H, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBXH_SH, PSUBXH_SH, PSUBXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBXS_SH, PSUBXS_SH, PSUBXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL3(PSUBXS_UH, PSUBXS_UH, PSUBXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD), + SYNTAX_NORMAL2(PUNPCKSB_H, PUNPCKSB_H, PUNPCKSB_H, INTREG, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL2(PUNPCKUB_H, PUNPCKUB_H, PUNPCKUB_H, INTREG, INTREG_HSEL, AVR32_SIMD), + SYNTAX_NORMAL0(PUSHJC, PUSHJC, PUSHJC, AVR32_V1), + SYNTAX_NORMAL_CM1(PUSHM, PUSHM, PUSHM, PUSHM_E, REGLIST8, AVR32_V1), + SYNTAX_NORMALM1(PUSHM_E, PUSHM, PUSHM_E, REGLIST16, AVR32_V1), + SYNTAX_NORMAL_C1(RCALL1, RCALL, RCALL1, RCALL2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(RCALL2, RCALL, RCALL2, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(RETEQ, RETEQ, RETEQ, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETNE, RETNE, RETNE, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETCC, RETCC, RETCC, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETCS, RETCS, RETCS, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETGE, RETGE, RETGE, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETLT, RETLT, RETLT, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETMI, RETMI, RETMI, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETPL, RETPL, RETPL, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETLS, RETLS, RETLS, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETGT, RETGT, RETGT, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETLE, RETLE, RETLE, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETHI, RETHI, RETHI, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETVS, RETVS, RETVS, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETVC, RETVC, RETVC, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETQS, RETQS, RETQS, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETAL, RETAL, RETAL, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETHS, RETHS, RETCC, RETVAL, AVR32_V1), + SYNTAX_NORMAL1(RETLO, RETLO, RETCS, RETVAL, AVR32_V1), + SYNTAX_NORMAL0(RETD, RETD, RETD, AVR32_V1), + SYNTAX_NORMAL0(RETE, RETE, RETE, AVR32_V1), + SYNTAX_NORMAL0(RETJ, RETJ, RETJ, AVR32_V1), + SYNTAX_NORMAL0(RETS, RETS, RETS, AVR32_V1), + SYNTAX_NORMAL1(RJMP, RJMP, RJMP, JMPLABEL, AVR32_V1), + SYNTAX_NORMAL1(ROL, ROL, ROL, INTREG, AVR32_V1), + SYNTAX_NORMAL1(ROR, ROR, ROR, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(RSUB1, RSUB, RSUB1, RSUB2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(RSUB2, RSUB, RSUB2, INTREG, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL3(SATADD_H, SATADD_H, SATADD_H, INTREG, INTREG, INTREG, AVR32_DSP), + SYNTAX_NORMAL3(SATADD_W, SATADD_W, SATADD_W, INTREG, INTREG, INTREG, AVR32_DSP), + SYNTAX_NORMAL2(SATRNDS, SATRNDS, SATRNDS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP), + SYNTAX_NORMAL2(SATRNDU, SATRNDU, SATRNDU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP), + SYNTAX_NORMAL2(SATS, SATS, SATS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP), + SYNTAX_NORMAL3(SATSUB_H, SATSUB_H, SATSUB_H, INTREG, INTREG, INTREG, AVR32_DSP), + SYNTAX_NORMAL_C3(SATSUB_W1, SATSUB_W, SATSUB_W1, SATSUB_W2, INTREG, INTREG, INTREG, AVR32_DSP), + SYNTAX_NORMAL3(SATSUB_W2, SATSUB_W, SATSUB_W2, INTREG, INTREG, SIGNED_CONST, AVR32_DSP), + SYNTAX_NORMAL2(SATU, SATU, SATU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL3(SBC, SBC, SBC, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL2(SBR, SBR, SBR, INTREG, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL0(SCALL, SCALL, SCALL, AVR32_V1), + SYNTAX_NORMAL1(SCR, SCR, SCR, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SLEEP, SLEEP, SLEEP, UNSIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL1(SREQ, SREQ, SREQ, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRNE, SRNE, SRNE, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRCC, SRCC, SRCC, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRCS, SRCS, SRCS, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRGE, SRGE, SRGE, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRLT, SRLT, SRLT, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRMI, SRMI, SRMI, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRPL, SRPL, SRPL, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRLS, SRLS, SRLS, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRGT, SRGT, SRGT, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRLE, SRLE, SRLE, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRHI, SRHI, SRHI, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRVS, SRVS, SRVS, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRVC, SRVC, SRVC, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRQS, SRQS, SRQS, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRAL, SRAL, SRAL, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRHS, SRHS, SRCC, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SRLO, SRLO, SRCS, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SSRF, SSRF, SSRF, UNSIGNED_NUMBER, AVR32_V1), + SYNTAX_NORMAL_C2(ST_B1, ST_B, ST_B1, ST_B2, INTREG_POSTINC, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_B2, ST_B, ST_B2, ST_B5, INTREG_PREDEC, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_B5, ST_B, ST_B5, ST_B3, INTREG_INDEX, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_B3, ST_B, ST_B3, ST_B4, INTREG_UDISP, INTREG, AVR32_V1), + SYNTAX_NORMAL2(ST_B4, ST_B, ST_B4, INTREG_SDISP, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_D1, ST_D, ST_D1, ST_D2, INTREG_POSTINC, DWREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_D2, ST_D, ST_D2, ST_D3, INTREG_PREDEC, DWREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_D3, ST_D, ST_D3, ST_D5, INTREG, DWREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_D5, ST_D, ST_D5, ST_D4, INTREG_INDEX, DWREG, AVR32_V1), + SYNTAX_NORMAL2(ST_D4, ST_D, ST_D4, INTREG_SDISP, DWREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_H1, ST_H, ST_H1, ST_H2, INTREG_POSTINC, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_H2, ST_H, ST_H2, ST_H5, INTREG_PREDEC, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_H5, ST_H, ST_H5, ST_H3, INTREG_INDEX, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_H3, ST_H, ST_H3, ST_H4, INTREG_UDISP_H, INTREG, AVR32_V1), + SYNTAX_NORMAL2(ST_H4, ST_H, ST_H4, INTREG_SDISP, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_W1, ST_W, ST_W1, ST_W2, INTREG_POSTINC, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_W2, ST_W, ST_W2, ST_W5, INTREG_PREDEC, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_W5, ST_W, ST_W5, ST_W3, INTREG_INDEX, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(ST_W3, ST_W, ST_W3, ST_W4, INTREG_UDISP_W, INTREG, AVR32_V1), + SYNTAX_NORMAL2(ST_W4, ST_W, ST_W4, INTREG_SDISP, INTREG, AVR32_V1), + SYNTAX_NORMAL3(STC_D1, STC_D, STC_D1, CPNO, INTREG_UDISP_W, CPREG_D, AVR32_V1), + SYNTAX_NORMAL_C3(STC_D2, STC_D, STC_D2, STC_D1, CPNO, INTREG_POSTINC, CPREG_D, AVR32_V1), + SYNTAX_NORMAL_C3(STC_D3, STC_D, STC_D3, STC_D2, CPNO, INTREG_INDEX, CPREG_D, AVR32_V1), + SYNTAX_NORMAL3(STC_W1, STC_W, STC_W1, CPNO, INTREG_UDISP_W, CPREG, AVR32_V1), + SYNTAX_NORMAL_C3(STC_W2, STC_W, STC_W2, STC_W1, CPNO, INTREG_POSTINC, CPREG, AVR32_V1), + SYNTAX_NORMAL_C3(STC_W3, STC_W, STC_W3, STC_W2, CPNO, INTREG_INDEX, CPREG, AVR32_V1), + SYNTAX_NORMAL2(STC0_D, STC0_D, STC0_D, INTREG_UDISP_W, CPREG_D, AVR32_V1), + SYNTAX_NORMAL2(STC0_W, STC0_W, STC0_W, INTREG_UDISP_W, CPREG, AVR32_V1), + SYNTAX_NORMAL_CM3(STCM_D, STCM_D, STCM_D, STCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1), + SYNTAX_NORMALM3(STCM_D_PU, STCM_D, STCM_D_PU, CPNO, INTREG_PREDEC, REGLIST_CPD8, AVR32_V1), + SYNTAX_NORMAL_CM3(STCM_W, STCM_W, STCM_W, STCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1), + SYNTAX_NORMALM3(STCM_W_PU, STCM_W, STCM_W_PU, CPNO, INTREG_PREDEC, REGLIST_CP8, AVR32_V1), + SYNTAX_NORMAL2(STCOND, STCOND, STCOND, INTREG_SDISP, INTREG, AVR32_V1), + SYNTAX_NORMAL2(STDSP, STDSP, STDSP, SP_UDISP_W, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(STHH_W2, STHH_W, STHH_W2, STHH_W1, INTREG_INDEX, INTREG_HSEL, INTREG_HSEL, AVR32_V1), + SYNTAX_NORMAL3(STHH_W1, STHH_W, STHH_W1, INTREG_UDISP_W, INTREG_HSEL, INTREG_HSEL, AVR32_V1), + SYNTAX_NORMAL_CM2(STM, STM, STM, STM_PU, INTREG, REGLIST16, AVR32_V1), + SYNTAX_NORMALM2(STM_PU, STM, STM_PU, INTREG_PREDEC, REGLIST16, AVR32_V1), + SYNTAX_NORMAL_CM2(STMTS, STMTS, STMTS, STMTS_PU, INTREG, REGLIST16, AVR32_V1), + SYNTAX_NORMALM2(STMTS_PU, STMTS, STMTS_PU, INTREG_PREDEC, REGLIST16, AVR32_V1), + SYNTAX_NORMAL2(STSWP_H, STSWP_H, STSWP_H, INTREG_SDISP_H, INTREG, AVR32_V1), + SYNTAX_NORMAL2(STSWP_W, STSWP_W, STSWP_W, INTREG_SDISP_W, INTREG, AVR32_V1), + SYNTAX_NORMAL_C2(SUB1, SUB, SUB1, SUB2, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL_C3(SUB2, SUB, SUB2, SUB5, INTREG, INTREG, INTREG_LSL, AVR32_V1), + SYNTAX_NORMAL_C3(SUB5, SUB, SUB5, SUB3_SP, INTREG, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL_C2(SUB3_SP, SUB, SUB3_SP, SUB3, SP, SIGNED_CONST_W, AVR32_V1), + SYNTAX_NORMAL_C2(SUB3, SUB, SUB3, SUB4, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUB4, SUB, SUB4, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBEQ, SUBEQ, SUBEQ, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBNE, SUBNE, SUBNE, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBCC, SUBCC, SUBCC, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBCS, SUBCS, SUBCS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBGE, SUBGE, SUBGE, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBLT, SUBLT, SUBLT, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBMI, SUBMI, SUBMI, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBPL, SUBPL, SUBPL, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBLS, SUBLS, SUBLS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBGT, SUBGT, SUBGT, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBLE, SUBLE, SUBLE, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBHI, SUBHI, SUBHI, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBVS, SUBVS, SUBVS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBVC, SUBVC, SUBVC, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBQS, SUBQS, SUBQS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBAL, SUBAL, SUBAL, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBHS, SUBHS, SUBCC, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBLO, SUBLO, SUBCS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFEQ, SUBFEQ, SUBFEQ, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFNE, SUBFNE, SUBFNE, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFCC, SUBFCC, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFCS, SUBFCS, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFGE, SUBFGE, SUBFGE, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFLT, SUBFLT, SUBFLT, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFMI, SUBFMI, SUBFMI, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFPL, SUBFPL, SUBFPL, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFLS, SUBFLS, SUBFLS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFGT, SUBFGT, SUBFGT, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFLE, SUBFLE, SUBFLE, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFHI, SUBFHI, SUBFHI, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFVS, SUBFVS, SUBFVS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFVC, SUBFVC, SUBFVC, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFQS, SUBFQS, SUBFQS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFAL, SUBFAL, SUBFAL, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFHS, SUBFHS, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL2(SUBFLO, SUBFLO, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL3(SUBHH_W, SUBHH_W, SUBHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP), + SYNTAX_NORMAL1(SWAP_B, SWAP_B, SWAP_B, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SWAP_BH, SWAP_BH, SWAP_BH, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SWAP_H, SWAP_H, SWAP_H, INTREG, AVR32_V1), + SYNTAX_NORMAL1(SYNC, SYNC, SYNC, UNSIGNED_CONST, AVR32_V1), + SYNTAX_NORMAL0(TLBR, TLBR, TLBR, AVR32_V1), + SYNTAX_NORMAL0(TLBS, TLBS, TLBS, AVR32_V1), + SYNTAX_NORMAL0(TLBW, TLBW, TLBW, AVR32_V1), + SYNTAX_NORMAL1(TNBZ, TNBZ, TNBZ, INTREG, AVR32_V1), + SYNTAX_NORMAL2(TST, TST, TST, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL3(XCHG, XCHG, XCHG, INTREG, INTREG, INTREG, AVR32_V1), + SYNTAX_NORMAL2(MEMC, MEMC, MEMC, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW), + SYNTAX_NORMAL2(MEMS, MEMS, MEMS, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW), + SYNTAX_NORMAL2(MEMT, MEMT, MEMT, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW), + SYNTAX_FP(FADD, 3), + SYNTAX_FP(FSUB, 3), + SYNTAX_FP(FMAC, 3), + SYNTAX_FP(FNMAC, 3), + SYNTAX_FP(FMSC, 3), + SYNTAX_FP(FNMSC, 3), + SYNTAX_FP(FMUL, 3), + SYNTAX_FP(FNMUL, 3), + SYNTAX_FP(FNEG, 2), + SYNTAX_FP(FABS, 2), + SYNTAX_FP(FCMP, 2), + { + AVR32_SYNTAX_FMOV1_S, + AVR32_FP, NULL, AVR32_PARSER_ALIAS, + { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV1_S] }, + &avr32_syntax_table[AVR32_SYNTAX_FMOV2_S], + 2, + { + AVR32_OPERAND_FPREG_S, + AVR32_OPERAND_FPREG_S, + }, + }, + { + AVR32_SYNTAX_FMOV1_D, + AVR32_FP, NULL, AVR32_PARSER_ALIAS, + { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV1_D] }, + &avr32_syntax_table[AVR32_SYNTAX_FMOV2_D], + 2, + { + AVR32_OPERAND_FPREG_D, + AVR32_OPERAND_FPREG_D, + }, + }, + { + AVR32_SYNTAX_FMOV2_S, + AVR32_FP, NULL, AVR32_PARSER_ALIAS, + { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV2_S] }, + &avr32_syntax_table[AVR32_SYNTAX_FMOV3_S], + 2, + { + AVR32_OPERAND_INTREG, + AVR32_OPERAND_FPREG_S, + }, + }, + { + AVR32_SYNTAX_FMOV2_D, + AVR32_FP, NULL, AVR32_PARSER_ALIAS, + { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV2_D] }, + &avr32_syntax_table[AVR32_SYNTAX_FMOV3_D], + 2, + { + AVR32_OPERAND_DWREG, + AVR32_OPERAND_FPREG_D, + }, + }, + { + AVR32_SYNTAX_FMOV3_S, + AVR32_FP, NULL, AVR32_PARSER_ALIAS, + { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV3_S] }, NULL, + 2, + { + AVR32_OPERAND_FPREG_S, + AVR32_OPERAND_INTREG, + }, + }, + { + AVR32_SYNTAX_FMOV3_D, + AVR32_FP, NULL, AVR32_PARSER_ALIAS, + { .alias = &avr32_alias_table[AVR32_ALIAS_FMOV3_D] }, NULL, + 2, + { + AVR32_OPERAND_FPREG_D, + AVR32_OPERAND_DWREG, + }, + }, + { + AVR32_SYNTAX_FCASTS_D, + AVR32_FP, NULL, AVR32_PARSER_ALIAS, + { .alias = &avr32_alias_table[AVR32_ALIAS_FCASTS_D] }, NULL, + 2, + { + AVR32_OPERAND_FPREG_S, + AVR32_OPERAND_FPREG_D, + }, + }, + { + AVR32_SYNTAX_FCASTD_S, + AVR32_FP, NULL, AVR32_PARSER_ALIAS, + { .alias = &avr32_alias_table[AVR32_ALIAS_FCASTD_S] }, NULL, + 2, + { + AVR32_OPERAND_FPREG_D, + AVR32_OPERAND_FPREG_S, + }, + }, + { + AVR32_SYNTAX_LDA_W, + AVR32_V1, NULL, AVR32_PARSER_LDA, + { NULL }, NULL, + 2, + { + AVR32_OPERAND_INTREG, + AVR32_OPERAND_SIGNED_CONST, + }, + }, + { + AVR32_SYNTAX_CALL, + AVR32_V1, NULL, AVR32_PARSER_CALL, + { NULL }, NULL, + 1, + { + AVR32_OPERAND_JMPLABEL, + }, + }, + }; + +#define NORMAL_MNEMONIC(name, syntax, str) \ + { \ + AVR32_MNEMONIC_##name, str, \ + &avr32_syntax_table[AVR32_SYNTAX_##syntax], \ + } +#define FP_MNEMONIC(name, syntax, str) \ + NORMAL_MNEMONIC(name##_S, syntax##_S, str ".s"), \ + NORMAL_MNEMONIC(name##_D, syntax##_D, str ".d") + +const struct avr32_mnemonic avr32_mnemonic_table[] = + { + NORMAL_MNEMONIC(ABS, ABS, "abs"), + NORMAL_MNEMONIC(ACALL, ACALL, "acall"), + NORMAL_MNEMONIC(ACR, ACR, "acr"), + NORMAL_MNEMONIC(ADC, ADC, "adc"), + NORMAL_MNEMONIC(ADD, ADD1, "add"), + NORMAL_MNEMONIC(ADDABS, ADDABS, "addabs"), + NORMAL_MNEMONIC(ADDHH_W, ADDHH_W, "addhh.w"), + NORMAL_MNEMONIC(AND, AND1, "and"), + NORMAL_MNEMONIC(ANDH, ANDH, "andh"), + NORMAL_MNEMONIC(ANDL, ANDL, "andl"), + NORMAL_MNEMONIC(ANDN, ANDN, "andn"), + NORMAL_MNEMONIC(ASR, ASR1, "asr"), + NORMAL_MNEMONIC(BFEXTS, BFEXTS, "bfexts"), + NORMAL_MNEMONIC(BFEXTU, BFEXTU, "bfextu"), + NORMAL_MNEMONIC(BFINS, BFINS, "bfins"), + NORMAL_MNEMONIC(BLD, BLD, "bld"), + NORMAL_MNEMONIC(BREQ, BREQ1, "breq"), + NORMAL_MNEMONIC(BRNE, BRNE1, "brne"), + NORMAL_MNEMONIC(BRCC, BRCC1, "brcc"), + NORMAL_MNEMONIC(BRCS, BRCS1, "brcs"), + NORMAL_MNEMONIC(BRGE, BRGE1, "brge"), + NORMAL_MNEMONIC(BRLT, BRLT1, "brlt"), + NORMAL_MNEMONIC(BRMI, BRMI1, "brmi"), + NORMAL_MNEMONIC(BRPL, BRPL1, "brpl"), + NORMAL_MNEMONIC(BRHS, BRHS1, "brhs"), + NORMAL_MNEMONIC(BRLO, BRLO1, "brlo"), + NORMAL_MNEMONIC(BRLS, BRLS, "brls"), + NORMAL_MNEMONIC(BRGT, BRGT, "brgt"), + NORMAL_MNEMONIC(BRLE, BRLE, "brle"), + NORMAL_MNEMONIC(BRHI, BRHI, "brhi"), + NORMAL_MNEMONIC(BRVS, BRVS, "brvs"), + NORMAL_MNEMONIC(BRVC, BRVC, "brvc"), + NORMAL_MNEMONIC(BRQS, BRQS, "brqs"), + NORMAL_MNEMONIC(BRAL, BRAL, "bral"), + NORMAL_MNEMONIC(BREAKPOINT, BREAKPOINT, "breakpoint"), + NORMAL_MNEMONIC(BREV, BREV, "brev"), + NORMAL_MNEMONIC(BST, BST, "bst"), + NORMAL_MNEMONIC(CACHE, CACHE, "cache"), + NORMAL_MNEMONIC(CASTS_B, CASTS_B, "casts.b"), + NORMAL_MNEMONIC(CASTS_H, CASTS_H, "casts.h"), + NORMAL_MNEMONIC(CASTU_B, CASTU_B, "castu.b"), + NORMAL_MNEMONIC(CASTU_H, CASTU_H, "castu.h"), + NORMAL_MNEMONIC(CBR, CBR, "cbr"), + NORMAL_MNEMONIC(CLZ, CLZ, "clz"), + NORMAL_MNEMONIC(COM, COM, "com"), + NORMAL_MNEMONIC(COP, COP, "cop"), + NORMAL_MNEMONIC(CP_B, CP_B, "cp.b"), + NORMAL_MNEMONIC(CP_H, CP_H, "cp.h"), + NORMAL_MNEMONIC(CP_W, CP_W1, "cp.w"), + NORMAL_MNEMONIC(CP, CP_W1, "cp"), + NORMAL_MNEMONIC(CPC, CPC1, "cpc"), + NORMAL_MNEMONIC(CSRF, CSRF, "csrf"), + NORMAL_MNEMONIC(CSRFCZ, CSRFCZ, "csrfcz"), + NORMAL_MNEMONIC(DIVS, DIVS, "divs"), + NORMAL_MNEMONIC(DIVU, DIVU, "divu"), + NORMAL_MNEMONIC(EOR, EOR1, "eor"), + NORMAL_MNEMONIC(EORL, EORL, "eorl"), + NORMAL_MNEMONIC(EORH, EORH, "eorh"), + NORMAL_MNEMONIC(FRS, FRS, "frs"), + NORMAL_MNEMONIC(ICALL, ICALL, "icall"), + NORMAL_MNEMONIC(INCJOSP, INCJOSP, "incjosp"), + NORMAL_MNEMONIC(LD_D, LD_D1, "ld.d"), + NORMAL_MNEMONIC(LD_SB, LD_SB2, "ld.sb"), + NORMAL_MNEMONIC(LD_UB, LD_UB1, "ld.ub"), + NORMAL_MNEMONIC(LD_SH, LD_SH1, "ld.sh"), + NORMAL_MNEMONIC(LD_UH, LD_UH1, "ld.uh"), + NORMAL_MNEMONIC(LD_W, LD_W1, "ld.w"), + NORMAL_MNEMONIC(LDC_D, LDC_D3, "ldc.d"), + NORMAL_MNEMONIC(LDC_W, LDC_W3, "ldc.w"), + NORMAL_MNEMONIC(LDC0_D, LDC0_D, "ldc0.d"), + NORMAL_MNEMONIC(LDC0_W, LDC0_W, "ldc0.w"), + NORMAL_MNEMONIC(LDCM_D, LDCM_D, "ldcm.d"), + NORMAL_MNEMONIC(LDCM_W, LDCM_W, "ldcm.w"), + NORMAL_MNEMONIC(LDDPC, LDDPC, "lddpc"), + NORMAL_MNEMONIC(LDDSP, LDDSP, "lddsp"), + NORMAL_MNEMONIC(LDINS_B, LDINS_B, "ldins.b"), + NORMAL_MNEMONIC(LDINS_H, LDINS_H, "ldins.h"), + NORMAL_MNEMONIC(LDM, LDM, "ldm"), + NORMAL_MNEMONIC(LDMTS, LDMTS, "ldmts"), + NORMAL_MNEMONIC(LDSWP_SH, LDSWP_SH, "ldswp.sh"), + NORMAL_MNEMONIC(LDSWP_UH, LDSWP_UH, "ldswp.uh"), + NORMAL_MNEMONIC(LDSWP_W, LDSWP_W, "ldswp.w"), + NORMAL_MNEMONIC(LSL, LSL1, "lsl"), + NORMAL_MNEMONIC(LSR, LSR1, "lsr"), + NORMAL_MNEMONIC(MAC, MAC, "mac"), + NORMAL_MNEMONIC(MACHH_D, MACHH_D, "machh.d"), + NORMAL_MNEMONIC(MACHH_W, MACHH_W, "machh.w"), + NORMAL_MNEMONIC(MACS_D, MACS_D, "macs.d"), + NORMAL_MNEMONIC(MACSATHH_W, MACSATHH_W, "macsathh.w"), + NORMAL_MNEMONIC(MACU_D, MACUD, "macu.d"), + NORMAL_MNEMONIC(MACWH_D, MACWH_D, "macwh.d"), + NORMAL_MNEMONIC(MAX, MAX, "max"), + NORMAL_MNEMONIC(MCALL, MCALL, "mcall"), + NORMAL_MNEMONIC(MFDR, MFDR, "mfdr"), + NORMAL_MNEMONIC(MFSR, MFSR, "mfsr"), + NORMAL_MNEMONIC(MIN, MIN, "min"), + NORMAL_MNEMONIC(MOV, MOV3, "mov"), + NORMAL_MNEMONIC(MOVEQ, MOVEQ1, "moveq"), + NORMAL_MNEMONIC(MOVNE, MOVNE1, "movne"), + NORMAL_MNEMONIC(MOVCC, MOVCC1, "movcc"), + NORMAL_MNEMONIC(MOVCS, MOVCS1, "movcs"), + NORMAL_MNEMONIC(MOVGE, MOVGE1, "movge"), + NORMAL_MNEMONIC(MOVLT, MOVLT1, "movlt"), + NORMAL_MNEMONIC(MOVMI, MOVMI1, "movmi"), + NORMAL_MNEMONIC(MOVPL, MOVPL1, "movpl"), + NORMAL_MNEMONIC(MOVLS, MOVLS1, "movls"), + NORMAL_MNEMONIC(MOVGT, MOVGT1, "movgt"), + NORMAL_MNEMONIC(MOVLE, MOVLE1, "movle"), + NORMAL_MNEMONIC(MOVHI, MOVHI1, "movhi"), + NORMAL_MNEMONIC(MOVVS, MOVVS1, "movvs"), + NORMAL_MNEMONIC(MOVVC, MOVVC1, "movvc"), + NORMAL_MNEMONIC(MOVQS, MOVQS1, "movqs"), + NORMAL_MNEMONIC(MOVAL, MOVAL1, "moval"), + NORMAL_MNEMONIC(MOVHS, MOVHS1, "movhs"), + NORMAL_MNEMONIC(MOVLO, MOVLO1, "movlo"), + NORMAL_MNEMONIC(MTDR, MTDR, "mtdr"), + NORMAL_MNEMONIC(MTSR, MTSR, "mtsr"), + NORMAL_MNEMONIC(MUL, MUL1, "mul"), + NORMAL_MNEMONIC(MULHH_W, MULHH_W, "mulhh.w"), + NORMAL_MNEMONIC(MULNHH_W, MULNHH_W, "mulnhh.w"), + NORMAL_MNEMONIC(MULNWH_D, MULNWH_D, "mulnwh.d"), + NORMAL_MNEMONIC(MULS_D, MULSD, "muls.d"), + NORMAL_MNEMONIC(MULSATHH_H, MULSATHH_H, "mulsathh.h"), + NORMAL_MNEMONIC(MULSATHH_W, MULSATHH_W, "mulsathh.w"), + NORMAL_MNEMONIC(MULSATRNDHH_H, MULSATRNDHH_H, "mulsatrndhh.h"), + NORMAL_MNEMONIC(MULSATRNDWH_W, MULSATRNDWH_W, "mulsatrndwh.w"), + NORMAL_MNEMONIC(MULSATWH_W, MULSATWH_W, "mulsatwh.w"), + NORMAL_MNEMONIC(MULU_D, MULU_D, "mulu.d"), + NORMAL_MNEMONIC(MULWH_D, MULWH_D, "mulwh.d"), + NORMAL_MNEMONIC(MUSFR, MUSFR, "musfr"), + NORMAL_MNEMONIC(MUSTR, MUSTR, "mustr"), + NORMAL_MNEMONIC(MVCR_D, MVCR_D, "mvcr.d"), + NORMAL_MNEMONIC(MVCR_W, MVCR_W, "mvcr.w"), + NORMAL_MNEMONIC(MVRC_D, MVRC_D, "mvrc.d"), + NORMAL_MNEMONIC(MVRC_W, MVRC_W, "mvrc.w"), + NORMAL_MNEMONIC(NEG, NEG, "neg"), + NORMAL_MNEMONIC(NOP, NOP, "nop"), + NORMAL_MNEMONIC(OR, OR1, "or"), + NORMAL_MNEMONIC(ORH, ORH, "orh"), + NORMAL_MNEMONIC(ORL, ORL, "orl"), + NORMAL_MNEMONIC(PABS_SB, PABS_SB, "pabs.sb"), + NORMAL_MNEMONIC(PABS_SH, PABS_SH, "pabs.sh"), + NORMAL_MNEMONIC(PACKSH_SB, PACKSH_SB, "packsh.sb"), + NORMAL_MNEMONIC(PACKSH_UB, PACKSH_UB, "packsh.ub"), + NORMAL_MNEMONIC(PACKW_SH, PACKW_SH, "packw.sh"), + NORMAL_MNEMONIC(PADD_B, PADD_B, "padd.b"), + NORMAL_MNEMONIC(PADD_H, PADD_H, "padd.h"), + NORMAL_MNEMONIC(PADDH_SH, PADDH_SH, "paddh.sh"), + NORMAL_MNEMONIC(PADDH_UB, PADDH_UB, "paddh.ub"), + NORMAL_MNEMONIC(PADDS_SB, PADDS_SB, "padds.sb"), + NORMAL_MNEMONIC(PADDS_SH, PADDS_SH, "padds.sh"), + NORMAL_MNEMONIC(PADDS_UB, PADDS_UB, "padds.ub"), + NORMAL_MNEMONIC(PADDS_UH, PADDS_UH, "padds.uh"), + NORMAL_MNEMONIC(PADDSUB_H, PADDSUB_H, "paddsub.h"), + NORMAL_MNEMONIC(PADDSUBH_SH, PADDSUBH_SH, "paddsubh.sh"), + NORMAL_MNEMONIC(PADDSUBS_SH, PADDSUBS_SH, "paddsubs.sh"), + NORMAL_MNEMONIC(PADDSUBS_UH, PADDSUBS_UH, "paddsubs.uh"), + NORMAL_MNEMONIC(PADDX_H, PADDX_H, "paddx.h"), + NORMAL_MNEMONIC(PADDXH_SH, PADDXH_SH, "paddxh.sh"), + NORMAL_MNEMONIC(PADDXS_SH, PADDXS_SH, "paddxs.sh"), + NORMAL_MNEMONIC(PADDXS_UH, PADDXS_UH, "paddxs.uh"), + NORMAL_MNEMONIC(PASR_B, PASR_B, "pasr.b"), + NORMAL_MNEMONIC(PASR_H, PASR_H, "pasr.h"), + NORMAL_MNEMONIC(PAVG_SH, PAVG_SH, "pavg.sh"), + NORMAL_MNEMONIC(PAVG_UB, PAVG_UB, "pavg.ub"), + NORMAL_MNEMONIC(PLSL_B, PLSL_B, "plsl.b"), + NORMAL_MNEMONIC(PLSL_H, PLSL_H, "plsl.h"), + NORMAL_MNEMONIC(PLSR_B, PLSR_B, "plsr.b"), + NORMAL_MNEMONIC(PLSR_H, PLSR_H, "plsr.h"), + NORMAL_MNEMONIC(PMAX_SH, PMAX_SH, "pmax.sh"), + NORMAL_MNEMONIC(PMAX_UB, PMAX_UB, "pmax.ub"), + NORMAL_MNEMONIC(PMIN_SH, PMIN_SH, "pmin.sh"), + NORMAL_MNEMONIC(PMIN_UB, PMIN_UB, "pmin.ub"), + NORMAL_MNEMONIC(POPJC, POPJC, "popjc"), + NORMAL_MNEMONIC(POPM, POPM, "popm"), + NORMAL_MNEMONIC(PREF, PREF, "pref"), + NORMAL_MNEMONIC(PSAD, PSAD, "psad"), + NORMAL_MNEMONIC(PSUB_B, PSUB_B, "psub.b"), + NORMAL_MNEMONIC(PSUB_H, PSUB_H, "psub.h"), + NORMAL_MNEMONIC(PSUBADD_H, PSUBADD_H, "psubadd.h"), + NORMAL_MNEMONIC(PSUBADDH_SH, PSUBADDH_SH, "psubaddh.sh"), + NORMAL_MNEMONIC(PSUBADDS_SH, PSUBADDS_SH, "psubadds.sh"), + NORMAL_MNEMONIC(PSUBADDS_UH, PSUBADDS_UH, "psubadds.uh"), + NORMAL_MNEMONIC(PSUBH_SH, PSUBH_SH, "psubh.sh"), + NORMAL_MNEMONIC(PSUBH_UB, PSUBH_UB, "psubh.ub"), + NORMAL_MNEMONIC(PSUBS_SB, PSUBS_SB, "psubs.sb"), + NORMAL_MNEMONIC(PSUBS_SH, PSUBS_SH, "psubs.sh"), + NORMAL_MNEMONIC(PSUBS_UB, PSUBS_UB, "psubs.ub"), + NORMAL_MNEMONIC(PSUBS_UH, PSUBS_UH, "psubs.uh"), + NORMAL_MNEMONIC(PSUBX_H, PSUBX_H, "psubx.h"), + NORMAL_MNEMONIC(PSUBXH_SH, PSUBXH_SH, "psubxh.sh"), + NORMAL_MNEMONIC(PSUBXS_SH, PSUBXS_SH, "psubxs.sh"), + NORMAL_MNEMONIC(PSUBXS_UH, PSUBXS_UH, "psubxs.uh"), + NORMAL_MNEMONIC(PUNPCKSB_H, PUNPCKSB_H, "punpcksb.h"), + NORMAL_MNEMONIC(PUNPCKUB_H, PUNPCKUB_H, "punpckub.h"), + NORMAL_MNEMONIC(PUSHJC, PUSHJC, "pushjc"), + NORMAL_MNEMONIC(PUSHM, PUSHM, "pushm"), + NORMAL_MNEMONIC(RCALL, RCALL1, "rcall"), + NORMAL_MNEMONIC(RETEQ, RETEQ, "reteq"), + NORMAL_MNEMONIC(RETNE, RETNE, "retne"), + NORMAL_MNEMONIC(RETCC, RETCC, "retcc"), + NORMAL_MNEMONIC(RETCS, RETCS, "retcs"), + NORMAL_MNEMONIC(RETGE, RETGE, "retge"), + NORMAL_MNEMONIC(RETLT, RETLT, "retlt"), + NORMAL_MNEMONIC(RETMI, RETMI, "retmi"), + NORMAL_MNEMONIC(RETPL, RETPL, "retpl"), + NORMAL_MNEMONIC(RETLS, RETLS, "retls"), + NORMAL_MNEMONIC(RETGT, RETGT, "retgt"), + NORMAL_MNEMONIC(RETLE, RETLE, "retle"), + NORMAL_MNEMONIC(RETHI, RETHI, "rethi"), + NORMAL_MNEMONIC(RETVS, RETVS, "retvs"), + NORMAL_MNEMONIC(RETVC, RETVC, "retvc"), + NORMAL_MNEMONIC(RETQS, RETQS, "retqs"), + NORMAL_MNEMONIC(RETAL, RETAL, "retal"), + NORMAL_MNEMONIC(RETHS, RETHS, "reths"), + NORMAL_MNEMONIC(RETLO, RETLO, "retlo"), + NORMAL_MNEMONIC(RET, RETAL, "ret"), + NORMAL_MNEMONIC(RETD, RETD, "retd"), + NORMAL_MNEMONIC(RETE, RETE, "rete"), + NORMAL_MNEMONIC(RETJ, RETJ, "retj"), + NORMAL_MNEMONIC(RETS, RETS, "rets"), + NORMAL_MNEMONIC(RJMP, RJMP, "rjmp"), + NORMAL_MNEMONIC(ROL, ROL, "rol"), + NORMAL_MNEMONIC(ROR, ROR, "ror"), + NORMAL_MNEMONIC(RSUB, RSUB1, "rsub"), + NORMAL_MNEMONIC(SATADD_H, SATADD_H, "satadd.h"), + NORMAL_MNEMONIC(SATADD_W, SATADD_W, "satadd.w"), + NORMAL_MNEMONIC(SATRNDS, SATRNDS, "satrnds"), + NORMAL_MNEMONIC(SATRNDU, SATRNDU, "satrndu"), + NORMAL_MNEMONIC(SATS, SATS, "sats"), + NORMAL_MNEMONIC(SATSUB_H, SATSUB_H, "satsub.h"), + NORMAL_MNEMONIC(SATSUB_W, SATSUB_W1, "satsub.w"), + NORMAL_MNEMONIC(SATU, SATU, "satu"), + NORMAL_MNEMONIC(SBC, SBC, "sbc"), + NORMAL_MNEMONIC(SBR, SBR, "sbr"), + NORMAL_MNEMONIC(SCALL, SCALL, "scall"), + NORMAL_MNEMONIC(SCR, SCR, "scr"), + NORMAL_MNEMONIC(SLEEP, SLEEP, "sleep"), + NORMAL_MNEMONIC(SREQ, SREQ, "sreq"), + NORMAL_MNEMONIC(SRNE, SRNE, "srne"), + NORMAL_MNEMONIC(SRCC, SRCC, "srcc"), + NORMAL_MNEMONIC(SRCS, SRCS, "srcs"), + NORMAL_MNEMONIC(SRGE, SRGE, "srge"), + NORMAL_MNEMONIC(SRLT, SRLT, "srlt"), + NORMAL_MNEMONIC(SRMI, SRMI, "srmi"), + NORMAL_MNEMONIC(SRPL, SRPL, "srpl"), + NORMAL_MNEMONIC(SRLS, SRLS, "srls"), + NORMAL_MNEMONIC(SRGT, SRGT, "srgt"), + NORMAL_MNEMONIC(SRLE, SRLE, "srle"), + NORMAL_MNEMONIC(SRHI, SRHI, "srhi"), + NORMAL_MNEMONIC(SRVS, SRVS, "srvs"), + NORMAL_MNEMONIC(SRVC, SRVC, "srvc"), + NORMAL_MNEMONIC(SRQS, SRQS, "srqs"), + NORMAL_MNEMONIC(SRAL, SRAL, "sral"), + NORMAL_MNEMONIC(SRHS, SRHS, "srhs"), + NORMAL_MNEMONIC(SRLO, SRLO, "srlo"), + NORMAL_MNEMONIC(SSRF, SSRF, "ssrf"), + NORMAL_MNEMONIC(ST_B, ST_B1, "st.b"), + NORMAL_MNEMONIC(ST_D, ST_D1, "st.d"), + NORMAL_MNEMONIC(ST_H, ST_H1, "st.h"), + NORMAL_MNEMONIC(ST_W, ST_W1, "st.w"), + NORMAL_MNEMONIC(STC_D, STC_D3, "stc.d"), + NORMAL_MNEMONIC(STC_W, STC_W3, "stc.w"), + NORMAL_MNEMONIC(STC0_D, STC0_D, "stc0.d"), + NORMAL_MNEMONIC(STC0_W, STC0_W, "stc0.w"), + NORMAL_MNEMONIC(STCM_D, STCM_D, "stcm.d"), + NORMAL_MNEMONIC(STCM_W, STCM_W, "stcm.w"), + NORMAL_MNEMONIC(STCOND, STCOND, "stcond"), + NORMAL_MNEMONIC(STDSP, STDSP, "stdsp"), + NORMAL_MNEMONIC(STHH_W, STHH_W2, "sthh.w"), + NORMAL_MNEMONIC(STM, STM, "stm"), + NORMAL_MNEMONIC(STMTS, STMTS, "stmts"), + NORMAL_MNEMONIC(STSWP_H, STSWP_H, "stswp.h"), + NORMAL_MNEMONIC(STSWP_W, STSWP_W, "stswp.w"), + NORMAL_MNEMONIC(SUB, SUB1, "sub"), + NORMAL_MNEMONIC(SUBEQ, SUBEQ, "subeq"), + NORMAL_MNEMONIC(SUBNE, SUBNE, "subne"), + NORMAL_MNEMONIC(SUBCC, SUBCC, "subcc"), + NORMAL_MNEMONIC(SUBCS, SUBCS, "subcs"), + NORMAL_MNEMONIC(SUBGE, SUBGE, "subge"), + NORMAL_MNEMONIC(SUBLT, SUBLT, "sublt"), + NORMAL_MNEMONIC(SUBMI, SUBMI, "submi"), + NORMAL_MNEMONIC(SUBPL, SUBPL, "subpl"), + NORMAL_MNEMONIC(SUBLS, SUBLS, "subls"), + NORMAL_MNEMONIC(SUBGT, SUBGT, "subgt"), + NORMAL_MNEMONIC(SUBLE, SUBLE, "suble"), + NORMAL_MNEMONIC(SUBHI, SUBHI, "subhi"), + NORMAL_MNEMONIC(SUBVS, SUBVS, "subvs"), + NORMAL_MNEMONIC(SUBVC, SUBVC, "subvc"), + NORMAL_MNEMONIC(SUBQS, SUBQS, "subqs"), + NORMAL_MNEMONIC(SUBAL, SUBAL, "subal"), + NORMAL_MNEMONIC(SUBHS, SUBHS, "subhs"), + NORMAL_MNEMONIC(SUBLO, SUBLO, "sublo"), + NORMAL_MNEMONIC(SUBFEQ, SUBFEQ, "subfeq"), + NORMAL_MNEMONIC(SUBFNE, SUBFNE, "subfne"), + NORMAL_MNEMONIC(SUBFCC, SUBFCC, "subfcc"), + NORMAL_MNEMONIC(SUBFCS, SUBFCS, "subfcs"), + NORMAL_MNEMONIC(SUBFGE, SUBFGE, "subfge"), + NORMAL_MNEMONIC(SUBFLT, SUBFLT, "subflt"), + NORMAL_MNEMONIC(SUBFMI, SUBFMI, "subfmi"), + NORMAL_MNEMONIC(SUBFPL, SUBFPL, "subfpl"), + NORMAL_MNEMONIC(SUBFLS, SUBFLS, "subfls"), + NORMAL_MNEMONIC(SUBFGT, SUBFGT, "subfgt"), + NORMAL_MNEMONIC(SUBFLE, SUBFLE, "subfle"), + NORMAL_MNEMONIC(SUBFHI, SUBFHI, "subfhi"), + NORMAL_MNEMONIC(SUBFVS, SUBFVS, "subfvs"), + NORMAL_MNEMONIC(SUBFVC, SUBFVC, "subfvc"), + NORMAL_MNEMONIC(SUBFQS, SUBFQS, "subfqs"), + NORMAL_MNEMONIC(SUBFAL, SUBFAL, "subfal"), + NORMAL_MNEMONIC(SUBFHS, SUBFHS, "subfhs"), + NORMAL_MNEMONIC(SUBFLO, SUBFLO, "subflo"), + NORMAL_MNEMONIC(SUBHH_W, SUBHH_W, "subhh.w"), + NORMAL_MNEMONIC(SWAP_B, SWAP_B, "swap.b"), + NORMAL_MNEMONIC(SWAP_BH, SWAP_BH, "swap.bh"), + NORMAL_MNEMONIC(SWAP_H, SWAP_H, "swap.h"), + NORMAL_MNEMONIC(SYNC, SYNC, "sync"), + NORMAL_MNEMONIC(TLBR, TLBR, "tlbr"), + NORMAL_MNEMONIC(TLBS, TLBS, "tlbs"), + NORMAL_MNEMONIC(TLBW, TLBW, "tlbw"), + NORMAL_MNEMONIC(TNBZ, TNBZ, "tnbz"), + NORMAL_MNEMONIC(TST, TST, "tst"), + NORMAL_MNEMONIC(XCHG, XCHG, "xchg"), + NORMAL_MNEMONIC(MEMC, MEMC, "memc"), + NORMAL_MNEMONIC(MEMS, MEMS, "mems"), + NORMAL_MNEMONIC(MEMT, MEMT, "memt"), + FP_MNEMONIC(FADD, FADD, "fadd"), + FP_MNEMONIC(FSUB, FSUB, "fsub"), + FP_MNEMONIC(FMAC, FMAC, "fmac"), + FP_MNEMONIC(FNMAC, FNMAC, "fnmac"), + FP_MNEMONIC(FMSC, FMSC, "fmsc"), + FP_MNEMONIC(FNMSC, FNMSC, "fnmsc"), + FP_MNEMONIC(FMUL, FMUL, "fmul"), + FP_MNEMONIC(FNMUL, FNMUL, "fnmul"), + FP_MNEMONIC(FNEG, FNEG, "fneg"), + FP_MNEMONIC(FABS, FABS, "fabs"), + FP_MNEMONIC(FCMP, FCMP, "fcmp"), + FP_MNEMONIC(FMOV, FMOV1, "fmov"), + NORMAL_MNEMONIC(FCASTS_D, FCASTS_D, "fcasts.d"), + NORMAL_MNEMONIC(FCASTD_S, FCASTD_S, "fcastd.s"), + NORMAL_MNEMONIC(LDA_W, LDA_W, "lda.w"), + NORMAL_MNEMONIC(CALL, CALL, "call"), + }; +#undef NORMAL_MNEMONIC +#undef ALIAS_MNEMONIC +#undef FP_MNEMONIC Index: binutils-2.16.1-avr32/opcodes/avr32-opc.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/opcodes/avr32-opc.h 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,1551 @@ +/* Opcode tables for AVR32. + Copyright 2005, 2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This file is part of libopcodes. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "bfd.h" + +#define AVR32_MAX_OPERANDS 8 +#define AVR32_MAX_FIELDS 8 + +#define AVR32_V1 (1 << 1) +#define AVR32_SIMD (1 << 2) +#define AVR32_DSP (1 << 3) +#define AVR32_RMW (1 << 4) +#define AVR32_FP (1 << 16) + +/* Registers we commonly refer to */ +#define AVR32_REG_R12 12 +#define AVR32_REG_SP 13 +#define AVR32_REG_LR 14 +#define AVR32_REG_PC 15 + +struct avr32_ifield +{ + int id; + unsigned short bitsize; + unsigned short shift; + unsigned long mask; + + /* If the value doesn't fit, it will be truncated with no warning */ + void (*insert)(const struct avr32_ifield *, void *, unsigned long); + void (*extract)(const struct avr32_ifield *, void *, unsigned long *); +}; + +struct avr32_opcode +{ + int id; + int size; + unsigned long value; + unsigned long mask; + const struct avr32_syntax *syntax; + bfd_reloc_code_real_type reloc_type; + unsigned int nr_fields; + /* if relaxable, which field is variable, otherwise -1 */ + int var_field; + const struct avr32_ifield *fields[AVR32_MAX_FIELDS]; +}; + +struct avr32_alias +{ + int id; + const struct avr32_opcode *opc; + struct { + int is_opindex; + unsigned long value; + } operand_map[AVR32_MAX_OPERANDS]; +}; + +struct avr32_syntax +{ + int id; + unsigned long isa_flags; + const struct avr32_mnemonic *mnemonic; + int type; + union { + const struct avr32_opcode *opc; + const struct avr32_alias *alias; + } u; + const struct avr32_syntax *next; + /* negative means "vararg" */ + int nr_operands; + int operand[AVR32_MAX_OPERANDS]; +}; + +#if 0 +#define AVR32_ALIAS_MAKE_CONST(val) ((val) | 0x80000000UL) +#define AVR32_ALIAS_IS_CONST(mapval) (((mapval) & 0x80000000UL) != 0) +#define AVR32_ALIAS_GET_CONST(mapval) ((mapval) & ~0x80000000UL) +#endif + +struct avr32_mnemonic +{ + int id; + const char *name; + const struct avr32_syntax *syntax; +}; + +extern const struct avr32_ifield avr32_ifield_table[]; +extern struct avr32_opcode avr32_opc_table[]; +extern const struct avr32_syntax avr32_syntax_table[]; +extern const struct avr32_alias avr32_alias_table[]; +extern const struct avr32_mnemonic avr32_mnemonic_table[]; + +extern void avr32_insert_simple(const struct avr32_ifield *field, + void *buf, unsigned long value); +extern void avr32_insert_bit5c(const struct avr32_ifield *field, + void *buf, unsigned long value); +extern void avr32_insert_k10(const struct avr32_ifield *field, + void *buf, unsigned long value); +extern void avr32_insert_k21(const struct avr32_ifield *field, + void *buf, unsigned long value); +extern void avr32_insert_cpop(const struct avr32_ifield *field, + void *buf, unsigned long value); +extern void avr32_insert_k12cp(const struct avr32_ifield *field, + void *buf, unsigned long value); + +extern void avr32_extract_simple(const struct avr32_ifield *field, + void *buf, unsigned long *value); +extern void avr32_extract_bit5c(const struct avr32_ifield *field, + void *buf, unsigned long *value); +extern void avr32_extract_k10(const struct avr32_ifield *field, + void *buf, unsigned long *value); +extern void avr32_extract_k21(const struct avr32_ifield *field, + void *buf, unsigned long *value); +extern void avr32_extract_cpop(const struct avr32_ifield *field, + void *buf, unsigned long *value); +extern void avr32_extract_k12cp(const struct avr32_ifield *field, + void *buf, unsigned long *value); + +enum avr32_operand_type +{ + AVR32_OPERAND_INTREG, /* just a register */ + AVR32_OPERAND_INTREG_PREDEC, /* register with pre-decrement */ + AVR32_OPERAND_INTREG_POSTINC, /* register with post-increment */ + AVR32_OPERAND_INTREG_LSL, /* register with left shift */ + AVR32_OPERAND_INTREG_LSR, /* register with right shift */ + AVR32_OPERAND_INTREG_BSEL, /* register with byte selector */ + AVR32_OPERAND_INTREG_HSEL, /* register with halfword selector */ + AVR32_OPERAND_INTREG_SDISP, /* Rp[signed disp] */ + AVR32_OPERAND_INTREG_SDISP_H, /* Rp[signed hword-aligned disp] */ + AVR32_OPERAND_INTREG_SDISP_W, /* Rp[signed word-aligned disp] */ + AVR32_OPERAND_INTREG_UDISP, /* Rp[unsigned disp] */ + AVR32_OPERAND_INTREG_UDISP_H, /* Rp[unsigned hword-aligned disp] */ + AVR32_OPERAND_INTREG_UDISP_W, /* Rp[unsigned word-aligned disp] */ + AVR32_OPERAND_INTREG_INDEX, /* Rp[Ri << sa] */ + AVR32_OPERAND_INTREG_XINDEX, /* Rp[Ri:bytesel << 2] */ + AVR32_OPERAND_DWREG, /* Even-numbered register */ + AVR32_OPERAND_PC_UDISP_W, /* PC[unsigned word-aligned disp] or label */ + AVR32_OPERAND_SP, /* Just SP */ + AVR32_OPERAND_SP_UDISP_W, /* SP[unsigned word-aligned disp] */ + AVR32_OPERAND_CPNO, + AVR32_OPERAND_CPREG, + AVR32_OPERAND_CPREG_D, + AVR32_OPERAND_UNSIGNED_CONST, + AVR32_OPERAND_UNSIGNED_CONST_W, + AVR32_OPERAND_SIGNED_CONST, + AVR32_OPERAND_SIGNED_CONST_W, + AVR32_OPERAND_JMPLABEL, + AVR32_OPERAND_UNSIGNED_NUMBER, + AVR32_OPERAND_UNSIGNED_NUMBER_W, + AVR32_OPERAND_REGLIST8, + AVR32_OPERAND_REGLIST9, + AVR32_OPERAND_REGLIST16, + AVR32_OPERAND_REGLIST_LDM, + AVR32_OPERAND_REGLIST_CP8, + AVR32_OPERAND_REGLIST_CPD8, + AVR32_OPERAND_RETVAL, + AVR32_OPERAND_MCALL, + AVR32_OPERAND_JOSPINC, + AVR32_OPERAND_COH, + AVR32_OPERAND_FPREG_S, + AVR32_OPERAND_FPREG_D, + AVR32_OPERAND__END_ +}; +#define AVR32_OPERAND_UNKNOWN AVR32_OPERAND__END_ +#define AVR32_NR_OPERANDS AVR32_OPERAND__END_ + +enum avr32_ifield_type +{ + AVR32_IFIELD_RX, + AVR32_IFIELD_RY, + AVR32_IFIELD_COND4C, + AVR32_IFIELD_K8C, + AVR32_IFIELD_K7C, + AVR32_IFIELD_K5C, + AVR32_IFIELD_K3, + AVR32_IFIELD_RY_DW, + AVR32_IFIELD_COND4E, + AVR32_IFIELD_K8E, + AVR32_IFIELD_BIT5C, + AVR32_IFIELD_COND3, + AVR32_IFIELD_K10, + AVR32_IFIELD_POPM, + AVR32_IFIELD_K2, + AVR32_IFIELD_RD_E, + AVR32_IFIELD_RD_DW, + AVR32_IFIELD_X, + AVR32_IFIELD_Y, + AVR32_IFIELD_X2, + AVR32_IFIELD_Y2, + AVR32_IFIELD_K5E, + AVR32_IFIELD_PART2, + AVR32_IFIELD_PART1, + AVR32_IFIELD_K16, + AVR32_IFIELD_CACHEOP, + AVR32_IFIELD_K11, + AVR32_IFIELD_K21, + AVR32_IFIELD_CPOP, + AVR32_IFIELD_CPNO, + AVR32_IFIELD_CRD_RI, + AVR32_IFIELD_CRX, + AVR32_IFIELD_CRY, + AVR32_IFIELD_K7E, + AVR32_IFIELD_CRD_DW, + AVR32_IFIELD_PART1_K12, + AVR32_IFIELD_PART2_K12, + AVR32_IFIELD_K12, + AVR32_IFIELD_S5, + AVR32_IFIELD_K5E2, + AVR32_IFIELD_K4, + AVR32_IFIELD_COND4E2, + AVR32_IFIELD_K8E2, + AVR32_IFIELD_K6, + AVR32_IFIELD_MEM15, + AVR32_IFIELD_MEMB5, + AVR32_IFIELD_W, + AVR32_IFIELD_CM_HL, + AVR32_IFIELD_K12CP, + AVR32_IFIELD__END_, +}; +#define AVR32_NR_IFIELDS AVR32_IFIELD__END_ + +enum avr32_opc_type +{ + AVR32_OPC_ABS, + AVR32_OPC_ACALL, + AVR32_OPC_ACR, + AVR32_OPC_ADC, + AVR32_OPC_ADD1, + AVR32_OPC_ADD2, + AVR32_OPC_ADDABS, + AVR32_OPC_ADDHH_W, + AVR32_OPC_AND1, + AVR32_OPC_AND2, + AVR32_OPC_AND3, + AVR32_OPC_ANDH, + AVR32_OPC_ANDH_COH, + AVR32_OPC_ANDL, + AVR32_OPC_ANDL_COH, + AVR32_OPC_ANDN, + AVR32_OPC_ASR1, + AVR32_OPC_ASR3, + AVR32_OPC_ASR2, + AVR32_OPC_BLD, + AVR32_OPC_BREQ1, + AVR32_OPC_BRNE1, + AVR32_OPC_BRCC1, + AVR32_OPC_BRCS1, + AVR32_OPC_BRGE1, + AVR32_OPC_BRLT1, + AVR32_OPC_BRMI1, + AVR32_OPC_BRPL1, + AVR32_OPC_BREQ2, + AVR32_OPC_BRNE2, + AVR32_OPC_BRCC2, + AVR32_OPC_BRCS2, + AVR32_OPC_BRGE2, + AVR32_OPC_BRLT2, + AVR32_OPC_BRMI2, + AVR32_OPC_BRPL2, + AVR32_OPC_BRLS, + AVR32_OPC_BRGT, + AVR32_OPC_BRLE, + AVR32_OPC_BRHI, + AVR32_OPC_BRVS, + AVR32_OPC_BRVC, + AVR32_OPC_BRQS, + AVR32_OPC_BRAL, + AVR32_OPC_BREAKPOINT, + AVR32_OPC_BREV, + AVR32_OPC_BST, + AVR32_OPC_CACHE, + AVR32_OPC_CASTS_B, + AVR32_OPC_CASTS_H, + AVR32_OPC_CASTU_B, + AVR32_OPC_CASTU_H, + AVR32_OPC_CBR, + AVR32_OPC_CLZ, + AVR32_OPC_COM, + AVR32_OPC_COP, + AVR32_OPC_CP_B, + AVR32_OPC_CP_H, + AVR32_OPC_CP_W1, + AVR32_OPC_CP_W2, + AVR32_OPC_CP_W3, + AVR32_OPC_CPC1, + AVR32_OPC_CPC2, + AVR32_OPC_CSRF, + AVR32_OPC_CSRFCZ, + AVR32_OPC_DIVS, + AVR32_OPC_DIVU, + AVR32_OPC_EOR1, + AVR32_OPC_EOR2, + AVR32_OPC_EOR3, + AVR32_OPC_EORL, + AVR32_OPC_EORH, + AVR32_OPC_FRS, + AVR32_OPC_ICALL, + AVR32_OPC_INCJOSP, + AVR32_OPC_LD_D1, + AVR32_OPC_LD_D2, + AVR32_OPC_LD_D3, + AVR32_OPC_LD_D5, + AVR32_OPC_LD_D4, + AVR32_OPC_LD_SB2, + AVR32_OPC_LD_SB1, + AVR32_OPC_LD_UB1, + AVR32_OPC_LD_UB2, + AVR32_OPC_LD_UB5, + AVR32_OPC_LD_UB3, + AVR32_OPC_LD_UB4, + AVR32_OPC_LD_SH1, + AVR32_OPC_LD_SH2, + AVR32_OPC_LD_SH5, + AVR32_OPC_LD_SH3, + AVR32_OPC_LD_SH4, + AVR32_OPC_LD_UH1, + AVR32_OPC_LD_UH2, + AVR32_OPC_LD_UH5, + AVR32_OPC_LD_UH3, + AVR32_OPC_LD_UH4, + AVR32_OPC_LD_W1, + AVR32_OPC_LD_W2, + AVR32_OPC_LD_W5, + AVR32_OPC_LD_W6, + AVR32_OPC_LD_W3, + AVR32_OPC_LD_W4, + AVR32_OPC_LDC_D1, + AVR32_OPC_LDC_D2, + AVR32_OPC_LDC_D3, + AVR32_OPC_LDC_W1, + AVR32_OPC_LDC_W2, + AVR32_OPC_LDC_W3, + AVR32_OPC_LDC0_D, + AVR32_OPC_LDC0_W, + AVR32_OPC_LDCM_D, + AVR32_OPC_LDCM_D_PU, + AVR32_OPC_LDCM_W, + AVR32_OPC_LDCM_W_PU, + AVR32_OPC_LDDPC, + AVR32_OPC_LDDPC_EXT, + AVR32_OPC_LDDSP, + AVR32_OPC_LDINS_B, + AVR32_OPC_LDINS_H, + AVR32_OPC_LDM, + AVR32_OPC_LDMTS, + AVR32_OPC_LDMTS_PU, + AVR32_OPC_LDSWP_SH, + AVR32_OPC_LDSWP_UH, + AVR32_OPC_LDSWP_W, + AVR32_OPC_LSL1, + AVR32_OPC_LSL3, + AVR32_OPC_LSL2, + AVR32_OPC_LSR1, + AVR32_OPC_LSR3, + AVR32_OPC_LSR2, + AVR32_OPC_MAC, + AVR32_OPC_MACHH_D, + AVR32_OPC_MACHH_W, + AVR32_OPC_MACS_D, + AVR32_OPC_MACSATHH_W, + AVR32_OPC_MACUD, + AVR32_OPC_MACWH_D, + AVR32_OPC_MAX, + AVR32_OPC_MCALL, + AVR32_OPC_MFDR, + AVR32_OPC_MFSR, + AVR32_OPC_MIN, + AVR32_OPC_MOV3, + AVR32_OPC_MOV1, + AVR32_OPC_MOV2, + AVR32_OPC_MOVEQ1, + AVR32_OPC_MOVNE1, + AVR32_OPC_MOVCC1, + AVR32_OPC_MOVCS1, + AVR32_OPC_MOVGE1, + AVR32_OPC_MOVLT1, + AVR32_OPC_MOVMI1, + AVR32_OPC_MOVPL1, + AVR32_OPC_MOVLS1, + AVR32_OPC_MOVGT1, + AVR32_OPC_MOVLE1, + AVR32_OPC_MOVHI1, + AVR32_OPC_MOVVS1, + AVR32_OPC_MOVVC1, + AVR32_OPC_MOVQS1, + AVR32_OPC_MOVAL1, + AVR32_OPC_MOVEQ2, + AVR32_OPC_MOVNE2, + AVR32_OPC_MOVCC2, + AVR32_OPC_MOVCS2, + AVR32_OPC_MOVGE2, + AVR32_OPC_MOVLT2, + AVR32_OPC_MOVMI2, + AVR32_OPC_MOVPL2, + AVR32_OPC_MOVLS2, + AVR32_OPC_MOVGT2, + AVR32_OPC_MOVLE2, + AVR32_OPC_MOVHI2, + AVR32_OPC_MOVVS2, + AVR32_OPC_MOVVC2, + AVR32_OPC_MOVQS2, + AVR32_OPC_MOVAL2, + AVR32_OPC_MTDR, + AVR32_OPC_MTSR, + AVR32_OPC_MUL1, + AVR32_OPC_MUL2, + AVR32_OPC_MUL3, + AVR32_OPC_MULHH_W, + AVR32_OPC_MULNHH_W, + AVR32_OPC_MULNWH_D, + AVR32_OPC_MULSD, + AVR32_OPC_MULSATHH_H, + AVR32_OPC_MULSATHH_W, + AVR32_OPC_MULSATRNDHH_H, + AVR32_OPC_MULSATRNDWH_W, + AVR32_OPC_MULSATWH_W, + AVR32_OPC_MULU_D, + AVR32_OPC_MULWH_D, + AVR32_OPC_MUSFR, + AVR32_OPC_MUSTR, + AVR32_OPC_MVCR_D, + AVR32_OPC_MVCR_W, + AVR32_OPC_MVRC_D, + AVR32_OPC_MVRC_W, + AVR32_OPC_NEG, + AVR32_OPC_NOP, + AVR32_OPC_OR1, + AVR32_OPC_OR2, + AVR32_OPC_OR3, + AVR32_OPC_ORH, + AVR32_OPC_ORL, + AVR32_OPC_PABS_SB, + AVR32_OPC_PABS_SH, + AVR32_OPC_PACKSH_SB, + AVR32_OPC_PACKSH_UB, + AVR32_OPC_PACKW_SH, + AVR32_OPC_PADD_B, + AVR32_OPC_PADD_H, + AVR32_OPC_PADDH_SH, + AVR32_OPC_PADDH_UB, + AVR32_OPC_PADDS_SB, + AVR32_OPC_PADDS_SH, + AVR32_OPC_PADDS_UB, + AVR32_OPC_PADDS_UH, + AVR32_OPC_PADDSUB_H, + AVR32_OPC_PADDSUBH_SH, + AVR32_OPC_PADDSUBS_SH, + AVR32_OPC_PADDSUBS_UH, + AVR32_OPC_PADDX_H, + AVR32_OPC_PADDXH_SH, + AVR32_OPC_PADDXS_SH, + AVR32_OPC_PADDXS_UH, + AVR32_OPC_PASR_B, + AVR32_OPC_PASR_H, + AVR32_OPC_PAVG_SH, + AVR32_OPC_PAVG_UB, + AVR32_OPC_PLSL_B, + AVR32_OPC_PLSL_H, + AVR32_OPC_PLSR_B, + AVR32_OPC_PLSR_H, + AVR32_OPC_PMAX_SH, + AVR32_OPC_PMAX_UB, + AVR32_OPC_PMIN_SH, + AVR32_OPC_PMIN_UB, + AVR32_OPC_POPJC, + AVR32_OPC_POPM, + AVR32_OPC_POPM_E, + AVR32_OPC_PREF, + AVR32_OPC_PSAD, + AVR32_OPC_PSUB_B, + AVR32_OPC_PSUB_H, + AVR32_OPC_PSUBADD_H, + AVR32_OPC_PSUBADDH_SH, + AVR32_OPC_PSUBADDS_SH, + AVR32_OPC_PSUBADDS_UH, + AVR32_OPC_PSUBH_SH, + AVR32_OPC_PSUBH_UB, + AVR32_OPC_PSUBS_SB, + AVR32_OPC_PSUBS_SH, + AVR32_OPC_PSUBS_UB, + AVR32_OPC_PSUBS_UH, + AVR32_OPC_PSUBX_H, + AVR32_OPC_PSUBXH_SH, + AVR32_OPC_PSUBXS_SH, + AVR32_OPC_PSUBXS_UH, + AVR32_OPC_PUNPCKSB_H, + AVR32_OPC_PUNPCKUB_H, + AVR32_OPC_PUSHJC, + AVR32_OPC_PUSHM, + AVR32_OPC_PUSHM_E, + AVR32_OPC_RCALL1, + AVR32_OPC_RCALL2, + AVR32_OPC_RETEQ, + AVR32_OPC_RETNE, + AVR32_OPC_RETCC, + AVR32_OPC_RETCS, + AVR32_OPC_RETGE, + AVR32_OPC_RETLT, + AVR32_OPC_RETMI, + AVR32_OPC_RETPL, + AVR32_OPC_RETLS, + AVR32_OPC_RETGT, + AVR32_OPC_RETLE, + AVR32_OPC_RETHI, + AVR32_OPC_RETVS, + AVR32_OPC_RETVC, + AVR32_OPC_RETQS, + AVR32_OPC_RETAL, + AVR32_OPC_RETD, + AVR32_OPC_RETE, + AVR32_OPC_RETJ, + AVR32_OPC_RETS, + AVR32_OPC_RJMP, + AVR32_OPC_ROL, + AVR32_OPC_ROR, + AVR32_OPC_RSUB1, + AVR32_OPC_RSUB2, + AVR32_OPC_SATADD_H, + AVR32_OPC_SATADD_W, + AVR32_OPC_SATRNDS, + AVR32_OPC_SATRNDU, + AVR32_OPC_SATS, + AVR32_OPC_SATSUB_H, + AVR32_OPC_SATSUB_W1, + AVR32_OPC_SATSUB_W2, + AVR32_OPC_SATU, + AVR32_OPC_SBC, + AVR32_OPC_SBR, + AVR32_OPC_SCALL, + AVR32_OPC_SCR, + AVR32_OPC_SLEEP, + AVR32_OPC_SREQ, + AVR32_OPC_SRNE, + AVR32_OPC_SRCC, + AVR32_OPC_SRCS, + AVR32_OPC_SRGE, + AVR32_OPC_SRLT, + AVR32_OPC_SRMI, + AVR32_OPC_SRPL, + AVR32_OPC_SRLS, + AVR32_OPC_SRGT, + AVR32_OPC_SRLE, + AVR32_OPC_SRHI, + AVR32_OPC_SRVS, + AVR32_OPC_SRVC, + AVR32_OPC_SRQS, + AVR32_OPC_SRAL, + AVR32_OPC_SSRF, + AVR32_OPC_ST_B1, + AVR32_OPC_ST_B2, + AVR32_OPC_ST_B5, + AVR32_OPC_ST_B3, + AVR32_OPC_ST_B4, + AVR32_OPC_ST_D1, + AVR32_OPC_ST_D2, + AVR32_OPC_ST_D3, + AVR32_OPC_ST_D5, + AVR32_OPC_ST_D4, + AVR32_OPC_ST_H1, + AVR32_OPC_ST_H2, + AVR32_OPC_ST_H5, + AVR32_OPC_ST_H3, + AVR32_OPC_ST_H4, + AVR32_OPC_ST_W1, + AVR32_OPC_ST_W2, + AVR32_OPC_ST_W5, + AVR32_OPC_ST_W3, + AVR32_OPC_ST_W4, + AVR32_OPC_STC_D1, + AVR32_OPC_STC_D2, + AVR32_OPC_STC_D3, + AVR32_OPC_STC_W1, + AVR32_OPC_STC_W2, + AVR32_OPC_STC_W3, + AVR32_OPC_STC0_D, + AVR32_OPC_STC0_W, + AVR32_OPC_STCM_D, + AVR32_OPC_STCM_D_PU, + AVR32_OPC_STCM_W, + AVR32_OPC_STCM_W_PU, + AVR32_OPC_STCOND, + AVR32_OPC_STDSP, + AVR32_OPC_STHH_W2, + AVR32_OPC_STHH_W1, + AVR32_OPC_STM, + AVR32_OPC_STM_PU, + AVR32_OPC_STMTS, + AVR32_OPC_STMTS_PU, + AVR32_OPC_STSWP_H, + AVR32_OPC_STSWP_W, + AVR32_OPC_SUB1, + AVR32_OPC_SUB2, + AVR32_OPC_SUB5, + AVR32_OPC_SUB3_SP, + AVR32_OPC_SUB3, + AVR32_OPC_SUB4, + AVR32_OPC_SUBEQ, + AVR32_OPC_SUBNE, + AVR32_OPC_SUBCC, + AVR32_OPC_SUBCS, + AVR32_OPC_SUBGE, + AVR32_OPC_SUBLT, + AVR32_OPC_SUBMI, + AVR32_OPC_SUBPL, + AVR32_OPC_SUBLS, + AVR32_OPC_SUBGT, + AVR32_OPC_SUBLE, + AVR32_OPC_SUBHI, + AVR32_OPC_SUBVS, + AVR32_OPC_SUBVC, + AVR32_OPC_SUBQS, + AVR32_OPC_SUBAL, + AVR32_OPC_SUBFEQ, + AVR32_OPC_SUBFNE, + AVR32_OPC_SUBFCC, + AVR32_OPC_SUBFCS, + AVR32_OPC_SUBFGE, + AVR32_OPC_SUBFLT, + AVR32_OPC_SUBFMI, + AVR32_OPC_SUBFPL, + AVR32_OPC_SUBFLS, + AVR32_OPC_SUBFGT, + AVR32_OPC_SUBFLE, + AVR32_OPC_SUBFHI, + AVR32_OPC_SUBFVS, + AVR32_OPC_SUBFVC, + AVR32_OPC_SUBFQS, + AVR32_OPC_SUBFAL, + AVR32_OPC_SUBHH_W, + AVR32_OPC_SWAP_B, + AVR32_OPC_SWAP_BH, + AVR32_OPC_SWAP_H, + AVR32_OPC_SYNC, + AVR32_OPC_TLBR, + AVR32_OPC_TLBS, + AVR32_OPC_TLBW, + AVR32_OPC_TNBZ, + AVR32_OPC_TST, + AVR32_OPC_XCHG, + AVR32_OPC_MEMC, + AVR32_OPC_MEMS, + AVR32_OPC_MEMT, + AVR32_OPC_BFEXTS, + AVR32_OPC_BFEXTU, + AVR32_OPC_BFINS, + AVR32_OPC__END_ +}; +#define AVR32_NR_OPCODES AVR32_OPC__END_ + +enum avr32_syntax_type +{ + AVR32_SYNTAX_ABS, + AVR32_SYNTAX_ACALL, + AVR32_SYNTAX_ACR, + AVR32_SYNTAX_ADC, + AVR32_SYNTAX_ADD1, + AVR32_SYNTAX_ADD2, + AVR32_SYNTAX_ADDABS, + AVR32_SYNTAX_ADDHH_W, + AVR32_SYNTAX_AND1, + AVR32_SYNTAX_AND2, + AVR32_SYNTAX_AND3, + AVR32_SYNTAX_ANDH, + AVR32_SYNTAX_ANDH_COH, + AVR32_SYNTAX_ANDL, + AVR32_SYNTAX_ANDL_COH, + AVR32_SYNTAX_ANDN, + AVR32_SYNTAX_ASR1, + AVR32_SYNTAX_ASR3, + AVR32_SYNTAX_ASR2, + AVR32_SYNTAX_BFEXTS, + AVR32_SYNTAX_BFEXTU, + AVR32_SYNTAX_BFINS, + AVR32_SYNTAX_BLD, + AVR32_SYNTAX_BREQ1, + AVR32_SYNTAX_BRNE1, + AVR32_SYNTAX_BRCC1, + AVR32_SYNTAX_BRCS1, + AVR32_SYNTAX_BRGE1, + AVR32_SYNTAX_BRLT1, + AVR32_SYNTAX_BRMI1, + AVR32_SYNTAX_BRPL1, + AVR32_SYNTAX_BRHS1, + AVR32_SYNTAX_BRLO1, + AVR32_SYNTAX_BREQ2, + AVR32_SYNTAX_BRNE2, + AVR32_SYNTAX_BRCC2, + AVR32_SYNTAX_BRCS2, + AVR32_SYNTAX_BRGE2, + AVR32_SYNTAX_BRLT2, + AVR32_SYNTAX_BRMI2, + AVR32_SYNTAX_BRPL2, + AVR32_SYNTAX_BRLS, + AVR32_SYNTAX_BRGT, + AVR32_SYNTAX_BRLE, + AVR32_SYNTAX_BRHI, + AVR32_SYNTAX_BRVS, + AVR32_SYNTAX_BRVC, + AVR32_SYNTAX_BRQS, + AVR32_SYNTAX_BRAL, + AVR32_SYNTAX_BRHS2, + AVR32_SYNTAX_BRLO2, + AVR32_SYNTAX_BREAKPOINT, + AVR32_SYNTAX_BREV, + AVR32_SYNTAX_BST, + AVR32_SYNTAX_CACHE, + AVR32_SYNTAX_CASTS_B, + AVR32_SYNTAX_CASTS_H, + AVR32_SYNTAX_CASTU_B, + AVR32_SYNTAX_CASTU_H, + AVR32_SYNTAX_CBR, + AVR32_SYNTAX_CLZ, + AVR32_SYNTAX_COM, + AVR32_SYNTAX_COP, + AVR32_SYNTAX_CP_B, + AVR32_SYNTAX_CP_H, + AVR32_SYNTAX_CP_W1, + AVR32_SYNTAX_CP_W2, + AVR32_SYNTAX_CP_W3, + AVR32_SYNTAX_CPC1, + AVR32_SYNTAX_CPC2, + AVR32_SYNTAX_CSRF, + AVR32_SYNTAX_CSRFCZ, + AVR32_SYNTAX_DIVS, + AVR32_SYNTAX_DIVU, + AVR32_SYNTAX_EOR1, + AVR32_SYNTAX_EOR2, + AVR32_SYNTAX_EOR3, + AVR32_SYNTAX_EORL, + AVR32_SYNTAX_EORH, + AVR32_SYNTAX_FRS, + AVR32_SYNTAX_ICALL, + AVR32_SYNTAX_INCJOSP, + AVR32_SYNTAX_LD_D1, + AVR32_SYNTAX_LD_D2, + AVR32_SYNTAX_LD_D3, + AVR32_SYNTAX_LD_D5, + AVR32_SYNTAX_LD_D4, + AVR32_SYNTAX_LD_SB2, + AVR32_SYNTAX_LD_SB1, + AVR32_SYNTAX_LD_UB1, + AVR32_SYNTAX_LD_UB2, + AVR32_SYNTAX_LD_UB5, + AVR32_SYNTAX_LD_UB3, + AVR32_SYNTAX_LD_UB4, + AVR32_SYNTAX_LD_SH1, + AVR32_SYNTAX_LD_SH2, + AVR32_SYNTAX_LD_SH5, + AVR32_SYNTAX_LD_SH3, + AVR32_SYNTAX_LD_SH4, + AVR32_SYNTAX_LD_UH1, + AVR32_SYNTAX_LD_UH2, + AVR32_SYNTAX_LD_UH5, + AVR32_SYNTAX_LD_UH3, + AVR32_SYNTAX_LD_UH4, + AVR32_SYNTAX_LD_W1, + AVR32_SYNTAX_LD_W2, + AVR32_SYNTAX_LD_W5, + AVR32_SYNTAX_LD_W6, + AVR32_SYNTAX_LD_W3, + AVR32_SYNTAX_LD_W4, + AVR32_SYNTAX_LDC_D1, + AVR32_SYNTAX_LDC_D2, + AVR32_SYNTAX_LDC_D3, + AVR32_SYNTAX_LDC_W1, + AVR32_SYNTAX_LDC_W2, + AVR32_SYNTAX_LDC_W3, + AVR32_SYNTAX_LDC0_D, + AVR32_SYNTAX_LDC0_W, + AVR32_SYNTAX_LDCM_D, + AVR32_SYNTAX_LDCM_D_PU, + AVR32_SYNTAX_LDCM_W, + AVR32_SYNTAX_LDCM_W_PU, + AVR32_SYNTAX_LDDPC, + AVR32_SYNTAX_LDDPC_EXT, + AVR32_SYNTAX_LDDSP, + AVR32_SYNTAX_LDINS_B, + AVR32_SYNTAX_LDINS_H, + AVR32_SYNTAX_LDM, + AVR32_SYNTAX_LDMTS, + AVR32_SYNTAX_LDMTS_PU, + AVR32_SYNTAX_LDSWP_SH, + AVR32_SYNTAX_LDSWP_UH, + AVR32_SYNTAX_LDSWP_W, + AVR32_SYNTAX_LSL1, + AVR32_SYNTAX_LSL3, + AVR32_SYNTAX_LSL2, + AVR32_SYNTAX_LSR1, + AVR32_SYNTAX_LSR3, + AVR32_SYNTAX_LSR2, + AVR32_SYNTAX_MAC, + AVR32_SYNTAX_MACHH_D, + AVR32_SYNTAX_MACHH_W, + AVR32_SYNTAX_MACS_D, + AVR32_SYNTAX_MACSATHH_W, + AVR32_SYNTAX_MACUD, + AVR32_SYNTAX_MACWH_D, + AVR32_SYNTAX_MAX, + AVR32_SYNTAX_MCALL, + AVR32_SYNTAX_MFDR, + AVR32_SYNTAX_MFSR, + AVR32_SYNTAX_MIN, + AVR32_SYNTAX_MOV3, + AVR32_SYNTAX_MOV1, + AVR32_SYNTAX_MOV2, + AVR32_SYNTAX_MOVEQ1, + AVR32_SYNTAX_MOVNE1, + AVR32_SYNTAX_MOVCC1, + AVR32_SYNTAX_MOVCS1, + AVR32_SYNTAX_MOVGE1, + AVR32_SYNTAX_MOVLT1, + AVR32_SYNTAX_MOVMI1, + AVR32_SYNTAX_MOVPL1, + AVR32_SYNTAX_MOVLS1, + AVR32_SYNTAX_MOVGT1, + AVR32_SYNTAX_MOVLE1, + AVR32_SYNTAX_MOVHI1, + AVR32_SYNTAX_MOVVS1, + AVR32_SYNTAX_MOVVC1, + AVR32_SYNTAX_MOVQS1, + AVR32_SYNTAX_MOVAL1, + AVR32_SYNTAX_MOVHS1, + AVR32_SYNTAX_MOVLO1, + AVR32_SYNTAX_MOVEQ2, + AVR32_SYNTAX_MOVNE2, + AVR32_SYNTAX_MOVCC2, + AVR32_SYNTAX_MOVCS2, + AVR32_SYNTAX_MOVGE2, + AVR32_SYNTAX_MOVLT2, + AVR32_SYNTAX_MOVMI2, + AVR32_SYNTAX_MOVPL2, + AVR32_SYNTAX_MOVLS2, + AVR32_SYNTAX_MOVGT2, + AVR32_SYNTAX_MOVLE2, + AVR32_SYNTAX_MOVHI2, + AVR32_SYNTAX_MOVVS2, + AVR32_SYNTAX_MOVVC2, + AVR32_SYNTAX_MOVQS2, + AVR32_SYNTAX_MOVAL2, + AVR32_SYNTAX_MOVHS2, + AVR32_SYNTAX_MOVLO2, + AVR32_SYNTAX_MTDR, + AVR32_SYNTAX_MTSR, + AVR32_SYNTAX_MUL1, + AVR32_SYNTAX_MUL2, + AVR32_SYNTAX_MUL3, + AVR32_SYNTAX_MULHH_W, + AVR32_SYNTAX_MULNHH_W, + AVR32_SYNTAX_MULNWH_D, + AVR32_SYNTAX_MULSD, + AVR32_SYNTAX_MULSATHH_H, + AVR32_SYNTAX_MULSATHH_W, + AVR32_SYNTAX_MULSATRNDHH_H, + AVR32_SYNTAX_MULSATRNDWH_W, + AVR32_SYNTAX_MULSATWH_W, + AVR32_SYNTAX_MULU_D, + AVR32_SYNTAX_MULWH_D, + AVR32_SYNTAX_MUSFR, + AVR32_SYNTAX_MUSTR, + AVR32_SYNTAX_MVCR_D, + AVR32_SYNTAX_MVCR_W, + AVR32_SYNTAX_MVRC_D, + AVR32_SYNTAX_MVRC_W, + AVR32_SYNTAX_NEG, + AVR32_SYNTAX_NOP, + AVR32_SYNTAX_OR1, + AVR32_SYNTAX_OR2, + AVR32_SYNTAX_OR3, + AVR32_SYNTAX_ORH, + AVR32_SYNTAX_ORL, + AVR32_SYNTAX_PABS_SB, + AVR32_SYNTAX_PABS_SH, + AVR32_SYNTAX_PACKSH_SB, + AVR32_SYNTAX_PACKSH_UB, + AVR32_SYNTAX_PACKW_SH, + AVR32_SYNTAX_PADD_B, + AVR32_SYNTAX_PADD_H, + AVR32_SYNTAX_PADDH_SH, + AVR32_SYNTAX_PADDH_UB, + AVR32_SYNTAX_PADDS_SB, + AVR32_SYNTAX_PADDS_SH, + AVR32_SYNTAX_PADDS_UB, + AVR32_SYNTAX_PADDS_UH, + AVR32_SYNTAX_PADDSUB_H, + AVR32_SYNTAX_PADDSUBH_SH, + AVR32_SYNTAX_PADDSUBS_SH, + AVR32_SYNTAX_PADDSUBS_UH, + AVR32_SYNTAX_PADDX_H, + AVR32_SYNTAX_PADDXH_SH, + AVR32_SYNTAX_PADDXS_SH, + AVR32_SYNTAX_PADDXS_UH, + AVR32_SYNTAX_PASR_B, + AVR32_SYNTAX_PASR_H, + AVR32_SYNTAX_PAVG_SH, + AVR32_SYNTAX_PAVG_UB, + AVR32_SYNTAX_PLSL_B, + AVR32_SYNTAX_PLSL_H, + AVR32_SYNTAX_PLSR_B, + AVR32_SYNTAX_PLSR_H, + AVR32_SYNTAX_PMAX_SH, + AVR32_SYNTAX_PMAX_UB, + AVR32_SYNTAX_PMIN_SH, + AVR32_SYNTAX_PMIN_UB, + AVR32_SYNTAX_POPJC, + AVR32_SYNTAX_POPM, + AVR32_SYNTAX_POPM_E, + AVR32_SYNTAX_PREF, + AVR32_SYNTAX_PSAD, + AVR32_SYNTAX_PSUB_B, + AVR32_SYNTAX_PSUB_H, + AVR32_SYNTAX_PSUBADD_H, + AVR32_SYNTAX_PSUBADDH_SH, + AVR32_SYNTAX_PSUBADDS_SH, + AVR32_SYNTAX_PSUBADDS_UH, + AVR32_SYNTAX_PSUBH_SH, + AVR32_SYNTAX_PSUBH_UB, + AVR32_SYNTAX_PSUBS_SB, + AVR32_SYNTAX_PSUBS_SH, + AVR32_SYNTAX_PSUBS_UB, + AVR32_SYNTAX_PSUBS_UH, + AVR32_SYNTAX_PSUBX_H, + AVR32_SYNTAX_PSUBXH_SH, + AVR32_SYNTAX_PSUBXS_SH, + AVR32_SYNTAX_PSUBXS_UH, + AVR32_SYNTAX_PUNPCKSB_H, + AVR32_SYNTAX_PUNPCKUB_H, + AVR32_SYNTAX_PUSHJC, + AVR32_SYNTAX_PUSHM, + AVR32_SYNTAX_PUSHM_E, + AVR32_SYNTAX_RCALL1, + AVR32_SYNTAX_RCALL2, + AVR32_SYNTAX_RETEQ, + AVR32_SYNTAX_RETNE, + AVR32_SYNTAX_RETCC, + AVR32_SYNTAX_RETCS, + AVR32_SYNTAX_RETGE, + AVR32_SYNTAX_RETLT, + AVR32_SYNTAX_RETMI, + AVR32_SYNTAX_RETPL, + AVR32_SYNTAX_RETLS, + AVR32_SYNTAX_RETGT, + AVR32_SYNTAX_RETLE, + AVR32_SYNTAX_RETHI, + AVR32_SYNTAX_RETVS, + AVR32_SYNTAX_RETVC, + AVR32_SYNTAX_RETQS, + AVR32_SYNTAX_RETAL, + AVR32_SYNTAX_RETHS, + AVR32_SYNTAX_RETLO, + AVR32_SYNTAX_RETD, + AVR32_SYNTAX_RETE, + AVR32_SYNTAX_RETJ, + AVR32_SYNTAX_RETS, + AVR32_SYNTAX_RJMP, + AVR32_SYNTAX_ROL, + AVR32_SYNTAX_ROR, + AVR32_SYNTAX_RSUB1, + AVR32_SYNTAX_RSUB2, + AVR32_SYNTAX_SATADD_H, + AVR32_SYNTAX_SATADD_W, + AVR32_SYNTAX_SATRNDS, + AVR32_SYNTAX_SATRNDU, + AVR32_SYNTAX_SATS, + AVR32_SYNTAX_SATSUB_H, + AVR32_SYNTAX_SATSUB_W1, + AVR32_SYNTAX_SATSUB_W2, + AVR32_SYNTAX_SATU, + AVR32_SYNTAX_SBC, + AVR32_SYNTAX_SBR, + AVR32_SYNTAX_SCALL, + AVR32_SYNTAX_SCR, + AVR32_SYNTAX_SLEEP, + AVR32_SYNTAX_SREQ, + AVR32_SYNTAX_SRNE, + AVR32_SYNTAX_SRCC, + AVR32_SYNTAX_SRCS, + AVR32_SYNTAX_SRGE, + AVR32_SYNTAX_SRLT, + AVR32_SYNTAX_SRMI, + AVR32_SYNTAX_SRPL, + AVR32_SYNTAX_SRLS, + AVR32_SYNTAX_SRGT, + AVR32_SYNTAX_SRLE, + AVR32_SYNTAX_SRHI, + AVR32_SYNTAX_SRVS, + AVR32_SYNTAX_SRVC, + AVR32_SYNTAX_SRQS, + AVR32_SYNTAX_SRAL, + AVR32_SYNTAX_SRHS, + AVR32_SYNTAX_SRLO, + AVR32_SYNTAX_SSRF, + AVR32_SYNTAX_ST_B1, + AVR32_SYNTAX_ST_B2, + AVR32_SYNTAX_ST_B5, + AVR32_SYNTAX_ST_B3, + AVR32_SYNTAX_ST_B4, + AVR32_SYNTAX_ST_D1, + AVR32_SYNTAX_ST_D2, + AVR32_SYNTAX_ST_D3, + AVR32_SYNTAX_ST_D5, + AVR32_SYNTAX_ST_D4, + AVR32_SYNTAX_ST_H1, + AVR32_SYNTAX_ST_H2, + AVR32_SYNTAX_ST_H5, + AVR32_SYNTAX_ST_H3, + AVR32_SYNTAX_ST_H4, + AVR32_SYNTAX_ST_W1, + AVR32_SYNTAX_ST_W2, + AVR32_SYNTAX_ST_W5, + AVR32_SYNTAX_ST_W3, + AVR32_SYNTAX_ST_W4, + AVR32_SYNTAX_STC_D1, + AVR32_SYNTAX_STC_D2, + AVR32_SYNTAX_STC_D3, + AVR32_SYNTAX_STC_W1, + AVR32_SYNTAX_STC_W2, + AVR32_SYNTAX_STC_W3, + AVR32_SYNTAX_STC0_D, + AVR32_SYNTAX_STC0_W, + AVR32_SYNTAX_STCM_D, + AVR32_SYNTAX_STCM_D_PU, + AVR32_SYNTAX_STCM_W, + AVR32_SYNTAX_STCM_W_PU, + AVR32_SYNTAX_STCOND, + AVR32_SYNTAX_STDSP, + AVR32_SYNTAX_STHH_W2, + AVR32_SYNTAX_STHH_W1, + AVR32_SYNTAX_STM, + AVR32_SYNTAX_STM_PU, + AVR32_SYNTAX_STMTS, + AVR32_SYNTAX_STMTS_PU, + AVR32_SYNTAX_STSWP_H, + AVR32_SYNTAX_STSWP_W, + AVR32_SYNTAX_SUB1, + AVR32_SYNTAX_SUB2, + AVR32_SYNTAX_SUB5, + AVR32_SYNTAX_SUB3_SP, + AVR32_SYNTAX_SUB3, + AVR32_SYNTAX_SUB4, + AVR32_SYNTAX_SUBEQ, + AVR32_SYNTAX_SUBNE, + AVR32_SYNTAX_SUBCC, + AVR32_SYNTAX_SUBCS, + AVR32_SYNTAX_SUBGE, + AVR32_SYNTAX_SUBLT, + AVR32_SYNTAX_SUBMI, + AVR32_SYNTAX_SUBPL, + AVR32_SYNTAX_SUBLS, + AVR32_SYNTAX_SUBGT, + AVR32_SYNTAX_SUBLE, + AVR32_SYNTAX_SUBHI, + AVR32_SYNTAX_SUBVS, + AVR32_SYNTAX_SUBVC, + AVR32_SYNTAX_SUBQS, + AVR32_SYNTAX_SUBAL, + AVR32_SYNTAX_SUBHS, + AVR32_SYNTAX_SUBLO, + AVR32_SYNTAX_SUBFEQ, + AVR32_SYNTAX_SUBFNE, + AVR32_SYNTAX_SUBFCC, + AVR32_SYNTAX_SUBFCS, + AVR32_SYNTAX_SUBFGE, + AVR32_SYNTAX_SUBFLT, + AVR32_SYNTAX_SUBFMI, + AVR32_SYNTAX_SUBFPL, + AVR32_SYNTAX_SUBFLS, + AVR32_SYNTAX_SUBFGT, + AVR32_SYNTAX_SUBFLE, + AVR32_SYNTAX_SUBFHI, + AVR32_SYNTAX_SUBFVS, + AVR32_SYNTAX_SUBFVC, + AVR32_SYNTAX_SUBFQS, + AVR32_SYNTAX_SUBFAL, + AVR32_SYNTAX_SUBFHS, + AVR32_SYNTAX_SUBFLO, + AVR32_SYNTAX_SUBHH_W, + AVR32_SYNTAX_SWAP_B, + AVR32_SYNTAX_SWAP_BH, + AVR32_SYNTAX_SWAP_H, + AVR32_SYNTAX_SYNC, + AVR32_SYNTAX_TLBR, + AVR32_SYNTAX_TLBS, + AVR32_SYNTAX_TLBW, + AVR32_SYNTAX_TNBZ, + AVR32_SYNTAX_TST, + AVR32_SYNTAX_XCHG, + AVR32_SYNTAX_MEMC, + AVR32_SYNTAX_MEMS, + AVR32_SYNTAX_MEMT, + AVR32_SYNTAX_FADD_S, + AVR32_SYNTAX_FADD_D, + AVR32_SYNTAX_FSUB_S, + AVR32_SYNTAX_FSUB_D, + AVR32_SYNTAX_FMAC_S, + AVR32_SYNTAX_FMAC_D, + AVR32_SYNTAX_FNMAC_S, + AVR32_SYNTAX_FNMAC_D, + AVR32_SYNTAX_FMSC_S, + AVR32_SYNTAX_FMSC_D, + AVR32_SYNTAX_FNMSC_S, + AVR32_SYNTAX_FNMSC_D, + AVR32_SYNTAX_FMUL_S, + AVR32_SYNTAX_FMUL_D, + AVR32_SYNTAX_FNMUL_S, + AVR32_SYNTAX_FNMUL_D, + AVR32_SYNTAX_FNEG_S, + AVR32_SYNTAX_FNEG_D, + AVR32_SYNTAX_FABS_S, + AVR32_SYNTAX_FABS_D, + AVR32_SYNTAX_FCMP_S, + AVR32_SYNTAX_FCMP_D, + AVR32_SYNTAX_FMOV1_S, + AVR32_SYNTAX_FMOV1_D, + AVR32_SYNTAX_FMOV2_S, + AVR32_SYNTAX_FMOV2_D, + AVR32_SYNTAX_FMOV3_S, + AVR32_SYNTAX_FMOV3_D, + AVR32_SYNTAX_FCASTS_D, + AVR32_SYNTAX_FCASTD_S, + AVR32_SYNTAX_LDA_W, + AVR32_SYNTAX_CALL, + AVR32_SYNTAX__END_ +}; +#define AVR32_NR_SYNTAX AVR32_SYNTAX__END_ + +enum avr32_alias_type + { + AVR32_ALIAS_FMAC_S, + AVR32_ALIAS_FMAC_D, + AVR32_ALIAS_FNMAC_S, + AVR32_ALIAS_FNMAC_D, + AVR32_ALIAS_FMSC_S, + AVR32_ALIAS_FMSC_D, + AVR32_ALIAS_FNMSC_S, + AVR32_ALIAS_FNMSC_D, + AVR32_ALIAS_FADD_S, + AVR32_ALIAS_FADD_D, + AVR32_ALIAS_FSUB_S, + AVR32_ALIAS_FSUB_D, + AVR32_ALIAS_FMUL_S, + AVR32_ALIAS_FMUL_D, + AVR32_ALIAS_FNMUL_S, + AVR32_ALIAS_FNMUL_D, + AVR32_ALIAS_FNEG_S, + AVR32_ALIAS_FNEG_D, + AVR32_ALIAS_FABS_S, + AVR32_ALIAS_FABS_D, + AVR32_ALIAS_FCMP_S, + AVR32_ALIAS_FCMP_D, + AVR32_ALIAS_FMOV1_S, + AVR32_ALIAS_FMOV1_D, + AVR32_ALIAS_FMOV2_S, + AVR32_ALIAS_FMOV2_D, + AVR32_ALIAS_FMOV3_S, + AVR32_ALIAS_FMOV3_D, + AVR32_ALIAS_FCASTS_D, + AVR32_ALIAS_FCASTD_S, + AVR32_ALIAS__END_ + }; +#define AVR32_NR_ALIAS AVR32_ALIAS__END_ + +enum avr32_mnemonic_type +{ + AVR32_MNEMONIC_ABS, + AVR32_MNEMONIC_ACALL, + AVR32_MNEMONIC_ACR, + AVR32_MNEMONIC_ADC, + AVR32_MNEMONIC_ADD, + AVR32_MNEMONIC_ADDABS, + AVR32_MNEMONIC_ADDHH_W, + AVR32_MNEMONIC_AND, + AVR32_MNEMONIC_ANDH, + AVR32_MNEMONIC_ANDL, + AVR32_MNEMONIC_ANDN, + AVR32_MNEMONIC_ASR, + AVR32_MNEMONIC_BFEXTS, + AVR32_MNEMONIC_BFEXTU, + AVR32_MNEMONIC_BFINS, + AVR32_MNEMONIC_BLD, + AVR32_MNEMONIC_BREQ, + AVR32_MNEMONIC_BRNE, + AVR32_MNEMONIC_BRCC, + AVR32_MNEMONIC_BRCS, + AVR32_MNEMONIC_BRGE, + AVR32_MNEMONIC_BRLT, + AVR32_MNEMONIC_BRMI, + AVR32_MNEMONIC_BRPL, + AVR32_MNEMONIC_BRHS, + AVR32_MNEMONIC_BRLO, + AVR32_MNEMONIC_BRLS, + AVR32_MNEMONIC_BRGT, + AVR32_MNEMONIC_BRLE, + AVR32_MNEMONIC_BRHI, + AVR32_MNEMONIC_BRVS, + AVR32_MNEMONIC_BRVC, + AVR32_MNEMONIC_BRQS, + AVR32_MNEMONIC_BRAL, + AVR32_MNEMONIC_BREAKPOINT, + AVR32_MNEMONIC_BREV, + AVR32_MNEMONIC_BST, + AVR32_MNEMONIC_CACHE, + AVR32_MNEMONIC_CASTS_B, + AVR32_MNEMONIC_CASTS_H, + AVR32_MNEMONIC_CASTU_B, + AVR32_MNEMONIC_CASTU_H, + AVR32_MNEMONIC_CBR, + AVR32_MNEMONIC_CLZ, + AVR32_MNEMONIC_COM, + AVR32_MNEMONIC_COP, + AVR32_MNEMONIC_CP_B, + AVR32_MNEMONIC_CP_H, + AVR32_MNEMONIC_CP_W, + AVR32_MNEMONIC_CP, + AVR32_MNEMONIC_CPC, + AVR32_MNEMONIC_CSRF, + AVR32_MNEMONIC_CSRFCZ, + AVR32_MNEMONIC_DIVS, + AVR32_MNEMONIC_DIVU, + AVR32_MNEMONIC_EOR, + AVR32_MNEMONIC_EORL, + AVR32_MNEMONIC_EORH, + AVR32_MNEMONIC_FRS, + AVR32_MNEMONIC_ICALL, + AVR32_MNEMONIC_INCJOSP, + AVR32_MNEMONIC_LD_D, + AVR32_MNEMONIC_LD_SB, + AVR32_MNEMONIC_LD_UB, + AVR32_MNEMONIC_LD_SH, + AVR32_MNEMONIC_LD_UH, + AVR32_MNEMONIC_LD_W, + AVR32_MNEMONIC_LDC_D, + AVR32_MNEMONIC_LDC_W, + AVR32_MNEMONIC_LDC0_D, + AVR32_MNEMONIC_LDC0_W, + AVR32_MNEMONIC_LDCM_D, + AVR32_MNEMONIC_LDCM_W, + AVR32_MNEMONIC_LDDPC, + AVR32_MNEMONIC_LDDSP, + AVR32_MNEMONIC_LDINS_B, + AVR32_MNEMONIC_LDINS_H, + AVR32_MNEMONIC_LDM, + AVR32_MNEMONIC_LDMTS, + AVR32_MNEMONIC_LDSWP_SH, + AVR32_MNEMONIC_LDSWP_UH, + AVR32_MNEMONIC_LDSWP_W, + AVR32_MNEMONIC_LSL, + AVR32_MNEMONIC_LSR, + AVR32_MNEMONIC_MAC, + AVR32_MNEMONIC_MACHH_D, + AVR32_MNEMONIC_MACHH_W, + AVR32_MNEMONIC_MACS_D, + AVR32_MNEMONIC_MACSATHH_W, + AVR32_MNEMONIC_MACU_D, + AVR32_MNEMONIC_MACWH_D, + AVR32_MNEMONIC_MAX, + AVR32_MNEMONIC_MCALL, + AVR32_MNEMONIC_MFDR, + AVR32_MNEMONIC_MFSR, + AVR32_MNEMONIC_MIN, + AVR32_MNEMONIC_MOV, + AVR32_MNEMONIC_MOVEQ, + AVR32_MNEMONIC_MOVNE, + AVR32_MNEMONIC_MOVCC, + AVR32_MNEMONIC_MOVCS, + AVR32_MNEMONIC_MOVGE, + AVR32_MNEMONIC_MOVLT, + AVR32_MNEMONIC_MOVMI, + AVR32_MNEMONIC_MOVPL, + AVR32_MNEMONIC_MOVLS, + AVR32_MNEMONIC_MOVGT, + AVR32_MNEMONIC_MOVLE, + AVR32_MNEMONIC_MOVHI, + AVR32_MNEMONIC_MOVVS, + AVR32_MNEMONIC_MOVVC, + AVR32_MNEMONIC_MOVQS, + AVR32_MNEMONIC_MOVAL, + AVR32_MNEMONIC_MOVHS, + AVR32_MNEMONIC_MOVLO, + AVR32_MNEMONIC_MTDR, + AVR32_MNEMONIC_MTSR, + AVR32_MNEMONIC_MUL, + AVR32_MNEMONIC_MULHH_W, + AVR32_MNEMONIC_MULNHH_W, + AVR32_MNEMONIC_MULNWH_D, + AVR32_MNEMONIC_MULS_D, + AVR32_MNEMONIC_MULSATHH_H, + AVR32_MNEMONIC_MULSATHH_W, + AVR32_MNEMONIC_MULSATRNDHH_H, + AVR32_MNEMONIC_MULSATRNDWH_W, + AVR32_MNEMONIC_MULSATWH_W, + AVR32_MNEMONIC_MULU_D, + AVR32_MNEMONIC_MULWH_D, + AVR32_MNEMONIC_MUSFR, + AVR32_MNEMONIC_MUSTR, + AVR32_MNEMONIC_MVCR_D, + AVR32_MNEMONIC_MVCR_W, + AVR32_MNEMONIC_MVRC_D, + AVR32_MNEMONIC_MVRC_W, + AVR32_MNEMONIC_NEG, + AVR32_MNEMONIC_NOP, + AVR32_MNEMONIC_OR, + AVR32_MNEMONIC_ORH, + AVR32_MNEMONIC_ORL, + AVR32_MNEMONIC_PABS_SB, + AVR32_MNEMONIC_PABS_SH, + AVR32_MNEMONIC_PACKSH_SB, + AVR32_MNEMONIC_PACKSH_UB, + AVR32_MNEMONIC_PACKW_SH, + AVR32_MNEMONIC_PADD_B, + AVR32_MNEMONIC_PADD_H, + AVR32_MNEMONIC_PADDH_SH, + AVR32_MNEMONIC_PADDH_UB, + AVR32_MNEMONIC_PADDS_SB, + AVR32_MNEMONIC_PADDS_SH, + AVR32_MNEMONIC_PADDS_UB, + AVR32_MNEMONIC_PADDS_UH, + AVR32_MNEMONIC_PADDSUB_H, + AVR32_MNEMONIC_PADDSUBH_SH, + AVR32_MNEMONIC_PADDSUBS_SH, + AVR32_MNEMONIC_PADDSUBS_UH, + AVR32_MNEMONIC_PADDX_H, + AVR32_MNEMONIC_PADDXH_SH, + AVR32_MNEMONIC_PADDXS_SH, + AVR32_MNEMONIC_PADDXS_UH, + AVR32_MNEMONIC_PASR_B, + AVR32_MNEMONIC_PASR_H, + AVR32_MNEMONIC_PAVG_SH, + AVR32_MNEMONIC_PAVG_UB, + AVR32_MNEMONIC_PLSL_B, + AVR32_MNEMONIC_PLSL_H, + AVR32_MNEMONIC_PLSR_B, + AVR32_MNEMONIC_PLSR_H, + AVR32_MNEMONIC_PMAX_SH, + AVR32_MNEMONIC_PMAX_UB, + AVR32_MNEMONIC_PMIN_SH, + AVR32_MNEMONIC_PMIN_UB, + AVR32_MNEMONIC_POPJC, + AVR32_MNEMONIC_POPM, + AVR32_MNEMONIC_PREF, + AVR32_MNEMONIC_PSAD, + AVR32_MNEMONIC_PSUB_B, + AVR32_MNEMONIC_PSUB_H, + AVR32_MNEMONIC_PSUBADD_H, + AVR32_MNEMONIC_PSUBADDH_SH, + AVR32_MNEMONIC_PSUBADDS_SH, + AVR32_MNEMONIC_PSUBADDS_UH, + AVR32_MNEMONIC_PSUBH_SH, + AVR32_MNEMONIC_PSUBH_UB, + AVR32_MNEMONIC_PSUBS_SB, + AVR32_MNEMONIC_PSUBS_SH, + AVR32_MNEMONIC_PSUBS_UB, + AVR32_MNEMONIC_PSUBS_UH, + AVR32_MNEMONIC_PSUBX_H, + AVR32_MNEMONIC_PSUBXH_SH, + AVR32_MNEMONIC_PSUBXS_SH, + AVR32_MNEMONIC_PSUBXS_UH, + AVR32_MNEMONIC_PUNPCKSB_H, + AVR32_MNEMONIC_PUNPCKUB_H, + AVR32_MNEMONIC_PUSHJC, + AVR32_MNEMONIC_PUSHM, + AVR32_MNEMONIC_RCALL, + AVR32_MNEMONIC_RETEQ, + AVR32_MNEMONIC_RETNE, + AVR32_MNEMONIC_RETCC, + AVR32_MNEMONIC_RETCS, + AVR32_MNEMONIC_RETGE, + AVR32_MNEMONIC_RETLT, + AVR32_MNEMONIC_RETMI, + AVR32_MNEMONIC_RETPL, + AVR32_MNEMONIC_RETLS, + AVR32_MNEMONIC_RETGT, + AVR32_MNEMONIC_RETLE, + AVR32_MNEMONIC_RETHI, + AVR32_MNEMONIC_RETVS, + AVR32_MNEMONIC_RETVC, + AVR32_MNEMONIC_RETQS, + AVR32_MNEMONIC_RETAL, + AVR32_MNEMONIC_RETHS, + AVR32_MNEMONIC_RETLO, + AVR32_MNEMONIC_RET, + AVR32_MNEMONIC_RETD, + AVR32_MNEMONIC_RETE, + AVR32_MNEMONIC_RETJ, + AVR32_MNEMONIC_RETS, + AVR32_MNEMONIC_RJMP, + AVR32_MNEMONIC_ROL, + AVR32_MNEMONIC_ROR, + AVR32_MNEMONIC_RSUB, + AVR32_MNEMONIC_SATADD_H, + AVR32_MNEMONIC_SATADD_W, + AVR32_MNEMONIC_SATRNDS, + AVR32_MNEMONIC_SATRNDU, + AVR32_MNEMONIC_SATS, + AVR32_MNEMONIC_SATSUB_H, + AVR32_MNEMONIC_SATSUB_W, + AVR32_MNEMONIC_SATU, + AVR32_MNEMONIC_SBC, + AVR32_MNEMONIC_SBR, + AVR32_MNEMONIC_SCALL, + AVR32_MNEMONIC_SCR, + AVR32_MNEMONIC_SLEEP, + AVR32_MNEMONIC_SREQ, + AVR32_MNEMONIC_SRNE, + AVR32_MNEMONIC_SRCC, + AVR32_MNEMONIC_SRCS, + AVR32_MNEMONIC_SRGE, + AVR32_MNEMONIC_SRLT, + AVR32_MNEMONIC_SRMI, + AVR32_MNEMONIC_SRPL, + AVR32_MNEMONIC_SRLS, + AVR32_MNEMONIC_SRGT, + AVR32_MNEMONIC_SRLE, + AVR32_MNEMONIC_SRHI, + AVR32_MNEMONIC_SRVS, + AVR32_MNEMONIC_SRVC, + AVR32_MNEMONIC_SRQS, + AVR32_MNEMONIC_SRAL, + AVR32_MNEMONIC_SRHS, + AVR32_MNEMONIC_SRLO, + AVR32_MNEMONIC_SSRF, + AVR32_MNEMONIC_ST_B, + AVR32_MNEMONIC_ST_D, + AVR32_MNEMONIC_ST_H, + AVR32_MNEMONIC_ST_W, + AVR32_MNEMONIC_STC_D, + AVR32_MNEMONIC_STC_W, + AVR32_MNEMONIC_STC0_D, + AVR32_MNEMONIC_STC0_W, + AVR32_MNEMONIC_STCM_D, + AVR32_MNEMONIC_STCM_W, + AVR32_MNEMONIC_STCOND, + AVR32_MNEMONIC_STDSP, + AVR32_MNEMONIC_STHH_W, + AVR32_MNEMONIC_STM, + AVR32_MNEMONIC_STMTS, + AVR32_MNEMONIC_STSWP_H, + AVR32_MNEMONIC_STSWP_W, + AVR32_MNEMONIC_SUB, + AVR32_MNEMONIC_SUBEQ, + AVR32_MNEMONIC_SUBNE, + AVR32_MNEMONIC_SUBCC, + AVR32_MNEMONIC_SUBCS, + AVR32_MNEMONIC_SUBGE, + AVR32_MNEMONIC_SUBLT, + AVR32_MNEMONIC_SUBMI, + AVR32_MNEMONIC_SUBPL, + AVR32_MNEMONIC_SUBLS, + AVR32_MNEMONIC_SUBGT, + AVR32_MNEMONIC_SUBLE, + AVR32_MNEMONIC_SUBHI, + AVR32_MNEMONIC_SUBVS, + AVR32_MNEMONIC_SUBVC, + AVR32_MNEMONIC_SUBQS, + AVR32_MNEMONIC_SUBAL, + AVR32_MNEMONIC_SUBHS, + AVR32_MNEMONIC_SUBLO, + AVR32_MNEMONIC_SUBFEQ, + AVR32_MNEMONIC_SUBFNE, + AVR32_MNEMONIC_SUBFCC, + AVR32_MNEMONIC_SUBFCS, + AVR32_MNEMONIC_SUBFGE, + AVR32_MNEMONIC_SUBFLT, + AVR32_MNEMONIC_SUBFMI, + AVR32_MNEMONIC_SUBFPL, + AVR32_MNEMONIC_SUBFLS, + AVR32_MNEMONIC_SUBFGT, + AVR32_MNEMONIC_SUBFLE, + AVR32_MNEMONIC_SUBFHI, + AVR32_MNEMONIC_SUBFVS, + AVR32_MNEMONIC_SUBFVC, + AVR32_MNEMONIC_SUBFQS, + AVR32_MNEMONIC_SUBFAL, + AVR32_MNEMONIC_SUBFHS, + AVR32_MNEMONIC_SUBFLO, + AVR32_MNEMONIC_SUBHH_W, + AVR32_MNEMONIC_SWAP_B, + AVR32_MNEMONIC_SWAP_BH, + AVR32_MNEMONIC_SWAP_H, + AVR32_MNEMONIC_SYNC, + AVR32_MNEMONIC_TLBR, + AVR32_MNEMONIC_TLBS, + AVR32_MNEMONIC_TLBW, + AVR32_MNEMONIC_TNBZ, + AVR32_MNEMONIC_TST, + AVR32_MNEMONIC_XCHG, + AVR32_MNEMONIC_MEMC, + AVR32_MNEMONIC_MEMS, + AVR32_MNEMONIC_MEMT, + AVR32_MNEMONIC_FADD_S, + AVR32_MNEMONIC_FADD_D, + AVR32_MNEMONIC_FSUB_S, + AVR32_MNEMONIC_FSUB_D, + AVR32_MNEMONIC_FMAC_S, + AVR32_MNEMONIC_FMAC_D, + AVR32_MNEMONIC_FNMAC_S, + AVR32_MNEMONIC_FNMAC_D, + AVR32_MNEMONIC_FMSC_S, + AVR32_MNEMONIC_FMSC_D, + AVR32_MNEMONIC_FNMSC_S, + AVR32_MNEMONIC_FNMSC_D, + AVR32_MNEMONIC_FMUL_S, + AVR32_MNEMONIC_FMUL_D, + AVR32_MNEMONIC_FNMUL_S, + AVR32_MNEMONIC_FNMUL_D, + AVR32_MNEMONIC_FNEG_S, + AVR32_MNEMONIC_FNEG_D, + AVR32_MNEMONIC_FABS_S, + AVR32_MNEMONIC_FABS_D, + AVR32_MNEMONIC_FCMP_S, + AVR32_MNEMONIC_FCMP_D, + AVR32_MNEMONIC_FMOV_S, + AVR32_MNEMONIC_FMOV_D, + AVR32_MNEMONIC_FCASTS_D, + AVR32_MNEMONIC_FCASTD_S, + /* AVR32_MNEMONIC_FLD_S, + AVR32_MNEMONIC_FLD_D, + AVR32_MNEMONIC_FST_S, + AVR32_MNEMONIC_FST_D, */ + AVR32_MNEMONIC_LDA_W, + AVR32_MNEMONIC_CALL, + AVR32_MNEMONIC__END_ +}; +#define AVR32_NR_MNEMONICS AVR32_MNEMONIC__END_ + +enum avr32_syntax_parser + { + AVR32_PARSER_NORMAL, + AVR32_PARSER_ALIAS, + AVR32_PARSER_LDA, + AVR32_PARSER_CALL, + AVR32_PARSER__END_ + }; +#define AVR32_NR_PARSERS AVR32_PARSER__END_ Index: binutils-2.16.1-avr32/opcodes/configure.in =================================================================== --- binutils-2.16.1-avr32.orig/opcodes/configure.in 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/opcodes/configure.in 2006-06-30 09:49:14.000000000 +0200 @@ -176,6 +176,7 @@ if test x${all_targets} = xfalse ; then bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; bfd_arm_arch) ta="$ta arm-dis.lo" ;; bfd_avr_arch) ta="$ta avr-dis.lo" ;; + bfd_avr32_arch) ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;; bfd_convex_arch) ;; bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo" ;; bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; Index: binutils-2.16.1-avr32/opcodes/disassemble.c =================================================================== --- binutils-2.16.1-avr32.orig/opcodes/disassemble.c 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/opcodes/disassemble.c 2006-06-30 09:49:14.000000000 +0200 @@ -25,6 +25,7 @@ #define ARCH_arc #define ARCH_arm #define ARCH_avr +#define ARCH_avr32 #define ARCH_cris #define ARCH_crx #define ARCH_d10v @@ -120,6 +121,11 @@ disassembler (abfd) disassemble = print_insn_avr; break; #endif +#ifdef ARCH_avr32 + case bfd_arch_avr32: + disassemble = print_insn_avr32; + break; +#endif #ifdef ARCH_cris case bfd_arch_cris: disassemble = cris_get_disassembler (abfd); @@ -407,6 +413,9 @@ disassembler_usage (stream) #ifdef ARCH_powerpc print_ppc_disassembler_options (stream); #endif +#ifdef ARCH_avr32 + print_avr32_disassembler_options (stream); +#endif return; } Index: binutils-2.16.1-avr32/binutils/Makefile.am =================================================================== --- binutils-2.16.1-avr32.orig/binutils/Makefile.am 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/binutils/Makefile.am 2006-06-30 09:49:14.000000000 +0200 @@ -466,7 +466,7 @@ readelf.o: readelf.c ../bfd/bfd.h $(INCD $(INCDIR)/symcat.h $(INCDIR)/elf/common.h $(INCDIR)/elf/external.h \ $(INCDIR)/elf/internal.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/alpha.h \ $(INCDIR)/elf/reloc-macros.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/arm.h \ - $(INCDIR)/elf/avr.h $(INCDIR)/elf/cris.h $(INCDIR)/elf/d10v.h \ + $(INCDIR)/elf/avr.h $(INCDIR)/elf/avr32.h $(INCDIR)/elf/cris.h $(INCDIR)/elf/d10v.h \ $(INCDIR)/elf/d30v.h $(INCDIR)/elf/dlx.h $(INCDIR)/elf/fr30.h \ $(INCDIR)/elf/frv.h $(INCDIR)/elf/h8.h $(INCDIR)/elf/hppa.h \ $(INCDIR)/elf/i386.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/i860.h \ Index: binutils-2.16.1-avr32/binutils/readelf.c =================================================================== --- binutils-2.16.1-avr32.orig/binutils/readelf.c 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/binutils/readelf.c 2006-06-30 09:49:14.000000000 +0200 @@ -72,6 +72,7 @@ #include "elf/arc.h" #include "elf/arm.h" #include "elf/avr.h" +#include "elf/avr32.h" #include "elf/cris.h" #include "elf/d10v.h" #include "elf/d30v.h" @@ -711,6 +712,7 @@ guess_is_rela (unsigned long e_machine) case EM_MCORE: case EM_IA_64: case EM_AVR: + case EM_AVR32: case EM_AVR_OLD: case EM_CRIS: case EM_860: @@ -1071,6 +1073,10 @@ dump_relocations (FILE *file, rtype = elf_avr_reloc_type (type); break; + case EM_AVR32: + rtype = elf_avr32_reloc_type (type); + break; + case EM_OLD_SPARCV9: case EM_SPARC32PLUS: case EM_SPARCV9: @@ -1700,6 +1706,7 @@ get_machine_name (unsigned e_machine) case EM_VAX: return "Digital VAX"; case EM_AVR_OLD: case EM_AVR: return "Atmel AVR 8-bit microcontroller"; + case EM_AVR32: return "Atmel AVR32"; case EM_CRIS: return "Axis Communications 32-bit embedded processor"; case EM_JAVELIN: return "Infineon Technologies 32-bit embedded cpu"; case EM_FIREPATH: return "Element 14 64-bit DSP processor"; Index: binutils-2.16.1-avr32/gas/Makefile.am =================================================================== --- binutils-2.16.1-avr32.orig/gas/Makefile.am 2006-06-30 09:49:11.000000000 +0200 +++ binutils-2.16.1-avr32/gas/Makefile.am 2006-06-30 09:49:14.000000000 +0200 @@ -45,6 +45,7 @@ CPU_TYPES = \ arc \ arm \ avr \ + avr32 \ cris \ crx \ d10v \ @@ -243,6 +244,7 @@ TARGET_CPU_CFILES = \ config/tc-arc.c \ config/tc-arm.c \ config/tc-avr.c \ + config/tc-avr32.c \ config/tc-cris.c \ config/tc-crx.c \ config/tc-d10v.c \ @@ -296,6 +298,7 @@ TARGET_CPU_HFILES = \ config/tc-arc.h \ config/tc-arm.h \ config/tc-avr.h \ + config/tc-avr32.h \ config/tc-cris.h \ config/tc-crx.h \ config/tc-d10v.h \ @@ -1048,6 +1051,11 @@ DEPTC_avr_elf = $(INCDIR)/symcat.h $(src $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ $(INCDIR)/opcode/avr.h +DEPTC_avr32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr32.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ + $(srcdir)/../opcodes/avr32-opc.h $(srcdir)/../opcodes/avr32-asm.h DEPTC_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \ $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ @@ -1635,6 +1643,11 @@ DEPOBJ_avr_elf = $(INCDIR)/symcat.h $(sr $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h +DEPOBJ_avr32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr32.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ + struc-symbol.h dwarf2dbg.h DEPOBJ_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \ $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \ $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h @@ -2135,6 +2148,9 @@ DEP_avr_coff = $(srcdir)/config/obj-coff DEP_avr_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h +DEP_avr32_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr32.h DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \ $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h DEP_cris_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ Index: binutils-2.16.1-avr32/gas/config/tc-avr32.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/gas/config/tc-avr32.c 2006-07-06 13:03:09.000000000 +0200 @@ -0,0 +1,4446 @@ +/* Assembler implementation for AVR32. + Copyright 2003-2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include "as.h" +#include "safe-ctype.h" +#include "subsegs.h" +#include "symcat.h" +#include "opcodes/avr32-opc.h" +#include "opcodes/avr32-asm.h" +#include "elf/avr32.h" +#include "dwarf2dbg.h" + +#define xDEBUG +#define xOPC_CONSISTENCY_CHECK + +#ifdef DEBUG +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args) +#else +# define pr_debug(fmt, args...) +#endif + +/* 3 MSB of instruction word indicate group. Group 7 -> extended */ +#define AVR32_COMPACT_P(opcode) ((opcode[0] & 0xe0) != 0xe0) + +#define streq(a, b) (strcmp(a, b) == 0) +#define skip_whitespace(str) do { while(*(str) == ' ') ++(str); } while(0) + +/* Flags given on the command line */ +static int avr32_pic = FALSE; +int linkrelax = FALSE; +int avr32_iarcompat = FALSE; + +/* This array holds the chars that always start a comment. */ +const char comment_chars[] = "#"; + +/* This array holds the chars that only start a comment at the + beginning of a line. We must include '#' here because the compiler + may produce #APP and #NO_APP in its output. */ +const char line_comment_chars[] = "#"; + +/* These may be used instead of newline (same as ';' in C). */ +const char line_separator_chars[] = ";"; + +/* Chars that can be used to separate mantissa from exponent in + floating point numbers. */ +const char EXP_CHARS[] = "eE"; + +/* Chars that mean this number is a floating point constant. */ +const char FLT_CHARS[] = "dD"; + +/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ +symbolS *GOT_symbol; + +static struct hash_control *avr32_mnemonic_htab; + +struct avr32_ifield_data +{ + bfd_vma value; + /* FIXME: Get rid of align_order and complain. complain is never + used, align_order is used in one place. Try to use the relax + table instead. */ + unsigned int align_order; +}; + +struct avr32_insn +{ + const struct avr32_syntax *syntax; + expressionS immediate; + int pcrel; + int force_extended; + unsigned int next_slot; + bfd_reloc_code_real_type r_type; + struct avr32_ifield_data field_value[AVR32_MAX_FIELDS]; +}; + +static struct avr32_insn current_insn; + +/* The target specific pseudo-ops we support. */ +static void s_rseg (int); +static void s_cpool(int); + +const pseudo_typeS md_pseudo_table[] = +{ + /* Make sure that .word is 32 bits */ + { "word", cons, 4 }, + { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 }, + { "loc", dwarf2_directive_loc, 0 }, + + /* .lcomm requires an explicit alignment parameter */ + { "lcomm", s_lcomm, 1 }, + + /* AVR32-specific pseudo-ops */ + { "cpool", s_cpool, 0}, + + /* IAR compatible pseudo-ops */ + { "program", s_ignore, 0 }, + { "public", s_globl, 0 }, + { "extern", s_ignore, 0 }, + { "module", s_ignore, 0 }, + { "rseg", s_rseg, 0 }, + { "dc8", cons, 1 }, + { "dc16", cons, 2 }, + { "dc32", cons, 4 }, + + { NULL, NULL, 0 } +}; + +/* Questionable stuff starts here */ + +enum avr32_opinfo { + AVR32_OPINFO_NONE = BFD_RELOC_NONE, + AVR32_OPINFO_GOT, + AVR32_OPINFO_TLSGD, + AVR32_OPINFO_HI, + AVR32_OPINFO_LO, +}; + +struct cpu_type_s +{ + /* CPU name */ + char *name; + /* Instruction Set Architecture Flags */ + unsigned long isa_flags; +}; + + +static struct cpu_type_s cpu_types[] = +{ + {"ap7000", AVR32_V1 | AVR32_SIMD | AVR32_DSP}, + {"all-insn", AVR32_V1 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_FP}, + {NULL, 0} +}; + +/* Current CPU type. */ +static struct cpu_type_s default_cpu = {"all-insn", AVR32_V1 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_FP}; +static struct cpu_type_s *avr32_cpu = &default_cpu; + +/* Display nicely formatted list of known CPU names. */ + +static void +show_cpu_list (FILE *stream) +{ + int i, x; + + fprintf (stream, _("Known CPU names:")); + x = 1000; + + for (i = 0; cpu_types[i].name; i++) + { + int len = strlen (cpu_types[i].name); + + x += len + 1; + + if (x < 75) + fprintf (stream, " %s", cpu_types[i].name); + else + { + fprintf (stream, "\n %s", cpu_types[i].name); + x = len + 2; + } + } + + fprintf (stream, "\n"); +} + +const char *md_shortopts = ""; +struct option md_longopts[] = +{ +#define OPTION_CPU 'c' +#define OPTION_IAR (OPTION_MD_BASE + 1) +#define OPTION_PIC (OPTION_IAR + 1) +#define OPTION_NOPIC (OPTION_PIC + 1) +#define OPTION_LINKRELAX (OPTION_NOPIC + 1) +#define OPTION_NOLINKRELAX (OPTION_LINKRELAX + 1) + {"mcpu", required_argument, NULL, OPTION_CPU}, + {"iar", no_argument, NULL, OPTION_IAR}, + {"pic", no_argument, NULL, OPTION_PIC}, + {"no-pic", no_argument, NULL, OPTION_NOPIC}, + {"linkrelax", no_argument, NULL, OPTION_LINKRELAX}, + {"no-linkrelax", no_argument, NULL, OPTION_NOLINKRELAX}, + {NULL, no_argument, NULL, 0} +}; + +size_t md_longopts_size = sizeof (md_longopts); + +void +md_show_usage (FILE *stream) +{ + fprintf (stream, + _( +"AVR32 options:\n" +"-mcpu=[cpu-name] Select cpu name. [Default `all-insn']\n" +"--pic Produce Position-Independent Code\n" +"--no-pic Don't produce Position-Independent Code\n" +"--linkrelax Produce output suitable for linker relaxing\n" +"--no-linkrelax Don't produce output suitable for linker relaxing\n")); + show_cpu_list(stream); +} + +int +md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) +{ + switch (c) + { + case OPTION_CPU: + { + int i; + char *s = alloca (strlen (arg) + 1); + + { + char *t = s; + char *arg1 = arg; + + do + *t = TOLOWER (*arg1++); + while (*t++); + } + + for (i = 0; cpu_types[i].name; ++i) + if (strcmp (cpu_types[i].name, s) == 0) + break; + + if (!cpu_types[i].name) + { + show_cpu_list (stderr); + as_fatal (_("unknown CPU: %s\n"), arg); + } + + avr32_cpu = &cpu_types[i]; + } + case OPTION_IAR: + avr32_iarcompat = 1; + break; + case OPTION_PIC: + avr32_pic = 1; + break; + case OPTION_NOPIC: + avr32_pic = 0; + break; + case OPTION_LINKRELAX: + linkrelax = 1; + break; + case OPTION_NOLINKRELAX: + linkrelax = 0; + break; + default: + return 0; + } + return 1; +} + +/* Can't use symbol_new here, so have to create a symbol and then at + a later date assign it a value. Thats what these functions do. + + Shamelessly stolen from ARM. */ + +static void +symbol_locate (symbolS * symbolP, + const char * name, /* It is copied, the caller can modify. */ + segT segment, /* Segment identifier (SEG_). */ + valueT valu, /* Symbol value. */ + fragS * frag) /* Associated fragment. */ +{ + unsigned int name_length; + char * preserved_copy_of_name; + + name_length = strlen (name) + 1; /* +1 for \0. */ + obstack_grow (¬es, name, name_length); + preserved_copy_of_name = obstack_finish (¬es); +#ifdef STRIP_UNDERSCORE + if (preserved_copy_of_name[0] == '_') + preserved_copy_of_name++; +#endif + +#ifdef tc_canonicalize_symbol_name + preserved_copy_of_name = + tc_canonicalize_symbol_name (preserved_copy_of_name); +#endif + + S_SET_NAME (symbolP, preserved_copy_of_name); + + S_SET_SEGMENT (symbolP, segment); + S_SET_VALUE (symbolP, valu); + symbol_clear_list_pointers (symbolP); + + symbol_set_frag (symbolP, frag); + + /* Link to end of symbol chain. */ + { + extern int symbol_table_frozen; + + if (symbol_table_frozen) + abort (); + } + + symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); + + obj_symbol_new_hook (symbolP); + +#ifdef tc_symbol_new_hook + tc_symbol_new_hook (symbolP); +#endif + +#ifdef DEBUG_SYMS + verify_symbol_chain (symbol_rootP, symbol_lastP); +#endif /* DEBUG_SYMS */ +} + +struct cpool_entry +{ + int refcount; + offsetT offset; + expressionS exp; +}; + +struct cpool +{ + struct cpool *next; + int used; + struct cpool_entry *literals; + unsigned int padding; + unsigned int next_free_entry; + unsigned int id; + symbolS *symbol; + segT section; + subsegT sub_section; +}; + +struct cpool *cpool_list = NULL; + +static struct cpool * +find_cpool(segT section, subsegT sub_section) +{ + struct cpool *pool; + + for (pool = cpool_list; pool != NULL; pool = pool->next) + { + if (!pool->used + && pool->section == section + && pool->sub_section == sub_section) + break; + } + + return pool; +} + +static struct cpool * +find_or_make_cpool(segT section, subsegT sub_section) +{ + static unsigned int next_cpool_id = 0; + struct cpool *pool; + + pool = find_cpool(section, sub_section); + + if (!pool) + { + pool = xmalloc(sizeof(*pool)); + if (!pool) + return NULL; + + pool->used = 0; + pool->literals = NULL; + pool->padding = 0; + pool->next_free_entry = 0; + pool->section = section; + pool->sub_section = sub_section; + pool->next = cpool_list; + pool->symbol = NULL; + + cpool_list = pool; + } + + /* NULL symbol means that the pool is new or has just been emptied. */ + if (!pool->symbol) + { + pool->symbol = symbol_create(FAKE_LABEL_NAME, undefined_section, + 0, &zero_address_frag); + pool->id = next_cpool_id++; + } + + return pool; +} + +static struct cpool * +add_to_cpool(expressionS *exp, unsigned int *index, int ref) +{ + struct cpool *pool; + unsigned int entry; + + pool = find_or_make_cpool(now_seg, now_subseg); + + /* Check if this constant is already in the pool. */ + for (entry = 0; entry < pool->next_free_entry; entry++) + { + if ((pool->literals[entry].exp.X_op == exp->X_op) + && (exp->X_op == O_constant) + && (pool->literals[entry].exp.X_add_number + == exp->X_add_number) + && (pool->literals[entry].exp.X_unsigned + == exp->X_unsigned)) + break; + + if ((pool->literals[entry].exp.X_op == exp->X_op) + && (exp->X_op == O_symbol) + && (pool->literals[entry].exp.X_add_number + == exp->X_add_number) + && (pool->literals[entry].exp.X_add_symbol + == exp->X_add_symbol) + && (pool->literals[entry].exp.X_op_symbol + == exp->X_op_symbol)) + break; + } + + /* Create an entry if we didn't find a match */ + if (entry == pool->next_free_entry) + { + pool->literals = xrealloc(pool->literals, + sizeof(struct cpool_entry) * (entry + 1)); + pool->literals[entry].exp = *exp; + pool->literals[entry].refcount = 0; + pool->next_free_entry++; + } + + if (index) + *index = entry; + if (ref) + pool->literals[entry].refcount++; + + return pool; +} + +struct avr32_operand +{ + int id; + int is_signed; + int is_pcrel; + int align_order; + int (*match)(char *str); + void (*parse)(const struct avr32_operand *op, char *str, int opindex); +}; + +static int +match_anything(char *str ATTRIBUTE_UNUSED) +{ + return 1; +} + +static int +match_intreg(char *str) +{ + int regid, ret = 1; + + regid = avr32_parse_intreg(str); + if (regid < 0) + ret = 0; + + pr_debug("match_intreg: `%s': %d\n", str, ret); + + return ret; +} + +static int +match_intreg_predec(char *str) +{ + int regid; + + if (str[0] != '-' || str[1] != '-') + return 0; + + regid = avr32_parse_intreg(str + 2); + if (regid < 0) + return 0; + + return 1; +} + +static int +match_intreg_postinc(char *str) +{ + int regid, ret = 1; + char *p, c; + + for (p = str; *p; p++) + if (*p == '+') + break; + + if (p[0] != '+' || p[1] != '+') + return 0; + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + if (regid < 0) + ret = 0; + + *p = c; + return ret; +} + +static int +match_intreg_lsl(char *str) +{ + int regid, ret = 1; + char *p, c; + + for (p = str; *p; p++) + if (*p == '<') + break; + + if (p[0] && p[1] != '<') + return 0; + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + if (regid < 0) + ret = 0; + + *p = c; + return ret; +} + +static int +match_intreg_lsr(char *str) +{ + int regid, ret = 1; + char *p, c; + + for (p = str; *p; p++) + if (*p == '>') + break; + + if (p[0] && p[1] != '>') + return 0; + + c = *p, *p = 0; + + regid = avr32_parse_intreg(str); + if (regid < 0) + ret = 0; + + *p = c; + return ret; +} + +static int +match_intreg_part(char *str) +{ + int regid, ret = 1; + char *p, c; + + for (p = str; *p; p++) + if (*p == ':') + break; + + if (p[0] != ':' || !ISPRINT(p[1]) || p[2] != '\0') + return 0; + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + if (regid < 0) + ret = 0; + + *p = c; + + return ret; +} + +#define match_intreg_disp match_anything + +static int +match_intreg_index(char *str) +{ + int regid, ret = 1; + char *p, *end, c; + + for (p = str; *p; p++) + if (*p == '[') + break; + + /* don't allow empty displacement here (it makes no sense) */ + if (p[0] != '[') + return 0; + + for (end = p + 1; *end; end++) ; + if (*(--end) != ']') + return 0; + + c = *end, *end = 0; + if (!match_intreg_lsl(p + 1)) + ret = 0; + *end = c; + + if (ret) + { + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + if (regid < 0) + ret = 0; + *p = c; + } + + return ret; +} + +static int +match_intreg_xindex(char *str) +{ + int regid, ret = 1; + char *p, *end, c; + + for (p = str; *p; p++) + if (*p == '[') + break; + + /* empty displacement makes no sense here either */ + if (p[0] != '[') + return 0; + + for (end = p + 1; *end; end++) + if (*end == '<') + break; + + if (!streq(end, "<<2]")) + return 0; + + c = *end, *end = 0; + if (!match_intreg_part(p + 1)) + ret = 0; + *end = c; + + if (ret) + { + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + if (regid < 0) + ret = 0; + *p = c; + } + + return ret; +} + +/* The PC_UDISP_W operator may show up as a label or as a pc[disp] + expression. So there's no point in attempting to match this... */ +#define match_pc_disp match_anything + +static int +match_sp(char *str) +{ + /* SP in any form will do */ + return avr32_parse_intreg(str) == AVR32_REG_SP; +} + +static int +match_sp_disp(char *str) +{ + int regid, ret = 1; + char *p, c; + + for (p = str; *p; p++) + if (*p == '[') + break; + + /* allow empty displacement, meaning zero */ + if (p[0] == '[') + { + char *end; + for (end = p + 1; *end; end++) ; + if (end[-1] != ']') + return 0; + } + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + if (regid != AVR32_REG_SP) + ret = 0; + + *p = c; + return ret; +} + +static int +match_cpno(char *str) +{ + if (strncasecmp(str, "cp", 2) != 0) + return 0; + return 1; +} + +static int +match_cpreg(char *str) +{ + if (strncasecmp(str, "cr", 2) != 0) + return 0; + return 1; +} + +/* We allow complex expressions, and register names may show up as + symbols. Just make sure immediate expressions are always matched + last. */ +#define match_const match_anything +#define match_jmplabel match_anything +#define match_number match_anything + +/* Mnemonics that take reglists never accept anything else */ +#define match_reglist8 match_anything +#define match_reglist9 match_anything +#define match_reglist16 match_anything +#define match_reglist_ldm match_anything +#define match_reglist_cp8 match_anything +#define match_reglist_cpd8 match_anything + +/* Ditto for retval, jospinc and mcall */ +#define match_retval match_anything +#define match_jospinc match_anything +#define match_mcall match_anything + +/* COH is used to select between two different syntaxes */ +static int +match_coh(char *str) +{ + return strcasecmp(str, "coh") == 0; +} + +static int +match_fpreg(char *str) +{ + unsigned long regid; + char *endptr; + + if ((str[0] != 'f' && str[0] != 'F') + || (str[1] != 'r' && str[1] != 'R')) + return 0; + + str += 2; + regid = strtoul(str, &endptr, 10); + if (!*str || *endptr) + return 0; + + return 1; +} + +static void parse_nothing(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str ATTRIBUTE_UNUSED, + int opindex ATTRIBUTE_UNUSED) +{ + /* Do nothing (this is used for "match-only" operands like COH) */ +} + +static void +parse_const(const struct avr32_operand *op, char *str, + int opindex ATTRIBUTE_UNUSED) +{ + expressionS *exp = ¤t_insn.immediate; + expressionS *sym_exp; + int slot; + char *save; + + pr_debug("parse_const: `%s' (signed: %d, pcrel: %d, align: %d)\n", + str, op->is_signed, op->is_pcrel, op->align_order); + + save = input_line_pointer; + input_line_pointer = str; + + expression(exp); + + slot = current_insn.next_slot++; + current_insn.field_value[slot].align_order = op->align_order; + current_insn.pcrel = op->is_pcrel; + + switch (exp->X_op) + { + case O_illegal: + as_bad(_("illegal operand")); + break; + case O_absent: + as_bad(_("missing operand")); + break; + case O_constant: + pr_debug(" -> constant: %ld\n", (long)exp->X_add_number); + current_insn.field_value[slot].value = exp->X_add_number; + break; + case O_uminus: + pr_debug(" -> uminus\n"); + sym_exp = symbol_get_value_expression(exp->X_add_symbol); + switch (sym_exp->X_op) { + case O_subtract: + pr_debug(" -> subtract: switching operands\n"); + exp->X_op_symbol = sym_exp->X_add_symbol; + exp->X_add_symbol = sym_exp->X_op_symbol; + exp->X_op = O_subtract; + /* TODO: Remove the old X_add_symbol */ + break; + default: + as_bad(_("Expression too complex\n")); + break; + } + break; +#if 0 + case O_subtract: + /* Any expression subtracting a symbol from the current section + can be made PC-relative by adding the right offset. */ + if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg) + current_insn.pcrel = TRUE; + pr_debug(" -> subtract: pcrel? %s\n", + current_insn.pcrel ? "yes" : "no"); + /* fall through */ +#endif + default: + pr_debug(" -> (%p <%d> %p + %d)\n", + exp->X_add_symbol, exp->X_op, exp->X_op_symbol, + exp->X_add_number); + current_insn.field_value[slot].value = 0; + break; + } + + input_line_pointer = save; +} + +static void +parse_jmplabel(const struct avr32_operand *op, char *str, + int opindex ATTRIBUTE_UNUSED) +{ + expressionS *exp = ¤t_insn.immediate; + int slot; + char *save; + + pr_debug("parse_jmplabel: `%s' (signed: %d, pcrel: %d, align: %d)\n", + str, op->is_signed, op->is_pcrel, op->align_order); + + save = input_line_pointer; + input_line_pointer = str; + + expression(exp); + + slot = current_insn.next_slot++; + current_insn.field_value[slot].align_order = op->align_order; + current_insn.pcrel = TRUE; + + switch (exp->X_op) + { + case O_illegal: + as_bad(_("illegal operand")); + break; + case O_absent: + as_bad(_("missing operand")); + break; + case O_constant: + pr_debug(" -> constant: %ld\n", (long)exp->X_add_number); + current_insn.field_value[slot].value = exp->X_add_number; + current_insn.pcrel = 0; + break; + default: + pr_debug(" -> (%p <%d> %p + %d)\n", + exp->X_add_symbol, exp->X_op, exp->X_op_symbol, + exp->X_add_number); + current_insn.field_value[slot].value = 0; + break; + } + + input_line_pointer = save; +} + +static void +parse_intreg(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + int regid, slot; + + pr_debug("parse_intreg: `%s'\n", str); + + regid = avr32_parse_intreg(str); + assert(regid >= 0); + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regid; + current_insn.field_value[slot].align_order = op->align_order; +} + +static void +parse_intreg_predec(const struct avr32_operand *op, char *str, int opindex) +{ + parse_intreg(op, str + 2, opindex); +} + +static void +parse_intreg_postinc(const struct avr32_operand *op, char *str, int opindex) +{ + char *p, c; + + pr_debug("parse_intreg_postinc: `%s'\n", str); + + for (p = str; *p != '+'; p++) ; + + c = *p, *p = 0; + parse_intreg(op, str, opindex); + *p = c; +} + +static void +parse_intreg_shift(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + int regid, slot, shift = 0; + char *p, c; + char shiftop; + + pr_debug("parse Ry<') + break; + + shiftop = *p; + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + assert(regid >= 0); + *p = c; + + if (c) + { + if (p[0] != shiftop || p[1] != shiftop) + as_bad(_("expected shift operator in `%s'"), p); + else + { + expressionS exp; + char *saved; + + saved = input_line_pointer; + input_line_pointer = p + 2; + expression(&exp); + input_line_pointer = saved; + + if (exp.X_op != O_constant) + as_bad(_("shift amount must be a numeric constant")); + else + shift = exp.X_add_number; + } + } + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regid; + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = shift; +} + +/* The match() function selected the right opcode, so it doesn't + matter which way we shift any more. */ +#define parse_intreg_lsl parse_intreg_shift +#define parse_intreg_lsr parse_intreg_shift + +static void +parse_intreg_part(const struct avr32_operand *op, char *str, + int opindex ATTRIBUTE_UNUSED) +{ + static const char bparts[] = { 'b', 'l', 'u', 't' }; + static const char hparts[] = { 'b', 't' }; + unsigned int slot, sel; + int regid; + char *p, c; + + pr_debug("parse reg:part `%s'\n", str); + + for (p = str; *p; p++) + if (*p == ':') + break; + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + assert(regid >= 0); + *p = c; + + assert(c == ':'); + + if (op->align_order) + { + for (sel = 0; sel < sizeof(hparts); sel++) + if (TOLOWER(p[1]) == hparts[sel]) + break; + + if (sel >= sizeof(hparts)) + { + as_bad(_("invalid halfword selector `%c' (must be either b or t)"), + p[1]); + sel = 0; + } + } + else + { + for (sel = 0; sel < sizeof(bparts); sel++) + if (TOLOWER(p[1]) == bparts[sel]) + break; + + if (sel >= sizeof(bparts)) + { + as_bad(_("invalid byte selector `%c' (must be one of b,l,u,t)"), + p[1]); + sel = 0; + } + } + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regid; + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = sel; +} + +/* This is the parser for "Rp[displacement]" expressions. In addition + to the "official" syntax, we accept a label as a replacement for + the register expression. This syntax implies Rp=PC and the + displacement is the pc-relative distance to the label. */ +static void +parse_intreg_disp(const struct avr32_operand *op, char *str, int opindex) +{ + expressionS *exp = ¤t_insn.immediate; + int slot, regid; + char *save, *p, c; + + pr_debug("parse_intreg_disp: `%s' (signed: %d, pcrel: %d, align: %d)\n", + str, op->is_signed, op->is_pcrel, op->align_order); + + for (p = str; *p; p++) + if (*p == '[') + break; + + slot = current_insn.next_slot++; + + /* First, check if we have a valid register either before '[' or as + the sole expression. If so, we use the Rp[disp] syntax. */ + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + *p = c; + + if (regid >= 0) + { + current_insn.field_value[slot].value = regid; + + slot = current_insn.next_slot++; + current_insn.field_value[slot].align_order = op->align_order; + + if (c == '[') + { + save = input_line_pointer; + input_line_pointer = p + 1; + + expression(exp); + + if (*input_line_pointer != ']') + as_bad(_("junk after displacement expression")); + + input_line_pointer = save; + + switch (exp->X_op) + { + case O_illegal: + as_bad(_("illegal displacement expression")); + break; + case O_absent: + as_bad(_("missing displacement expression")); + break; + case O_constant: + pr_debug(" -> constant: %ld\n", exp->X_add_number); + current_insn.field_value[slot].value = exp->X_add_number; + break; +#if 0 + case O_subtract: + if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg) + current_insn.pcrel = TRUE; + pr_debug(" -> subtract: pcrel? %s\n", + current_insn.pcrel ? "yes" : "no"); + /* fall through */ +#endif + default: + pr_debug(" -> (%p <%d> %p + %d)\n", + exp->X_add_symbol, exp->X_op, exp->X_op_symbol, + exp->X_add_number); + current_insn.field_value[slot].value = 0; + } + } + else + { + exp->X_op = O_constant; + exp->X_add_number = 0; + current_insn.field_value[slot].value = 0; + } + } + else + { + /* Didn't find a valid register. Try parsing it as a label. */ + current_insn.field_value[slot].value = AVR32_REG_PC; + parse_jmplabel(op, str, opindex); + } +} + +static void +parse_intreg_index(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + int slot, regid; + char *p, *end, c; + + for (p = str; *p; p++) + if (*p == '[') + break; + + assert(*p); + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + assert(regid >= 0); + *p = c; + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regid; + + p++; + for (end = p; *end; end++) + if (*end == ']' || *end == '<') + break; + + assert(*end); + + c = *end, *end = 0; + regid = avr32_parse_intreg(p); + assert(regid >= 0); + *end = c; + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regid; + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = 0; + + if (*end == '<') + { + expressionS exp; + char *save; + + p = end + 2; + for (end = p; *end; end++) + if (*end == ']') + break; + + assert(*end == ']'); + + c = *end, *end = 0; + save = input_line_pointer; + input_line_pointer = p; + expression(&exp); + + if (*input_line_pointer) + as_bad(_("junk after shift expression")); + + *end = c; + input_line_pointer = save; + + if (exp.X_op == O_constant) + current_insn.field_value[slot].value = exp.X_add_number; + else + as_bad(_("shift expression too complex")); + } +} + +static void +parse_intreg_xindex(const struct avr32_operand *op, char *str, int opindex) +{ + int slot, regid; + char *p, *end, c; + + for (p = str; *p; p++) + if (*p == '[') + break; + + assert(*p); + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + assert(regid >= 0); + *p = c; + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regid; + + p++; + for (end = p; *end; end++) + if (*end == '<') + break; + + assert(*end); + + c = *end, *end = 0; + parse_intreg_part(op, p, opindex); + *end = c; +} + +static void +parse_pc_disp(const struct avr32_operand *op, char *str, int opindex) +{ + char *p, c; + + for (p = str; *p; p++) + if (*p == '[') + break; + + /* The lddpc instruction comes in two different syntax variants: + lddpc reg, expression + lddpc reg, pc[disp] + If the operand contains a '[', we use the second form. */ + if (*p) + { + int regid; + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + *p = c; + if (regid == AVR32_REG_PC) + { + char *end; + + for (end = ++p; *end; end++) ; + if (*(--end) != ']') + as_bad(_("unrecognized form of instruction: `%s'"), str); + else + { + c = *end, *end = 0; + parse_const(op, p, opindex); + *end = c; + current_insn.pcrel = 0; + } + } + else + as_bad(_("unrecognized form of instruction: `%s'"), str); + } + else + { + parse_jmplabel(op, str, opindex); + } +} + +static void parse_sp(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str ATTRIBUTE_UNUSED, + int opindex ATTRIBUTE_UNUSED) +{ + int slot; + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = AVR32_REG_SP; +} + +static void +parse_sp_disp(const struct avr32_operand *op, char *str, int opindex) +{ + char *p, c; + + for (; *str; str++) + if (*str == '[') + break; + + assert(*str); + + for (p = ++str; *p; p++) + if (*p == ']') + break; + + c = *p, *p = 0; + parse_const(op, str, opindex); + *p = c; +} + +static void +parse_cpno(const struct avr32_operand *op ATTRIBUTE_UNUSED, char *str, + int opindex ATTRIBUTE_UNUSED) +{ + int slot; + + str += 2; + if (*str == '#') + str++; + if (*str < '0' || *str > '7' || str[1]) + as_bad(_("invalid coprocessor `%s'"), str); + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = *str - '0'; +} + +static void +parse_cpreg(const struct avr32_operand *op, char *str, + int opindex ATTRIBUTE_UNUSED) +{ + unsigned int crid; + int slot; + char *endptr; + + str += 2; + crid = strtoul(str, &endptr, 10); + if (*endptr || crid > 15 || crid & ((1 << op->align_order) - 1)) + as_bad(_("invalid coprocessor register `%s'"), str); + + crid >>= op->align_order; + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = crid; +} + +static void +parse_number(const struct avr32_operand *op, char *str, + int opindex ATTRIBUTE_UNUSED) +{ + expressionS exp; + int slot; + char *save; + + save = input_line_pointer; + input_line_pointer = str; + expression(&exp); + input_line_pointer = save; + + slot = current_insn.next_slot++; + current_insn.field_value[slot].align_order = op->align_order; + + if (exp.X_op == O_constant) + current_insn.field_value[slot].value = exp.X_add_number; + else + as_bad(_("invalid numeric expression `%s'"), str); +} + +static void +parse_reglist8(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + unsigned long regmask; + unsigned long value = 0; + int slot; + char *tail; + + regmask = avr32_parse_reglist(str, &tail); + if (*tail) + as_bad(_("invalid register list `%s'"), str); + else + { + if (avr32_make_regmask8(regmask, &value)) + as_bad(_("register list `%s' doesn't fit"), str); + } + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = value; +} + +static int +parse_reglist_tail(char *str, unsigned long regmask) +{ + expressionS exp; + char *save, *p, c; + int regid; + + for (p = str + 1; *p; p++) + if (*p == '=') + break; + + if (!*p) + { + as_bad(_("invalid register list `%s'"), str); + return -2; + } + + c = *p, *p = 0; + regid = avr32_parse_intreg(str); + *p = c; + + if (regid != 12) + { + as_bad(_("invalid register list `%s'"), str); + return -2; + } + + /* If we have an assignment, we must pop PC and we must _not_ + pop LR or R12 */ + if (!(regmask & (1 << AVR32_REG_PC))) + { + as_bad(_("return value specified for non-return instruction")); + return -2; + } + else if (regmask & ((1 << AVR32_REG_R12) | (1 << AVR32_REG_LR))) + { + as_bad(_("can't pop LR or R12 when specifying return value")); + return -2; + } + + save = input_line_pointer; + input_line_pointer = p + 1; + expression(&exp); + input_line_pointer = save; + + if (exp.X_op != O_constant + || exp.X_add_number < -1 + || exp.X_add_number > 1) + { + as_bad(_("invalid return value `%s'"), str); + return -2; + } + + return exp.X_add_number; +} + +static void +parse_reglist9(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + unsigned long regmask; + unsigned long value = 0, kbit = 0; + int slot; + char *tail; + + regmask = avr32_parse_reglist(str, &tail); + /* printf("parsed reglist16: %04lx, tail: `%s'\n", regmask, tail); */ + if (*tail) + { + int retval; + + retval = parse_reglist_tail(tail, regmask); + + switch (retval) + { + case -1: + regmask |= 1 << AVR32_REG_LR; + break; + case 0: + break; + case 1: + regmask |= 1 << AVR32_REG_R12; + break; + default: + break; + } + + kbit = 1; + } + + if (avr32_make_regmask8(regmask, &value)) + as_bad(_("register list `%s' doesn't fit"), str); + + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = (value << 1) | kbit; +} + +static void +parse_reglist16(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + unsigned long regmask; + int slot; + char *tail; + + regmask = avr32_parse_reglist(str, &tail); + if (*tail) + as_bad(_("invalid register list `%s'"), str); + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regmask; +} + +static void +parse_reglist_ldm(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + unsigned long regmask; + int slot, rp, w_bit = 0; + char *tail, *p, c; + + for (p = str; *p && *p != ','; p++) + if (*p == '+') + break; + + c = *p, *p = 0; + rp = avr32_parse_intreg(str); + *p = c; + if (rp < 0) + { + as_bad(_("invalid destination register in `%s'"), str); + return; + } + + if (p[0] == '+' && p[1] == '+') + { + w_bit = 1; + p += 2; + } + + if (*p != ',') + { + as_bad(_("expected `,' after destination register in `%s'"), str); + return; + } + + str = p + 1; + regmask = avr32_parse_reglist(str, &tail); + if (*tail) + { + int retval; + + if (rp != AVR32_REG_SP) + { + as_bad(_("junk at end of line: `%s'"), tail); + return; + } + + rp = AVR32_REG_PC; + + retval = parse_reglist_tail(tail, regmask); + + switch (retval) + { + case -1: + regmask |= 1 << AVR32_REG_LR; + break; + case 0: + break; + case 1: + regmask |= 1 << AVR32_REG_R12; + break; + default: + return; + } + } + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = rp; + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = w_bit; + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regmask; +} + +static void +parse_reglist_cp8(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + unsigned long regmask; + int slot, h_bit = 0; + char *tail; + + regmask = avr32_parse_cpreglist(str, &tail); + if (*tail) + as_bad(_("junk at end of line: `%s'"), tail); + else if (regmask & 0xffUL) + { + if (regmask & 0xff00UL) + as_bad(_("register list `%s' doesn't fit"), str); + regmask &= 0xff; + } + else if (regmask & 0xff00UL) + { + regmask >>= 8; + h_bit = 1; + } + else + as_warn(_("register list is empty")); + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regmask; + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = h_bit; +} + +static void +parse_reglist_cpd8(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + unsigned long regmask, regmask_d = 0; + int slot, i; + char *tail; + + regmask = avr32_parse_cpreglist(str, &tail); + if (*tail) + as_bad(_("junk at end of line: `%s'"), tail); + + for (i = 0; i < 8; i++) + { + if (regmask & 1) + { + if (!(regmask & 2)) + { + as_bad(_("register list `%s' doesn't fit"), str); + break; + } + regmask_d |= 1 << i; + } + else if (regmask & 2) + { + as_bad(_("register list `%s' doesn't fit"), str); + break; + } + + regmask >>= 2; + } + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regmask_d; +} + +static void +parse_retval(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + int regid, slot; + + regid = avr32_parse_intreg(str); + if (regid < 0) + { + expressionS exp; + char *save; + + regid = 0; + + save = input_line_pointer; + input_line_pointer = str; + expression(&exp); + input_line_pointer = save; + + if (exp.X_op != O_constant) + as_bad(_("invalid return value `%s'"), str); + else + switch (exp.X_add_number) + { + case -1: + regid = AVR32_REG_LR; + break; + case 0: + regid = AVR32_REG_SP; + break; + case 1: + regid = AVR32_REG_PC; + break; + default: + as_bad(_("invalid return value `%s'"), str); + break; + } + } + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regid; +} + +#define parse_mcall parse_intreg_disp + +static void +parse_jospinc(const struct avr32_operand *op ATTRIBUTE_UNUSED, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + expressionS exp; + int slot; + char *save; + + save = input_line_pointer; + input_line_pointer = str; + expression(&exp); + input_line_pointer = save; + + slot = current_insn.next_slot++; + + if (exp.X_op == O_constant) + { + if (exp.X_add_number > 0) + exp.X_add_number--; + current_insn.field_value[slot].value = exp.X_add_number; + } + else + as_bad(_("invalid numeric expression `%s'"), str); +} + +#define parse_coh parse_nothing + +static void +parse_fpreg(const struct avr32_operand *op, + char *str, int opindex ATTRIBUTE_UNUSED) +{ + unsigned long regid; + int slot; + + regid = strtoul(str + 2, NULL, 10); + + if ((regid >= 16) || (regid & ((1 << op->align_order) - 1))) + as_bad(_("invalid floating-point register `%s'"), str); + + slot = current_insn.next_slot++; + current_insn.field_value[slot].value = regid; + current_insn.field_value[slot].align_order = op->align_order; +} + +#define OP(name, sgn, pcrel, align, func) \ + { AVR32_OPERAND_##name, sgn, pcrel, align, match_##func, parse_##func } + +struct avr32_operand avr32_operand_table[] = { + OP(INTREG, 0, 0, 0, intreg), + OP(INTREG_PREDEC, 0, 0, 0, intreg_predec), + OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc), + OP(INTREG_LSL, 0, 0, 0, intreg_lsl), + OP(INTREG_LSR, 0, 0, 0, intreg_lsr), + OP(INTREG_BSEL, 0, 0, 0, intreg_part), + OP(INTREG_HSEL, 0, 0, 1, intreg_part), + OP(INTREG_SDISP, 1, 0, 0, intreg_disp), + OP(INTREG_SDISP_H, 1, 0, 1, intreg_disp), + OP(INTREG_SDISP_W, 1, 0, 2, intreg_disp), + OP(INTREG_UDISP, 0, 0, 0, intreg_disp), + OP(INTREG_UDISP_H, 0, 0, 1, intreg_disp), + OP(INTREG_UDISP_W, 0, 0, 2, intreg_disp), + OP(INTREG_INDEX, 0, 0, 0, intreg_index), + OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex), + OP(DWREG, 0, 0, 1, intreg), + OP(PC_UDISP_W, 0, 1, 2, pc_disp), + OP(SP, 0, 0, 0, sp), + OP(SP_UDISP_W, 0, 0, 2, sp_disp), + OP(CPNO, 0, 0, 0, cpno), + OP(CPREG, 0, 0, 0, cpreg), + OP(CPREG_D, 0, 0, 1, cpreg), + OP(UNSIGNED_CONST, 0, 0, 0, const), + OP(UNSIGNED_CONST_W, 0, 0, 2, const), + OP(SIGNED_CONST, 1, 0, 0, const), + OP(SIGNED_CONST_W, 1, 0, 2, const), + OP(JMPLABEL, 1, 1, 1, jmplabel), + OP(UNSIGNED_NUMBER, 0, 0, 0, number), + OP(UNSIGNED_NUMBER_W, 0, 0, 2, number), + OP(REGLIST8, 0, 0, 0, reglist8), + OP(REGLIST9, 0, 0, 0, reglist9), + OP(REGLIST16, 0, 0, 0, reglist16), + OP(REGLIST_LDM, 0, 0, 0, reglist_ldm), + OP(REGLIST_CP8, 0, 0, 0, reglist_cp8), + OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8), + OP(RETVAL, 0, 0, 0, retval), + OP(MCALL, 1, 0, 2, mcall), + OP(JOSPINC, 0, 0, 0, jospinc), + OP(COH, 0, 0, 0, coh), + OP(FPREG_S, 0, 0, 0, fpreg), + OP(FPREG_D, 0, 0, 1, fpreg), +}; + +symbolS * +md_undefined_symbol (char *name ATTRIBUTE_UNUSED) +{ + pr_debug("md_undefined_symbol: %s\n", name); + return 0; +} + +struct avr32_relax_type +{ + long lower_bound; + long upper_bound; + unsigned char align; + unsigned char length; + signed short next; +}; + +#define EMPTY { 0, 0, 0, 0, -1 } +#define C(lower, upper, align, next) \ + { (lower), (upper), (align), 2, AVR32_OPC_##next } +#define E(lower, upper, align) \ + { (lower), (upper), (align), 4, -1 } + +static const struct avr32_relax_type avr32_relax_table[] = + { + /* 0 */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, + E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0), + EMPTY, + /* 16 */ + EMPTY, EMPTY, EMPTY, EMPTY, + + C(-256, 254, 1, BREQ2), C(-256, 254, 1, BRNE2), + C(-256, 254, 1, BRCC2), C(-256, 254, 1, BRCS2), + C(-256, 254, 1, BRGE2), C(-256, 254, 1, BRLT2), + C(-256, 254, 1, BRMI2), C(-256, 254, 1, BRPL2), + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1), + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1), + /* 32 */ + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1), + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1), + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1), + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1), + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1), + E(-2097152, 2097150, 1), E(-2097152, 2097150, 1), + + EMPTY, EMPTY, EMPTY, EMPTY, + /* 48 */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, + + C(-32, 31, 0, CP_W3), E(-1048576, 1048575, 0), + + EMPTY, EMPTY, EMPTY, + /* 64: csrfcz */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + E(0, 65535, 0), E(0, 65535, 0), + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + E(-32768, 32767, 0), + /* 80: LD_SB2 */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + + C(0, 7, 0, LD_UB4), E(-32768, 32767, 0), + + EMPTY, + EMPTY, EMPTY, + + C(0, 14, 1, LD_SH4), E(-32768, 32767, 0), + + EMPTY, EMPTY, EMPTY, + + C(0, 14, 1, LD_UH4), E(-32768, 32767, 0), + + EMPTY, EMPTY, EMPTY, EMPTY, + + C(0, 124, 2, LD_W4), E(-32768, 32767, 0), + + E(0, 1020, 2), /* LDC_D1 */ + EMPTY, EMPTY, + E(0, 1020, 2), /* LDC_W1 */ + EMPTY, EMPTY, + E(0, 16380, 2), /* LDC0_D */ + E(0, 16380, 2), /* LDC0_W */ + EMPTY, EMPTY, EMPTY, EMPTY, + + C(0, 508, 2, LDDPC_EXT), E(-32768, 32767, 0), + + EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + /* 128: MACHH_W */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + E(-131072, 131068, 2), /* MCALL */ + E(0, 1020, 2), /* MFDR */ + E(0, 1020, 2), /* MFSR */ + EMPTY, EMPTY, + + C(-128, 127, 0, MOV2), E(-1048576, 1048575, 0), + + EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + + E(-128, 127, 0), /* MOVEQ2 */ + E(-128, 127, 0), /* MOVNE2 */ + E(-128, 127, 0), /* MOVCC2 */ + E(-128, 127, 0), /* 160: MOVCS2 */ + E(-128, 127, 0), /* MOVGE2 */ + E(-128, 127, 0), /* MOVLT2 */ + E(-128, 127, 0), /* MOVMI2 */ + E(-128, 127, 0), /* MOVPL2 */ + E(-128, 127, 0), /* MOVLS2 */ + E(-128, 127, 0), /* MOVGT2 */ + E(-128, 127, 0), /* MOVLE2 */ + E(-128, 127, 0), /* MOVHI2 */ + E(-128, 127, 0), /* MOVVS2 */ + E(-128, 127, 0), /* MOVVC2 */ + E(-128, 127, 0), /* MOVQS2 */ + E(-128, 127, 0), /* MOVAL2 */ + + E(0, 1020, 2), /* MTDR */ + E(0, 1020, 2), /* MTSR */ + EMPTY, + EMPTY, + E(-128, 127, 0), /* MUL3 */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + /* 192: MVCR_W */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + E(0, 65535, 0), E(0, 65535, 0), + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + /* 224: PASR_H */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + /* 256: PUNPCKSB_H */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + + C(-1024, 1022, 1, RCALL2), E(-2097152, 2097150, 1), + + EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, + + C(-1024, 1022, 1, BRAL), + + EMPTY, EMPTY, EMPTY, + E(-128, 127, 0), /* RSUB2 */ + /* 288: SATADD_H */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + E(0, 255, 0), /* SLEEP */ + EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + /* 320: ST_B2 */ + EMPTY, EMPTY, + C(0, 7, 0, ST_B4), E(-32768, 32767, 0), + EMPTY, EMPTY, EMPTY, EMPTY, + E(-32768, 32767, 0), + EMPTY, EMPTY, EMPTY, + C(0, 14, 1, ST_H4), E(-32768, 32767, 0), + EMPTY, EMPTY, + EMPTY, + C(0, 60, 2, ST_W4), E(-32768, 32767, 0), + E(0, 1020, 2), /* STC_D1 */ + EMPTY, EMPTY, + E(0, 1020, 2), /* STC_W1 */ + EMPTY, EMPTY, + E(0, 16380, 2), /* STC0_D */ + E(0, 16380, 2), /* STC0_W */ + + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + /* 352: STDSP */ + EMPTY, EMPTY, + E(0, 1020, 2), /* STHH_W1 */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + EMPTY, EMPTY, EMPTY, + E(-32768, 32767, 0), + C(-512, 508, 2, SUB4), + C(-128, 127, 0, SUB4), E(-1048576, 1048576, 0), + /* SUB{cond} */ + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), + /* SUBF{cond} */ + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), + E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), + EMPTY, + + /* 400: SWAP_B */ + EMPTY, EMPTY, EMPTY, + E(0, 255, 0), /* SYNC */ + EMPTY, EMPTY, EMPTY, EMPTY, + /* 408: TST */ + EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, + /* 416: EXTRACT_B */ + EMPTY, EMPTY, EMPTY, EMPTY, + }; + +#undef E +#undef C +#undef EMPTY + +#define AVR32_RS_NONE (-1) + +#define avr32_rs_size(state) (avr32_relax_table[(state)].length) +#define avr32_rs_align(state) (avr32_relax_table[(state)].align) +#define relax_more(state) (avr32_relax_table[(state)].next) + +#define opc_initial_substate(opc) ((opc)->id) + +static int need_relax(int subtype, offsetT distance) +{ + offsetT upper_bound, lower_bound; + + upper_bound = avr32_relax_table[subtype].upper_bound; + lower_bound = avr32_relax_table[subtype].lower_bound; + + if (distance & ((1 << avr32_rs_align(subtype)) - 1)) + return 1; + if ((distance > upper_bound) || (distance < lower_bound)) + return 1; + + return 0; +} + +enum { + LDA_SUBTYPE_MOV1, + LDA_SUBTYPE_MOV2, + LDA_SUBTYPE_SUB, + LDA_SUBTYPE_LDDPC, + LDA_SUBTYPE_LDW, + LDA_SUBTYPE_GOTLOAD, + LDA_SUBTYPE_GOTLOAD_LARGE, +}; + +enum { + CALL_SUBTYPE_RCALL1, + CALL_SUBTYPE_RCALL2, + CALL_SUBTYPE_MCALL_CP, + CALL_SUBTYPE_MCALL_GOT, + CALL_SUBTYPE_MCALL_LARGE, +}; + +#define LDA_INITIAL_SIZE (avr32_pic ? 4 : 2) +#define CALL_INITIAL_SIZE 2 + +#define need_reloc(sym, seg, pcrel) \ + (!(S_IS_DEFINED(sym) \ + && ((pcrel && S_GET_SEGMENT(sym) == seg) \ + || (!pcrel && S_GET_SEGMENT(sym) == absolute_section))) \ + || S_FORCE_RELOC(sym, 1)) + +/* Return an initial guess of the length by which a fragment must grow to + hold a branch to reach its destination. + Also updates fr_type/fr_subtype as necessary. + + Called just before doing relaxation. + Any symbol that is now undefined will not become defined. + The guess for fr_var is ACTUALLY the growth beyond fr_fix. + Whatever we do to grow fr_fix or fr_var contributes to our returned value. + Although it may not be explicit in the frag, pretend fr_var starts with a + 0 value. */ + +static int +avr32_default_estimate_size_before_relax (fragS *fragP, segT segment) +{ + int growth = 0; + + assert(fragP); + assert(fragP->fr_symbol); + + if (fragP->tc_frag_data.force_extended + || need_reloc(fragP->fr_symbol, segment, fragP->tc_frag_data.pcrel)) + { + int largest_state = fragP->fr_subtype; + while (relax_more(largest_state) != AVR32_RS_NONE) + largest_state = relax_more(largest_state); + growth = avr32_rs_size(largest_state) - fragP->fr_var; + } + else + { + growth = avr32_rs_size(fragP->fr_subtype) - fragP->fr_var; + } + + pr_debug("%s:%d: md_estimate_size_before_relax: %d\n", + fragP->fr_file, fragP->fr_line, growth); + + return growth; +} + +static int +avr32_lda_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED) +{ + return fragP->fr_var - LDA_INITIAL_SIZE; +} + +static int +avr32_call_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED) +{ + return fragP->fr_var - CALL_INITIAL_SIZE; +} + +static int +avr32_cpool_estimate_size_before_relax(fragS *fragP, + segT segment ATTRIBUTE_UNUSED) +{ + return fragP->fr_var; +} + +/* This macro may be defined to relax a frag. GAS will call this with the + * segment, the frag, and the change in size of all previous frags; + * md_relax_frag should return the change in size of the frag. */ +static long +avr32_default_relax_frag (segT segment, fragS *fragP, long stretch) +{ + int state, next_state; + symbolS *symbolP; /* The target symbol */ + long growth = 0; + + state = next_state = fragP->fr_subtype; + + symbolP = fragP->fr_symbol; + + if (fragP->tc_frag_data.force_extended + || need_reloc(symbolP, segment, fragP->tc_frag_data.pcrel)) + { + /* Symbol must be resolved by the linker. Emit the largest + possible opcode. */ + while (relax_more(next_state) != AVR32_RS_NONE) + next_state = relax_more(next_state); + } + else + { + addressT address; /* The address of fragP */ + addressT target; /* The address of the target symbol */ + offsetT distance; /* The distance between the insn and the symbol */ + fragS *sym_frag; + + address = fragP->fr_address; + target = fragP->fr_offset; + symbolP = fragP->fr_symbol; + sym_frag = symbol_get_frag(symbolP); + + address += fragP->fr_fix - fragP->fr_var; + target += S_GET_VALUE(symbolP); + + if (stretch != 0 + && sym_frag->relax_marker != fragP->relax_marker + && S_GET_SEGMENT(symbolP) == segment) + /* if it was correctly aligned before, make sure it stays aligned */ + target += stretch & (~0UL << avr32_rs_align(state)); + + if (fragP->tc_frag_data.pcrel) + distance = target - (address & (~0UL << avr32_rs_align(state))); + else + distance = target; + + pr_debug("%s:%d: relax more? 0x%x - 0x%x = 0x%x (%d), align %d\n", + fragP->fr_file, fragP->fr_line, target, address, + distance, distance, avr32_rs_align(state)); + + if (need_relax(state, distance)) + { + if (relax_more(state) != AVR32_RS_NONE) + next_state = relax_more(state); + pr_debug("%s:%d: relax more %d -> %d (%d - %d, align %d)\n", + fragP->fr_file, fragP->fr_line, state, next_state, + target, address, avr32_rs_align(state)); + } + } + + growth = avr32_rs_size(next_state) - avr32_rs_size(state); + fragP->fr_subtype = next_state; + + pr_debug("%s:%d: md_relax_frag: growth=%d, subtype=%d, opc=0x%08lx\n", + fragP->fr_file, fragP->fr_line, growth, fragP->fr_subtype, + avr32_opc_table[next_state].value); + + return growth; +} + +static long +avr32_lda_relax_frag(segT segment, fragS *fragP, long stretch) +{ + struct cpool *pool; + unsigned int entry; + addressT address, target; + offsetT distance; + symbolS *symbolP; + fragS *sym_frag; + long old_size, new_size; + + symbolP = fragP->fr_symbol; + old_size = fragP->fr_var; + if (!avr32_pic) + { + pool = fragP->tc_frag_data.pool; + entry = fragP->tc_frag_data.pool_entry; + } + + address = fragP->fr_address; + address += fragP->fr_fix - LDA_INITIAL_SIZE; + + if (!S_IS_DEFINED(symbolP) || S_FORCE_RELOC(symbolP, 1)) + goto relax_max; + + target = fragP->fr_offset; + sym_frag = symbol_get_frag(symbolP); + target += S_GET_VALUE(symbolP); + + if (sym_frag->relax_marker != fragP->relax_marker + && S_GET_SEGMENT(symbolP) == segment) + target += stretch; + + distance = target - address; + + pr_debug("lda_relax_frag: target: %d, address: %d, var: %d\n", + target, address, fragP->fr_var); + + if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section + && target <= 127 && (offsetT)target >= -128) + { + if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC + || fragP->fr_subtype == LDA_SUBTYPE_LDW) + pool->literals[entry].refcount--; + new_size = 2; + fragP->fr_subtype = LDA_SUBTYPE_MOV1; + } + else if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section + && target <= 1048575 && (offsetT)target >= -1048576) + { + if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC + || fragP->fr_subtype == LDA_SUBTYPE_LDW) + pool->literals[entry].refcount--; + new_size = 4; + fragP->fr_subtype = LDA_SUBTYPE_MOV2; + } + else if (!linkrelax && S_GET_SEGMENT(symbolP) == segment + /* the field will be negated, so this is really -(-32768) + and -(32767) */ + && distance <= 32768 && distance >= -32767) + { + if (!avr32_pic + && (fragP->fr_subtype == LDA_SUBTYPE_LDDPC + || fragP->fr_subtype == LDA_SUBTYPE_LDW)) + pool->literals[entry].refcount--; + new_size = 4; + fragP->fr_subtype = LDA_SUBTYPE_SUB; + } + else + { + relax_max: + if (avr32_pic) + { + if (linkrelax) + { + new_size = 8; + fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD_LARGE; + } + else + { + new_size = 4; + fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD; + } + } + else + { + if (fragP->fr_subtype != LDA_SUBTYPE_LDDPC + && fragP->fr_subtype != LDA_SUBTYPE_LDW) + pool->literals[entry].refcount++; + + sym_frag = symbol_get_frag(pool->symbol); + target = (sym_frag->fr_address + sym_frag->fr_fix + + pool->padding + pool->literals[entry].offset); + + pr_debug("cpool sym address: 0x%lx\n", + sym_frag->fr_address + sym_frag->fr_fix); + + know(pool->section == segment); + + if (sym_frag->relax_marker != fragP->relax_marker) + target += stretch; + + distance = target - address; + if (distance <= 508 && distance >= 0) + { + new_size = 2; + fragP->fr_subtype = LDA_SUBTYPE_LDDPC; + } + else + { + new_size = 4; + fragP->fr_subtype = LDA_SUBTYPE_LDW; + } + + pr_debug("lda_relax_frag (cpool): target=0x%lx, address=0x%lx, refcount=%d\n", + target, address, pool->literals[entry].refcount); + } + } + + fragP->fr_var = new_size; + + pr_debug("%s:%d: lda: relax pass done. subtype: %d, growth: %ld\n", + fragP->fr_file, fragP->fr_line, + fragP->fr_subtype, new_size - old_size); + + return new_size - old_size; +} + +static long +avr32_call_relax_frag(segT segment, fragS *fragP, long stretch) +{ + struct cpool *pool; + unsigned int entry; + addressT address, target; + offsetT distance; + symbolS *symbolP; + fragS *sym_frag; + long old_size, new_size; + + symbolP = fragP->fr_symbol; + old_size = fragP->fr_var; + if (!avr32_pic) + { + pool = fragP->tc_frag_data.pool; + entry = fragP->tc_frag_data.pool_entry; + } + + address = fragP->fr_address; + address += fragP->fr_fix - CALL_INITIAL_SIZE; + + if (need_reloc(symbolP, segment, 1)) + { + pr_debug("call: must emit reloc\n"); + goto relax_max; + } + + target = fragP->fr_offset; + sym_frag = symbol_get_frag(symbolP); + target += S_GET_VALUE(symbolP); + + if (sym_frag->relax_marker != fragP->relax_marker + && S_GET_SEGMENT(symbolP) == segment) + target += stretch; + + distance = target - address; + + if (distance <= 1022 && distance >= -1024) + { + pr_debug("call: distance is %d, emitting short rcall\n", distance); + if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP) + pool->literals[entry].refcount--; + new_size = 2; + fragP->fr_subtype = CALL_SUBTYPE_RCALL1; + } + else if (distance <= 2097150 && distance >= -2097152) + { + pr_debug("call: distance is %d, emitting long rcall\n", distance); + if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP) + pool->literals[entry].refcount--; + new_size = 4; + fragP->fr_subtype = CALL_SUBTYPE_RCALL2; + } + else + { + pr_debug("call: distance %d too far, emitting something big\n", distance); + + relax_max: + if (avr32_pic) + { + if (linkrelax) + { + new_size = 10; + fragP->fr_subtype = CALL_SUBTYPE_MCALL_LARGE; + } + else + { + new_size = 4; + fragP->fr_subtype = CALL_SUBTYPE_MCALL_GOT; + } + } + else + { + if (fragP->fr_subtype != CALL_SUBTYPE_MCALL_CP) + pool->literals[entry].refcount++; + + new_size = 4; + fragP->fr_subtype = CALL_SUBTYPE_MCALL_CP; + } + } + + fragP->fr_var = new_size; + + pr_debug("%s:%d: call: relax pass done, growth: %d, fr_var: %d\n", + fragP->fr_file, fragP->fr_line, + new_size - old_size, fragP->fr_var); + + return new_size - old_size; +} + +static long +avr32_cpool_relax_frag(segT segment ATTRIBUTE_UNUSED, + fragS *fragP, + long stretch ATTRIBUTE_UNUSED) +{ + struct cpool *pool; + addressT address; + long old_size, new_size; + unsigned int entry; + + pool = fragP->tc_frag_data.pool; + address = fragP->fr_address + fragP->fr_fix; + old_size = fragP->fr_var; + new_size = 0; + + for (entry = 0; entry < pool->next_free_entry; entry++) + { + if (pool->literals[entry].refcount > 0) + { + pool->literals[entry].offset = new_size; + new_size += 4; + } + } + + fragP->fr_var = new_size; + + return new_size - old_size; +} + +/* *fragP has been relaxed to its final size, and now needs to have + the bytes inside it modified to conform to the new size. + + Called after relaxation is finished. + fragP->fr_type == rs_machine_dependent. + fragP->fr_subtype is the subtype of what the address relaxed to. */ + +static void +avr32_default_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, + segT segment ATTRIBUTE_UNUSED, + fragS *fragP) +{ + const struct avr32_opcode *opc; + const struct avr32_ifield *ifield; + bfd_reloc_code_real_type r_type; + symbolS *symbolP; + fixS *fixP; + bfd_vma value; + int subtype; + + opc = &avr32_opc_table[fragP->fr_subtype]; + ifield = opc->fields[opc->var_field]; + symbolP = fragP->fr_symbol; + subtype = fragP->fr_subtype; + r_type = opc->reloc_type; + + /* Clear the opcode bits and the bits belonging to the relaxed + field. We assume all other fields stay the same. */ + value = bfd_getb32(fragP->fr_opcode); + value &= ~(opc->mask | ifield->mask); + + /* Insert the new opcode */ + value |= opc->value; + bfd_putb32(value, fragP->fr_opcode); + + fragP->fr_fix += opc->size - fragP->fr_var; + + if (fragP->tc_frag_data.reloc_info != AVR32_OPINFO_NONE) + { + switch (fragP->tc_frag_data.reloc_info) + { + case AVR32_OPINFO_HI: + r_type = BFD_RELOC_HI16; + break; + case AVR32_OPINFO_LO: + r_type = BFD_RELOC_LO16; + break; + case AVR32_OPINFO_GOT: + switch (r_type) + { + case BFD_RELOC_AVR32_18W_PCREL: + r_type = BFD_RELOC_AVR32_GOT18SW; + break; + case BFD_RELOC_AVR32_16S: + r_type = BFD_RELOC_AVR32_GOT16S; + break; + default: + BAD_CASE(r_type); + break; + } + break; + default: + BAD_CASE(fragP->tc_frag_data.reloc_info); + break; + } + } + + pr_debug("%s:%d: convert_frag: new %s fixup\n", + fragP->fr_file, fragP->fr_line, + bfd_get_reloc_code_name(r_type)); + +#if 1 + fixP = fix_new_exp(fragP, fragP->fr_fix - opc->size, opc->size, + &fragP->tc_frag_data.exp, + fragP->tc_frag_data.pcrel, r_type); +#else + fixP = fix_new(fragP, fragP->fr_fix - opc->size, opc->size, symbolP, + fragP->fr_offset, fragP->tc_frag_data.pcrel, r_type); +#endif + + /* Revert fix_new brain damage. "dot_value" is the value of PC at + the point of the fixup, relative to the frag address. fix_new() + and friends think they are only being called during the assembly + pass, not during relaxation or similar, so fx_dot_value, fx_file + and fx_line are all initialized to the wrong value. But we don't + know the size of the fixup until now, so we really can't live up + to the assumptions these functions make about the target. What + do these functions think the "where" and "frag" argument mean + anyway? */ + fixP->fx_dot_value = fragP->fr_fix - opc->size; + fixP->fx_file = fragP->fr_file; + fixP->fx_line = fragP->fr_line; + + fixP->tc_fix_data.ifield = ifield; + fixP->tc_fix_data.align = avr32_rs_align(subtype); + fixP->tc_fix_data.min = avr32_relax_table[subtype].lower_bound; + fixP->tc_fix_data.max = avr32_relax_table[subtype].upper_bound; +} + +static void +avr32_lda_convert_frag(bfd *abfd ATTRIBUTE_UNUSED, + segT segment ATTRIBUTE_UNUSED, + fragS *fragP) +{ + const struct avr32_opcode *opc; + const struct avr32_ifield *ifield; + bfd_reloc_code_real_type r_type; + expressionS exp; + struct cpool *pool; + fixS *fixP; + bfd_vma value; + int regid, pcrel = 0, align = 0; + char *p; + + r_type = BFD_RELOC_NONE; + regid = fragP->tc_frag_data.reloc_info; + p = fragP->fr_opcode; + exp.X_add_symbol = fragP->fr_symbol; + exp.X_add_number = fragP->fr_offset; + exp.X_op = O_symbol; + + pr_debug("%s:%d: lda_convert_frag, subtype: %d, fix: %d, var: %d, regid: %d\n", + fragP->fr_file, fragP->fr_line, + fragP->fr_subtype, fragP->fr_fix, fragP->fr_var, regid); + + switch (fragP->fr_subtype) + { + case LDA_SUBTYPE_MOV1: + opc = &avr32_opc_table[AVR32_OPC_MOV1]; + opc->fields[0]->insert(opc->fields[0], p, regid); + ifield = opc->fields[1]; + r_type = opc->reloc_type; + break; + case LDA_SUBTYPE_MOV2: + opc = &avr32_opc_table[AVR32_OPC_MOV2]; + opc->fields[0]->insert(opc->fields[0], p, regid); + ifield = opc->fields[1]; + r_type = opc->reloc_type; + break; + case LDA_SUBTYPE_SUB: + opc = &avr32_opc_table[AVR32_OPC_SUB5]; + opc->fields[0]->insert(opc->fields[0], p, regid); + opc->fields[1]->insert(opc->fields[1], p, AVR32_REG_PC); + ifield = opc->fields[2]; + r_type = BFD_RELOC_AVR32_16N_PCREL; + + /* Pretend that SUB5 isn't a "negated" pcrel expression for now. + We'll have to fix it up later when we know whether to + generate a reloc for it (in which case the linker will negate + it, so we shouldn't). */ + pcrel = 1; + break; + case LDA_SUBTYPE_LDDPC: + opc = &avr32_opc_table[AVR32_OPC_LDDPC]; + align = 2; + r_type = BFD_RELOC_AVR32_9W_CP; + goto cpool_common; + case LDA_SUBTYPE_LDW: + opc = &avr32_opc_table[AVR32_OPC_LDDPC_EXT]; + r_type = BFD_RELOC_AVR32_16_CP; + cpool_common: + opc->fields[0]->insert(opc->fields[0], p, regid); + ifield = opc->fields[1]; + pool = fragP->tc_frag_data.pool; + exp.X_add_symbol = pool->symbol; + exp.X_add_number = pool->literals[fragP->tc_frag_data.pool_entry].offset; + pcrel = 1; + break; + case LDA_SUBTYPE_GOTLOAD_LARGE: + /* ld.w Rd, r6[Rd << 2] (last) */ + opc = &avr32_opc_table[AVR32_OPC_LD_W5]; + bfd_putb32(opc->value, p + 4); + opc->fields[0]->insert(opc->fields[0], p + 4, regid); + opc->fields[1]->insert(opc->fields[1], p + 4, 6); + opc->fields[2]->insert(opc->fields[2], p + 4, regid); + opc->fields[3]->insert(opc->fields[3], p + 4, 2); + + /* mov Rd, (got_offset / 4) */ + opc = &avr32_opc_table[AVR32_OPC_MOV2]; + opc->fields[0]->insert(opc->fields[0], p, regid); + ifield = opc->fields[1]; + r_type = BFD_RELOC_AVR32_LDA_GOT; + break; + case LDA_SUBTYPE_GOTLOAD: + opc = &avr32_opc_table[AVR32_OPC_LD_W4]; + opc->fields[0]->insert(opc->fields[0], p, regid); + opc->fields[1]->insert(opc->fields[1], p, 6); + ifield = opc->fields[2]; + if (r_type == BFD_RELOC_NONE) + r_type = BFD_RELOC_AVR32_GOT16S; + break; + default: + BAD_CASE(fragP->fr_subtype); + } + + value = bfd_getb32(p); + value &= ~(opc->mask | ifield->mask); + value |= opc->value; + bfd_putb32(value, p); + + fragP->fr_fix += fragP->fr_var - LDA_INITIAL_SIZE; + + if (fragP->fr_next + && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address) + != fragP->fr_fix)) + { + fprintf(stderr, "LDA frag: fr_fix is wrong! fragP->fr_var = %ld, r_type = %s\n", + fragP->fr_var, bfd_get_reloc_code_name(r_type)); + abort(); + } + + fixP = fix_new_exp(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var, + &exp, pcrel, r_type); + + /* Revert fix_new brain damage. "dot_value" is the value of PC at + the point of the fixup, relative to the frag address. fix_new() + and friends think they are only being called during the assembly + pass, not during relaxation or similar, so fx_dot_value, fx_file + and fx_line are all initialized to the wrong value. But we don't + know the size of the fixup until now, so we really can't live up + to the assumptions these functions make about the target. What + do these functions think the "where" and "frag" argument mean + anyway? */ + fixP->fx_dot_value = fragP->fr_fix - opc->size; + fixP->fx_file = fragP->fr_file; + fixP->fx_line = fragP->fr_line; + + fixP->tc_fix_data.ifield = ifield; + fixP->tc_fix_data.align = align; + /* these are only used if the fixup can actually be resolved */ + fixP->tc_fix_data.min = -32768; + fixP->tc_fix_data.max = 32767; +} + +static void +avr32_call_convert_frag(bfd *abfd ATTRIBUTE_UNUSED, + segT segment ATTRIBUTE_UNUSED, + fragS *fragP) +{ + const struct avr32_opcode *opc = NULL; + const struct avr32_ifield *ifield; + bfd_reloc_code_real_type r_type; + symbolS *symbol; + offsetT offset; + fixS *fixP; + bfd_vma value; + int pcrel = 0, align = 0; + char *p; + + symbol = fragP->fr_symbol; + offset = fragP->fr_offset; + r_type = BFD_RELOC_NONE; + p = fragP->fr_opcode; + + pr_debug("%s:%d: call_convert_frag, subtype: %d, fix: %d, var: %d\n", + fragP->fr_file, fragP->fr_line, + fragP->fr_subtype, fragP->fr_fix, fragP->fr_var); + + switch (fragP->fr_subtype) + { + case CALL_SUBTYPE_RCALL1: + opc = &avr32_opc_table[AVR32_OPC_RCALL1]; + /* fall through */ + case CALL_SUBTYPE_RCALL2: + if (!opc) + opc = &avr32_opc_table[AVR32_OPC_RCALL2]; + ifield = opc->fields[0]; + r_type = opc->reloc_type; + pcrel = 1; + align = 1; + break; + case CALL_SUBTYPE_MCALL_CP: + opc = &avr32_opc_table[AVR32_OPC_MCALL]; + opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_PC); + ifield = opc->fields[1]; + r_type = BFD_RELOC_AVR32_CPCALL; + symbol = fragP->tc_frag_data.pool->symbol; + offset = fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].offset; + assert(fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].refcount > 0); + pcrel = 1; + align = 2; + break; + case CALL_SUBTYPE_MCALL_GOT: + opc = &avr32_opc_table[AVR32_OPC_MCALL]; + opc->fields[0]->insert(opc->fields[0], p, 6); + ifield = opc->fields[1]; + r_type = BFD_RELOC_AVR32_GOT18SW; + break; + case CALL_SUBTYPE_MCALL_LARGE: + assert(fragP->fr_var == 10); + /* ld.w lr, r6[lr << 2] */ + opc = &avr32_opc_table[AVR32_OPC_LD_W5]; + bfd_putb32(opc->value, p + 4); + opc->fields[0]->insert(opc->fields[0], p + 4, AVR32_REG_LR); + opc->fields[1]->insert(opc->fields[1], p + 4, 6); + opc->fields[2]->insert(opc->fields[2], p + 4, AVR32_REG_LR); + opc->fields[3]->insert(opc->fields[3], p + 4, 2); + + /* icall lr */ + opc = &avr32_opc_table[AVR32_OPC_ICALL]; + bfd_putb16(opc->value >> 16, p + 8); + opc->fields[0]->insert(opc->fields[0], p + 8, AVR32_REG_LR); + + /* mov lr, (got_offset / 4) */ + opc = &avr32_opc_table[AVR32_OPC_MOV2]; + opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_LR); + ifield = opc->fields[1]; + r_type = BFD_RELOC_AVR32_GOTCALL; + break; + default: + BAD_CASE(fragP->fr_subtype); + } + + /* Insert the opcode and clear the variable ifield */ + value = bfd_getb32(p); + value &= ~(opc->mask | ifield->mask); + value |= opc->value; + bfd_putb32(value, p); + + fragP->fr_fix += fragP->fr_var - CALL_INITIAL_SIZE; + + if (fragP->fr_next + && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address) + != fragP->fr_fix)) + { + fprintf(stderr, "%s:%d: fr_fix %lu is wrong! fr_var=%lu, r_type=%s\n", + fragP->fr_file, fragP->fr_line, + fragP->fr_fix, fragP->fr_var, bfd_get_reloc_code_name(r_type)); + fprintf(stderr, "fr_fix should be %ld. next frag is %s:%d\n", + (offsetT)(fragP->fr_next->fr_address - fragP->fr_address), + fragP->fr_next->fr_file, fragP->fr_next->fr_line); + } + + fixP = fix_new(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var, + symbol, offset, pcrel, r_type); + + /* Revert fix_new brain damage. "dot_value" is the value of PC at + the point of the fixup, relative to the frag address. fix_new() + and friends think they are only being called during the assembly + pass, not during relaxation or similar, so fx_dot_value, fx_file + and fx_line are all initialized to the wrong value. But we don't + know the size of the fixup until now, so we really can't live up + to the assumptions these functions make about the target. What + do these functions think the "where" and "frag" argument mean + anyway? */ + fixP->fx_dot_value = fragP->fr_fix - opc->size; + fixP->fx_file = fragP->fr_file; + fixP->fx_line = fragP->fr_line; + + fixP->tc_fix_data.ifield = ifield; + fixP->tc_fix_data.align = align; + /* these are only used if the fixup can actually be resolved */ + fixP->tc_fix_data.min = -2097152; + fixP->tc_fix_data.max = 2097150; +} + +static void +avr32_cpool_convert_frag(bfd *abfd ATTRIBUTE_UNUSED, + segT segment ATTRIBUTE_UNUSED, + fragS *fragP) +{ + struct cpool *pool; + addressT address; + unsigned int entry; + char *p; + char sym_name[20]; + + /* Did we get rid of the frag altogether? */ + if (!fragP->fr_var) + return; + + pool = fragP->tc_frag_data.pool; + address = fragP->fr_address + fragP->fr_fix; + p = fragP->fr_literal + fragP->fr_fix; + + sprintf(sym_name, "$$cp_\002%x", pool->id); + symbol_locate(pool->symbol, sym_name, pool->section, fragP->fr_fix, fragP); + symbol_table_insert(pool->symbol); + + for (entry = 0; entry < pool->next_free_entry; entry++) + { + if (pool->literals[entry].refcount > 0) + { + fix_new_exp(fragP, fragP->fr_fix, 4, &pool->literals[entry].exp, + FALSE, BFD_RELOC_AVR32_32_CPENT); + fragP->fr_fix += 4; + } + } +} + +static struct avr32_relaxer avr32_default_relaxer = { + .estimate_size = avr32_default_estimate_size_before_relax, + .relax_frag = avr32_default_relax_frag, + .convert_frag = avr32_default_convert_frag, +}; +static struct avr32_relaxer avr32_lda_relaxer = { + .estimate_size = avr32_lda_estimate_size_before_relax, + .relax_frag = avr32_lda_relax_frag, + .convert_frag = avr32_lda_convert_frag, +}; +static struct avr32_relaxer avr32_call_relaxer = { + .estimate_size = avr32_call_estimate_size_before_relax, + .relax_frag = avr32_call_relax_frag, + .convert_frag = avr32_call_convert_frag, +}; +static struct avr32_relaxer avr32_cpool_relaxer = { + .estimate_size = avr32_cpool_estimate_size_before_relax, + .relax_frag = avr32_cpool_relax_frag, + .convert_frag = avr32_cpool_convert_frag, +}; + +static void s_cpool(int arg ATTRIBUTE_UNUSED) +{ + struct cpool *pool; + unsigned int max_size; + char *buf; + + pool = find_cpool(now_seg, now_subseg); + if (!pool || !pool->symbol || pool->next_free_entry == 0) + return; + + /* Make sure the constant pool is properly aligned */ + frag_align_code(2, 0); + + /* Assume none of the entries are discarded, and that we need the + maximum amount of alignment. But we're not going to allocate + anything up front. */ + max_size = pool->next_free_entry * 4 + 2; + frag_grow(max_size); + buf = frag_more(0); + + frag_now->tc_frag_data.relaxer = &avr32_cpool_relaxer; + frag_now->tc_frag_data.pool = pool; + + symbol_set_frag(pool->symbol, frag_now); + + /* Assume zero initial size, allowing other relaxers to be + optimistic about things. */ + frag_var(rs_machine_dependent, max_size, 0, + 0, pool->symbol, 0, NULL); + + /* Mark the pool as empty. */ + pool->used = 1; +} + +/* The location from which a PC relative jump should be calculated, + given a PC relative reloc. */ + +long +md_pcrel_from_section (fixS *fixP, segT sec) +{ + pr_debug("pcrel_from_section, fx_offset = %d\n", fixP->fx_offset); + + if (fixP->fx_addsy != NULL + && (! S_IS_DEFINED (fixP->fx_addsy) + || S_GET_SEGMENT (fixP->fx_addsy) != sec + || S_FORCE_RELOC(fixP->fx_addsy, 1))) + { + pr_debug("Unknown pcrel symbol: %s\n", S_GET_NAME(fixP->fx_addsy)); + + /* The symbol is undefined (or is defined but not in this section). + Let the linker figure it out. */ + return 0; + } + + pr_debug("pcrel from %x + %x, symbol: %s (%x)\n", + fixP->fx_frag->fr_address, fixP->fx_where, + fixP->fx_addsy?S_GET_NAME(fixP->fx_addsy):"(null)", + fixP->fx_addsy?S_GET_VALUE(fixP->fx_addsy):0); + + return ((fixP->fx_frag->fr_address + fixP->fx_where) + & (~0UL << fixP->tc_fix_data.align)); +} + +valueT +md_section_align (segT segment, valueT size) +{ + int align = bfd_get_section_alignment (stdoutput, segment); + return ((size + (1 << align) - 1) & (-1 << align)); +} + +static int syntax_matches(const struct avr32_syntax *syntax, + char *str) +{ + int i; + + pr_debug("syntax %d matches `%s'?\n", syntax->id, str); + + if (syntax->nr_operands < 0) + { + struct avr32_operand *op; + int optype; + + for (i = 0; i < (-syntax->nr_operands - 1); i++) + { + char *p; + char c; + + optype = syntax->operand[i]; + assert(optype < AVR32_NR_OPERANDS); + op = &avr32_operand_table[optype]; + + for (p = str; *p; p++) + if (*p == ',') + break; + + if (p == str) + return 0; + + c = *p; + *p = 0; + + if (!op->match(str)) + { + *p = c; + return 0; + } + + str = p; + *p = c; + if (c) + str++; + } + + optype = syntax->operand[i]; + assert(optype < AVR32_NR_OPERANDS); + op = &avr32_operand_table[optype]; + + if (!op->match(str)) + return 0; + return 1; + } + + for (i = 0; i < syntax->nr_operands; i++) + { + struct avr32_operand *op; + int optype = syntax->operand[i]; + char *p; + char c; + + assert(optype < AVR32_NR_OPERANDS); + op = &avr32_operand_table[optype]; + + for (p = str; *p; p++) + if (*p == ',') + break; + + if (p == str) + return 0; + + c = *p; + *p = 0; + + if (!op->match(str)) + { + *p = c; + return 0; + } + + str = p; + *p = c; + if (c) + str++; + } + + if (*str == '\0') + return 1; + + if ((*str == 'e' || *str == 'E') && !str[1]) + return 1; + + return 0; +} + +static int parse_operands(char *str) +{ + int i; + + if (current_insn.syntax->nr_operands < 0) + { + int optype; + struct avr32_operand *op; + + for (i = 0; i < (-current_insn.syntax->nr_operands - 1); i++) + { + char *p; + char c; + + optype = current_insn.syntax->operand[i]; + op = &avr32_operand_table[optype]; + + for (p = str; *p; p++) + if (*p == ',') + break; + + assert(p != str); + + c = *p, *p = 0; + op->parse(op, str, i); + *p = c; + + str = p; + if (c) str++; + } + + /* give the rest of the line to the last operand */ + optype = current_insn.syntax->operand[i]; + op = &avr32_operand_table[optype]; + op->parse(op, str, i); + } + else + { + for (i = 0; i < current_insn.syntax->nr_operands; i++) + { + int optype = current_insn.syntax->operand[i]; + struct avr32_operand *op = &avr32_operand_table[optype]; + char *p; + char c; + + skip_whitespace(str); + + for (p = str; *p; p++) + if (*p == ',') + break; + + assert(p != str); + + c = *p, *p = 0; + op->parse(op, str, i); + *p = c; + + str = p; + if (c) str++; + } + + if (*str == 'E' || *str == 'e') + current_insn.force_extended = 1; + } + + return 0; +} + +static const char * +finish_insn(const struct avr32_opcode *opc) +{ + expressionS *exp = ¤t_insn.immediate; + unsigned int i; + int will_relax = 0; + char *buf; + + assert(current_insn.next_slot == opc->nr_fields); + + pr_debug("%s:%d: finish_insn: trying opcode %d\n", + frag_now->fr_file, frag_now->fr_line, opc->id); + + /* Go through the relaxation stage for all instructions that can + possibly take a symbolic immediate. The relax code will take + care of range checking and alignment. */ + if (opc->var_field != -1) + { + int substate, largest_substate; + symbolS *sym; + offsetT off; + + will_relax = 1; + substate = largest_substate = opc_initial_substate(opc); + + while (relax_more(largest_substate) != AVR32_RS_NONE) + largest_substate = relax_more(largest_substate); + + pr_debug("will relax. initial substate: %d (size %d), largest substate: %d (size %d)\n", + substate, avr32_rs_size(substate), + largest_substate, avr32_rs_size(largest_substate)); + + /* make sure we have enough room for the largest possible opcode */ + frag_grow(avr32_rs_size(largest_substate)); + buf = frag_more(opc->size); + + dwarf2_emit_insn(opc->size); + + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_NONE; + frag_now->tc_frag_data.pcrel = current_insn.pcrel; + frag_now->tc_frag_data.force_extended = current_insn.force_extended; + frag_now->tc_frag_data.relaxer = &avr32_default_relaxer; + + if (exp->X_op == O_hi) + { + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_HI; + exp->X_op = exp->X_md; + } + else if (exp->X_op == O_lo) + { + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_LO; + exp->X_op = exp->X_md; + } + else if (exp->X_op == O_got) + { + frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_GOT; + exp->X_op = O_symbol; + } + +#if 0 + if ((opc->reloc_type == BFD_RELOC_AVR32_SUB5) + && exp->X_op == O_subtract) + { + symbolS *tmp; + tmp = exp->X_add_symbol; + exp->X_add_symbol = exp->X_op_symbol; + exp->X_op_symbol = tmp; + } +#endif + + frag_now->tc_frag_data.exp = current_insn.immediate; + + sym = exp->X_add_symbol; + off = exp->X_add_number; + if (exp->X_op != O_symbol) + { + sym = make_expr_symbol(exp); + off = 0; + } + + frag_var(rs_machine_dependent, + avr32_rs_size(largest_substate) - opc->size, + opc->size, + substate, sym, off, buf); + } + else + { + assert(avr32_rs_size(opc_initial_substate(opc)) == 0); + buf = frag_more(opc->size); + dwarf2_emit_insn(opc->size); + } + + assert(!(opc->value & ~opc->mask)); + + pr_debug("inserting opcode: 0x%lx\n", opc->value); + bfd_putb32(opc->value, buf); + + for (i = 0; i < opc->nr_fields; i++) + { + const struct avr32_ifield *f = opc->fields[i]; + const struct avr32_ifield_data *fd = ¤t_insn.field_value[i]; + + pr_debug("inserting field: 0x%lx & 0x%lx\n", + fd->value >> fd->align_order, f->mask); + + f->insert(f, buf, fd->value >> fd->align_order); + } + + assert(will_relax || !current_insn.immediate.X_add_symbol); + return NULL; +} + +static const char * +finish_alias(const struct avr32_alias *alias) +{ + const struct avr32_opcode *opc; + struct { + unsigned long value; + unsigned long align; + } mapped_operand[AVR32_MAX_OPERANDS]; + unsigned int i; + + opc = alias->opc; + + /* Remap the operands from the alias to the real opcode */ + for (i = 0; i < opc->nr_fields; i++) + { + if (alias->operand_map[i].is_opindex) + { + struct avr32_ifield_data *fd; + fd = ¤t_insn.field_value[alias->operand_map[i].value]; + mapped_operand[i].value = fd->value; + mapped_operand[i].align = fd->align_order; + } + else + { + mapped_operand[i].value = alias->operand_map[i].value; + mapped_operand[i].align = 0; + } + } + + for (i = 0; i < opc->nr_fields; i++) + { + current_insn.field_value[i].value = mapped_operand[i].value; + if (opc->id == AVR32_OPC_COP) + current_insn.field_value[i].align_order = 0; + else + current_insn.field_value[i].align_order + = mapped_operand[i].align; + } + + current_insn.next_slot = opc->nr_fields; + + return finish_insn(opc); +} + +static const char * +finish_lda(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED) +{ + expressionS *exp = ¤t_insn.immediate; + relax_substateT initial_subtype; + symbolS *sym; + offsetT off; + int initial_size, max_size; + char *buf; + + initial_size = LDA_INITIAL_SIZE; + + if (avr32_pic) + { + initial_subtype = LDA_SUBTYPE_SUB; + if (linkrelax) + max_size = 8; + else + max_size = 4; + } + else + { + initial_subtype = LDA_SUBTYPE_MOV1; + max_size = 4; + } + + frag_grow(max_size); + buf = frag_more(initial_size); + dwarf2_emit_insn(initial_size); + + if (exp->X_op == O_symbol) + { + sym = exp->X_add_symbol; + off = exp->X_add_number; + } + else + { + sym = make_expr_symbol(exp); + off = 0; + } + + frag_now->tc_frag_data.reloc_info = current_insn.field_value[0].value; + frag_now->tc_frag_data.relaxer = &avr32_lda_relaxer; + + if (!avr32_pic) + { + /* The relaxer will bump the refcount if necessary */ + frag_now->tc_frag_data.pool + = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0); + } + + frag_var(rs_machine_dependent, max_size - initial_size, + initial_size, initial_subtype, sym, off, buf); + + return NULL; +} + +static const char * +finish_call(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED) +{ + expressionS *exp = ¤t_insn.immediate; + symbolS *sym; + offsetT off; + int initial_size, max_size; + char *buf; + + initial_size = CALL_INITIAL_SIZE; + + if (avr32_pic) + { + if (linkrelax) + max_size = 10; + else + max_size = 4; + } + else + max_size = 4; + + frag_grow(max_size); + buf = frag_more(initial_size); + dwarf2_emit_insn(initial_size); + + frag_now->tc_frag_data.relaxer = &avr32_call_relaxer; + + if (exp->X_op == O_symbol) + { + sym = exp->X_add_symbol; + off = exp->X_add_number; + } + else + { + sym = make_expr_symbol(exp); + off = 0; + } + + if (!avr32_pic) + { + /* The relaxer will bump the refcount if necessary */ + frag_now->tc_frag_data.pool + = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0); + } + + frag_var(rs_machine_dependent, max_size - initial_size, + initial_size, CALL_SUBTYPE_RCALL1, sym, off, buf); + + return NULL; +} + +void +md_begin (void) +{ + unsigned long flags = 0; + int i; + + avr32_mnemonic_htab = hash_new(); + + if (!avr32_mnemonic_htab) + as_fatal(_("virtual memory exhausted")); + + for (i = 0; i < AVR32_NR_MNEMONICS; i++) + { + hash_insert(avr32_mnemonic_htab, avr32_mnemonic_table[i].name, + (void *)&avr32_mnemonic_table[i]); + } + + if (linkrelax) + flags |= EF_AVR32_LINKRELAX; + if (avr32_pic) + flags |= EF_AVR32_PIC; + + bfd_set_private_flags(stdoutput, flags); + +#ifdef OPC_CONSISTENCY_CHECK + if (sizeof(avr32_operand_table)/sizeof(avr32_operand_table[0]) + < AVR32_NR_OPERANDS) + as_fatal(_("operand table is incomplete")); + + for (i = 0; i < AVR32_NR_OPERANDS; i++) + if (avr32_operand_table[i].id != i) + as_fatal(_("operand table inconsistency found at index %d\n"), i); + pr_debug("%d operands verified\n", AVR32_NR_OPERANDS); + + for (i = 0; i < AVR32_NR_IFIELDS; i++) + if (avr32_ifield_table[i].id != i) + as_fatal(_("ifield table inconsistency found at index %d\n"), i); + pr_debug("%d instruction fields verified\n", AVR32_NR_IFIELDS); + + for (i = 0; i < AVR32_NR_OPCODES; i++) + { + if (avr32_opc_table[i].id != i) + as_fatal(_("opcode table inconsistency found at index %d\n"), i); + if ((avr32_opc_table[i].var_field == -1 + && avr32_relax_table[i].length != 0) + || (avr32_opc_table[i].var_field != -1 + && avr32_relax_table[i].length == 0)) + as_fatal(_("relax table inconsistency found at index %d\n"), i); + } + pr_debug("%d opcodes verified\n", AVR32_NR_OPCODES); + + for (i = 0; i < AVR32_NR_SYNTAX; i++) + if (avr32_syntax_table[i].id != i) + as_fatal(_("syntax table inconsistency found at index %d\n"), i); + pr_debug("%d syntax variants verified\n", AVR32_NR_SYNTAX); + + for (i = 0; i < AVR32_NR_ALIAS; i++) + if (avr32_alias_table[i].id != i) + as_fatal(_("alias table inconsistency found at index %d\n"), i); + pr_debug("%d aliases verified\n", AVR32_NR_ALIAS); + + for (i = 0; i < AVR32_NR_MNEMONICS; i++) + if (avr32_mnemonic_table[i].id != i) + as_fatal(_("mnemonic table inconsistency found at index %d\n"), i); + pr_debug("%d mnemonics verified\n", AVR32_NR_MNEMONICS); +#endif +} + +void +md_assemble (char *str) +{ + struct avr32_mnemonic *mnemonic; + char *p, c; + + memset(¤t_insn, 0, sizeof(current_insn)); + current_insn.immediate.X_op = O_constant; + + skip_whitespace(str); + for (p = str; *p; p++) + if (*p == ' ') + break; + c = *p; + *p = 0; + + mnemonic = hash_find(avr32_mnemonic_htab, str); + *p = c; + if (c) p++; + + if (mnemonic) + { + const struct avr32_syntax *syntax; + + for (syntax = mnemonic->syntax; syntax; syntax = syntax->next) + { + const char *errmsg = NULL; + + if (syntax_matches(syntax, p)) + { + if (!(syntax->isa_flags & avr32_cpu->isa_flags)) + { + as_bad(_("Selected cpu `%s' does not support `%s'"), + avr32_cpu->name, str); + return; + } + + current_insn.syntax = syntax; + parse_operands(p); + + switch (syntax->type) + { + case AVR32_PARSER_NORMAL: + errmsg = finish_insn(syntax->u.opc); + break; + case AVR32_PARSER_ALIAS: + errmsg = finish_alias(syntax->u.alias); + break; + case AVR32_PARSER_LDA: + errmsg = finish_lda(syntax); + break; + case AVR32_PARSER_CALL: + errmsg = finish_call(syntax); + break; + default: + BAD_CASE(syntax->type); + break; + } + + if (errmsg) + as_bad("%s in `%s'", errmsg, str); + + return; + } + } + + as_bad(_("unrecognized form of instruction: `%s'"), str); + } + else + as_bad(_("unrecognized instruction `%s'"), str); +} + +void avr32_cleanup(void) +{ + struct cpool *pool; + + /* Emit any constant pools that haven't been explicitly flushed with + a .cpool directive. */ + for (pool = cpool_list; pool; pool = pool->next) + { + subseg_set(pool->section, pool->sub_section); + s_cpool(0); + } +} + +/* Handle any PIC-related operands in data allocation pseudo-ops */ +void +avr32_cons_fix_new (fragS *frag, int off, int size, expressionS *exp) +{ + bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED; + int pcrel = 0; + + pr_debug("%s:%u: cons_fix_new, add_sym: %s, op_sym: %s, op: %d, add_num: %d\n", + frag->fr_file, frag->fr_line, + exp->X_add_symbol?S_GET_NAME(exp->X_add_symbol):"(none)", + exp->X_op_symbol?S_GET_NAME(exp->X_op_symbol):"(none)", + exp->X_op, exp->X_add_number); + + if (exp->X_op == O_subtract && exp->X_op_symbol) + { + if (exp->X_op_symbol == GOT_symbol) + { + if (size != 4) + goto bad_size; + r_type = BFD_RELOC_AVR32_GOTPC; + exp->X_op = O_symbol; + exp->X_op_symbol = NULL; + } + } + else if (exp->X_op == O_got) + { + switch (size) + { + case 1: + r_type = BFD_RELOC_AVR32_GOT8; + break; + case 2: + r_type = BFD_RELOC_AVR32_GOT16; + break; + case 4: + r_type = BFD_RELOC_AVR32_GOT32; + break; + default: + goto bad_size; + } + + exp->X_op = O_symbol; + } + + if (r_type == BFD_RELOC_UNUSED) + switch (size) + { + case 1: + r_type = BFD_RELOC_8; + break; + case 2: + r_type = BFD_RELOC_16; + break; + case 4: + r_type = BFD_RELOC_32; + break; + default: + goto bad_size; + } + else if (size != 4) + { + bad_size: + as_bad(_("unsupported BFD relocation size %u"), size); + r_type = BFD_RELOC_UNUSED; + } + + fix_new_exp (frag, off, size, exp, pcrel, r_type); +} + +static void +avr32_frob_section(bfd *abfd ATTRIBUTE_UNUSED, segT sec, + void *ignore ATTRIBUTE_UNUSED) +{ + segment_info_type *seginfo; + fixS *fix; + + seginfo = seg_info(sec); + if (!seginfo) + return; + + for (fix = seginfo->fix_root; fix; fix = fix->fx_next) + { + if (fix->fx_done) + continue; + + if (fix->fx_r_type == BFD_RELOC_AVR32_SUB5 + && fix->fx_addsy && fix->fx_subsy) + { + if (S_GET_SEGMENT(fix->fx_addsy) != S_GET_SEGMENT(fix->fx_subsy) + || linkrelax) + { + symbolS *tmp; +#ifdef DEBUG + fprintf(stderr, "Swapping symbols in fixup:\n"); + print_fixup(fix); +#endif + tmp = fix->fx_addsy; + fix->fx_addsy = fix->fx_subsy; + fix->fx_subsy = tmp; + fix->fx_offset = -fix->fx_offset; + } + } + } +} + +/* We need to look for SUB5 instructions with expressions that will be + made PC-relative and switch fx_addsy with fx_subsy. This has to be + done before adjustment or the wrong symbol might be adjusted. + + This applies to fixups that are a result of expressions like -(sym + - .) and that will make it all the way to md_apply_fix3(). LDA + does the right thing in convert_frag, so we must not convert + those. */ +void +avr32_frob_file(void) +{ + /* if (1 || !linkrelax) + return; */ + + bfd_map_over_sections(stdoutput, avr32_frob_section, NULL); +} + +static bfd_boolean +convert_to_diff_reloc(fixS *fixP) +{ + switch (fixP->fx_r_type) + { + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32; + break; + case BFD_RELOC_16: + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF16; + break; + case BFD_RELOC_8: + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF8; + break; + default: + return FALSE; + } + + return TRUE; +} + +/* Simplify a fixup. If possible, the fixup is reduced to a single + constant which is written to the output file. Otherwise, a + relocation is generated so that the linker can take care of the + rest. + + ELF relocations have certain constraints: They can only take a + single symbol and a single addend. This means that for difference + expressions, we _must_ get rid of the fx_subsy symbol somehow. + + The difference between two labels in the same section can be + calculated directly unless 'linkrelax' is set, or a relocation is + forced. If so, we must emit a R_AVR32_DIFFxx relocation. If there + are addends involved at this point, we must be especially careful + as the relocation must point exactly to the symbol being + subtracted. + + When subtracting a symbol defined in the same section as the fixup, + we might be able to convert it to a PC-relative expression, unless + linkrelax is set. If this is the case, there's no way we can make + sure that the difference between the fixup and fx_subsy stays + constant. So for now, we're just going to disallow that. + */ +void +avr32_process_fixup(fixS *fixP, segT this_segment) +{ + segT add_symbol_segment = absolute_section; + segT sub_symbol_segment = absolute_section; + symbolS *fx_addsy, *fx_subsy; + offsetT value = 0, fx_offset; + bfd_boolean apply = FALSE; + + assert(this_segment != absolute_section); + + if (fixP->fx_r_type >= BFD_RELOC_UNUSED) + { + as_bad_where(fixP->fx_file, fixP->fx_line, + _("Bad relocation type %d\n"), fixP->fx_r_type); + return; + } + + /* BFD_RELOC_AVR32_SUB5 fixups have been swapped by avr32_frob_section() */ + fx_addsy = fixP->fx_addsy; + fx_subsy = fixP->fx_subsy; + fx_offset = fixP->fx_offset; + + if (fx_addsy) + add_symbol_segment = S_GET_SEGMENT(fx_addsy); + + if (fx_subsy) + { + resolve_symbol_value(fx_subsy); + sub_symbol_segment = S_GET_SEGMENT(fx_subsy); + + if (sub_symbol_segment == this_segment + && (!linkrelax + || S_GET_VALUE(fx_subsy) == (fixP->fx_frag->fr_address + + fixP->fx_dot_value))) + { + fixP->fx_pcrel = TRUE; + fx_offset += (fixP->fx_frag->fr_address + fixP->fx_dot_value + - S_GET_VALUE(fx_subsy)); + fx_subsy = NULL; + } + else if (sub_symbol_segment == absolute_section) + { + /* The symbol is really a constant. */ + fx_offset -= S_GET_VALUE(fx_subsy); + fx_subsy = NULL; + } + else if (SEG_NORMAL(add_symbol_segment) + && sub_symbol_segment == add_symbol_segment + && (!linkrelax || convert_to_diff_reloc(fixP))) + { + /* Difference between two labels in the same section. */ + if (linkrelax) + { + /* convert_to_diff() has ensured that the reloc type is + either DIFF32, DIFF16 or DIFF8. */ + value = (S_GET_VALUE(fx_addsy) + fixP->fx_offset + - S_GET_VALUE(fx_subsy)); + + /* Try to convert it to a section symbol if possible */ + if (!S_FORCE_RELOC(fx_addsy, 1) + && !(sub_symbol_segment->flags & SEC_THREAD_LOCAL)) + { + fx_offset = S_GET_VALUE(fx_subsy); + fx_addsy = section_symbol(sub_symbol_segment); + } + else + { + fx_addsy = fx_subsy; + fx_offset = 0; + } + + fx_subsy = NULL; + apply = TRUE; + } + else + { + fx_offset += S_GET_VALUE(fx_addsy); + fx_offset -= S_GET_VALUE(fx_subsy); + fx_addsy = NULL; + fx_subsy = NULL; + } + } + else + { + as_bad_where(fixP->fx_file, fixP->fx_line, + _("can't resolve `%s' {%s section} - `%s' {%s section}"), + fx_addsy ? S_GET_NAME (fx_addsy) : "0", + segment_name (add_symbol_segment), + S_GET_NAME (fx_subsy), + segment_name (sub_symbol_segment)); + return; + } + } + + if (fx_addsy && !TC_FORCE_RELOCATION(fixP)) + { + if (add_symbol_segment == this_segment + && fixP->fx_pcrel) + { + value += S_GET_VALUE(fx_addsy); + value -= md_pcrel_from_section(fixP, this_segment); + fx_addsy = NULL; + fixP->fx_pcrel = FALSE; + } + else if (add_symbol_segment == absolute_section) + { + fx_offset += S_GET_VALUE(fixP->fx_addsy); + fx_addsy = NULL; + } + } + + if (!fx_addsy) + fixP->fx_done = TRUE; + + if (fixP->fx_pcrel) + { + if (fx_addsy != NULL + && S_IS_DEFINED(fx_addsy) + && S_GET_SEGMENT(fx_addsy) != this_segment) + value += md_pcrel_from_section(fixP, this_segment); + + switch (fixP->fx_r_type) + { + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_32_PCREL; + break; + case BFD_RELOC_16: + fixP->fx_r_type = BFD_RELOC_16_PCREL; + break; + case BFD_RELOC_8: + fixP->fx_r_type = BFD_RELOC_8_PCREL; + break; + case BFD_RELOC_AVR32_SUB5: + fixP->fx_r_type = BFD_RELOC_AVR32_16N_PCREL; + break; + case BFD_RELOC_AVR32_16S: + fixP->fx_r_type = BFD_RELOC_AVR32_16B_PCREL; + break; + case BFD_RELOC_AVR32_14UW: + fixP->fx_r_type = BFD_RELOC_AVR32_14UW_PCREL; + break; + case BFD_RELOC_AVR32_10UW: + fixP->fx_r_type = BFD_RELOC_AVR32_10UW_PCREL; + break; + default: + /* Should have been taken care of already */ + break; + } + } + + if (fixP->fx_done || apply) + { + const struct avr32_ifield *ifield; + char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; + + if (fixP->fx_done) + value += fx_offset; + + switch (fixP->fx_r_type) + { + case BFD_RELOC_32: + case BFD_RELOC_16: + case BFD_RELOC_8: + case BFD_RELOC_AVR32_DIFF32: + case BFD_RELOC_AVR32_DIFF16: + case BFD_RELOC_AVR32_DIFF8: + md_number_to_chars(buf, value, fixP->fx_size); + break; + case BFD_RELOC_HI16: + value >>= 16; + case BFD_RELOC_LO16: + value &= 0xffff; + md_number_to_chars(buf + 2, value, 2); + break; + case BFD_RELOC_AVR32_16N_PCREL: + value = -value; + /* fall through */ + case BFD_RELOC_AVR32_22H_PCREL: + case BFD_RELOC_AVR32_18W_PCREL: + case BFD_RELOC_AVR32_16B_PCREL: + case BFD_RELOC_AVR32_11H_PCREL: + case BFD_RELOC_AVR32_9H_PCREL: + case BFD_RELOC_AVR32_9UW_PCREL: + case BFD_RELOC_AVR32_3U: + case BFD_RELOC_AVR32_4UH: + case BFD_RELOC_AVR32_6UW: + case BFD_RELOC_AVR32_6S: + case BFD_RELOC_AVR32_7UW: + case BFD_RELOC_AVR32_8S_EXT: + case BFD_RELOC_AVR32_8S: + case BFD_RELOC_AVR32_10UW: + case BFD_RELOC_AVR32_10SW: + case BFD_RELOC_AVR32_STHH_W: + case BFD_RELOC_AVR32_14UW: + case BFD_RELOC_AVR32_16S: + case BFD_RELOC_AVR32_16U: + case BFD_RELOC_AVR32_21S: + case BFD_RELOC_AVR32_SUB5: + case BFD_RELOC_AVR32_CPCALL: + case BFD_RELOC_AVR32_16_CP: + case BFD_RELOC_AVR32_9W_CP: + ifield = fixP->tc_fix_data.ifield; + pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n", + fixP->tc_fix_data.min, value, fixP->tc_fix_data.max, + fixP->tc_fix_data.align); + if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max) + as_bad_where(fixP->fx_file, fixP->fx_line, + _("operand out of range (%ld not between %ld and %ld)"), + value, fixP->tc_fix_data.min, fixP->tc_fix_data.max); + if (value & ((1 << fixP->tc_fix_data.align) - 1)) + as_bad_where(fixP->fx_file, fixP->fx_line, + _("misaligned operand (required alignment: %d)"), + 1 << fixP->tc_fix_data.align); + ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align); + break; + case BFD_RELOC_AVR32_ALIGN: + /* Nothing to do */ + fixP->fx_done = FALSE; + break; + default: + as_fatal("reloc type %s not handled\n", + bfd_get_reloc_code_name(fixP->fx_r_type)); + } + } + + fixP->fx_addsy = fx_addsy; + fixP->fx_subsy = fx_subsy; + fixP->fx_offset = fx_offset; + + if (!fixP->fx_done) + { + if (!fixP->fx_addsy) + fixP->fx_addsy = abs_section_sym; + + symbol_mark_used_in_reloc(fixP->fx_addsy); + if (fixP->fx_subsy) + abort(); + } +} + +#if 0 +void +md_apply_fix3 (fixS *fixP, valueT *valP, segT seg) +{ + const struct avr32_ifield *ifield; + offsetT value = *valP; + char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; + bfd_boolean apply; + + pr_debug("%s:%u: apply_fix3: r_type=%d value=%lx offset=%lx\n", + fixP->fx_file, fixP->fx_line, fixP->fx_r_type, *valP, + fixP->fx_offset); + + if (fixP->fx_r_type >= BFD_RELOC_UNUSED) + { + as_bad_where(fixP->fx_file, fixP->fx_line, + _("Bad relocation type %d\n"), fixP->fx_r_type); + return; + } + + if (!fixP->fx_addsy && !fixP->fx_subsy) + fixP->fx_done = 1; + + if (fixP->fx_pcrel) + { + if (fixP->fx_addsy != NULL + && S_IS_DEFINED(fixP->fx_addsy) + && S_GET_SEGMENT(fixP->fx_addsy) != seg) + value += md_pcrel_from_section(fixP, seg); + + switch (fixP->fx_r_type) + { + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_32_PCREL; + break; + case BFD_RELOC_16: + case BFD_RELOC_8: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("8- and 16-bit PC-relative relocations not supported")); + break; + case BFD_RELOC_AVR32_SUB5: + fixP->fx_r_type = BFD_RELOC_AVR32_PCREL_SUB5; + break; + case BFD_RELOC_AVR32_16S: + fixP->fx_r_type = BFD_RELOC_AVR32_16_PCREL; + break; + default: + /* Should have been taken care of already */ + break; + } + } + + if (fixP->fx_r_type == BFD_RELOC_32 + && fixP->fx_subsy) + { + fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32; + + /* Offsets are only allowed if it's a result of adjusting a + local symbol into a section-relative offset. + tc_fix_adjustable() should prevent any adjustment if there + was an offset involved before. */ + if (fixP->fx_offset && !symbol_section_p(fixP->fx_addsy)) + as_bad_where(fixP->fx_file, fixP->fx_line, + _("cannot represent symbol difference with an offset")); + + value = (S_GET_VALUE(fixP->fx_addsy) + fixP->fx_offset + - S_GET_VALUE(fixP->fx_subsy)); + + /* The difference before any relaxing takes place is written + out, and the DIFF32 reloc identifies the address of the first + symbol (i.e. the on that's subtracted.) */ + *valP = value; + fixP->fx_offset -= value; + fixP->fx_subsy = NULL; + + md_number_to_chars(buf, value, fixP->fx_size); + } + + if (fixP->fx_done) + { + switch (fixP->fx_r_type) + { + case BFD_RELOC_8: + case BFD_RELOC_16: + case BFD_RELOC_32: + md_number_to_chars(buf, value, fixP->fx_size); + break; + case BFD_RELOC_HI16: + value >>= 16; + case BFD_RELOC_LO16: + value &= 0xffff; + *valP = value; + md_number_to_chars(buf + 2, value, 2); + break; + case BFD_RELOC_AVR32_PCREL_SUB5: + value = -value; + /* fall through */ + case BFD_RELOC_AVR32_9_PCREL: + case BFD_RELOC_AVR32_11_PCREL: + case BFD_RELOC_AVR32_16_PCREL: + case BFD_RELOC_AVR32_18_PCREL: + case BFD_RELOC_AVR32_22_PCREL: + case BFD_RELOC_AVR32_3U: + case BFD_RELOC_AVR32_4UH: + case BFD_RELOC_AVR32_6UW: + case BFD_RELOC_AVR32_6S: + case BFD_RELOC_AVR32_7UW: + case BFD_RELOC_AVR32_8S: + case BFD_RELOC_AVR32_10UW: + case BFD_RELOC_AVR32_10SW: + case BFD_RELOC_AVR32_14UW: + case BFD_RELOC_AVR32_16S: + case BFD_RELOC_AVR32_16U: + case BFD_RELOC_AVR32_21S: + case BFD_RELOC_AVR32_BRC1: + case BFD_RELOC_AVR32_SUB5: + case BFD_RELOC_AVR32_CPCALL: + case BFD_RELOC_AVR32_16_CP: + case BFD_RELOC_AVR32_9_CP: + ifield = fixP->tc_fix_data.ifield; + pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n", + fixP->tc_fix_data.min, value, fixP->tc_fix_data.max, + fixP->tc_fix_data.align); + if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max) + as_bad_where(fixP->fx_file, fixP->fx_line, + _("operand out of range (%ld not between %ld and %ld)"), + value, fixP->tc_fix_data.min, fixP->tc_fix_data.max); + if (value & ((1 << fixP->tc_fix_data.align) - 1)) + as_bad_where(fixP->fx_file, fixP->fx_line, + _("misaligned operand (required alignment: %d)"), + 1 << fixP->tc_fix_data.align); + ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align); + break; + case BFD_RELOC_AVR32_ALIGN: + /* Nothing to do */ + fixP->fx_done = FALSE; + break; + default: + as_fatal("reloc type %s not handled\n", + bfd_get_reloc_code_name(fixP->fx_r_type)); + } + } +} +#endif + +arelent * +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, + fixS *fixp) +{ + arelent *reloc; + bfd_reloc_code_real_type code; + + reloc = xmalloc (sizeof (arelent)); + + reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc->addend = fixp->fx_offset; + code = fixp->fx_r_type; + + reloc->howto = bfd_reloc_type_lookup (stdoutput, code); + + if (reloc->howto == NULL) + { + as_bad_where (fixp->fx_file, fixp->fx_line, + _("cannot represent relocation %s in this object file format"), + bfd_get_reloc_code_name (code)); + return NULL; + } + + return reloc; +} + +bfd_boolean +avr32_force_reloc(fixS *fixP) +{ + if (linkrelax && fixP->fx_addsy + && !(S_GET_SEGMENT(fixP->fx_addsy)->flags & SEC_DEBUGGING) + && S_GET_SEGMENT(fixP->fx_addsy) != absolute_section) + { + pr_debug(stderr, "force reloc: addsy=%p, r_type=%d, sec=%s\n", + fixP->fx_addsy, fixP->fx_r_type, S_GET_SEGMENT(fixP->fx_addsy)->name); + return 1; + } + + return generic_force_reloc(fixP); +} + +bfd_boolean +avr32_fix_adjustable(fixS *fixP) +{ + switch (fixP->fx_r_type) + { + /* GOT relocations can't have addends since BFD treats all + references to a given symbol the same. This means that we + must avoid section-relative references to local symbols when + dealing with these kinds of relocs */ + case BFD_RELOC_AVR32_GOT32: + case BFD_RELOC_AVR32_GOT16: + case BFD_RELOC_AVR32_GOT8: + case BFD_RELOC_AVR32_GOT21S: + case BFD_RELOC_AVR32_GOT18SW: + case BFD_RELOC_AVR32_GOT16S: + case BFD_RELOC_AVR32_LDA_GOT: + case BFD_RELOC_AVR32_GOTCALL: + pr_debug("fix not adjustable\n"); + return 0; + + default: + break; + } + + return 1; +} + +/* When we want the linker to be able to relax the code, we need to + output a reloc for every .align directive requesting an alignment + to a four byte boundary or larger. If we don't do this, the linker + can't guarantee that the alignment is actually maintained in the + linker output. + + TODO: Might as well insert proper NOPs while we're at it... */ +void +avr32_handle_align(fragS *frag) +{ + if (linkrelax + && frag->fr_type == rs_align_code + && frag->fr_address + frag->fr_fix > 0 + && frag->fr_offset > 0) + { + /* The alignment order (fr_offset) is stored in the addend. */ + fix_new(frag, frag->fr_fix, 2, &abs_symbol, frag->fr_offset, + FALSE, BFD_RELOC_AVR32_ALIGN); + } +} + +/* Relax_align. Advance location counter to next address that has 'alignment' + lowest order bits all 0s, return size of adjustment made. */ +relax_addressT +avr32_relax_align(segT segment ATTRIBUTE_UNUSED, + fragS *fragP, + relax_addressT address) +{ + relax_addressT mask; + relax_addressT new_address; + int alignment; + + alignment = fragP->fr_offset; + mask = ~((~0) << alignment); + new_address = (address + mask) & (~mask); + + return new_address - address; +} + +/* Turn a string in input_line_pointer into a floating point constant + of type type, and store the appropriate bytes in *litP. The number + of LITTLENUMS emitted is stored in *sizeP . An error message is + returned, or NULL on OK. */ + +/* Equal to MAX_PRECISION in atof-ieee.c */ +#define MAX_LITTLENUMS 6 + +char * +md_atof (type, litP, sizeP) +char type; +char * litP; +int * sizeP; +{ + int i; + int prec; + LITTLENUM_TYPE words [MAX_LITTLENUMS]; + char * t; + + switch (type) + { + case 'f': + case 'F': + case 's': + case 'S': + prec = 2; + break; + + case 'd': + case 'D': + case 'r': + case 'R': + prec = 4; + break; + + /* FIXME: Some targets allow other format chars for bigger sizes here. */ + + default: + * sizeP = 0; + return _("Bad call to md_atof()"); + } + + t = atof_ieee (input_line_pointer, type, words); + if (t) + input_line_pointer = t; + * sizeP = prec * sizeof (LITTLENUM_TYPE); + + for (i = 0; i < prec; i++) + { + md_number_to_chars (litP, (valueT) words[i], + sizeof (LITTLENUM_TYPE)); + litP += sizeof (LITTLENUM_TYPE); + } + + return 0; +} + +static char *avr32_end_of_match(char *cont, char *what) +{ + int len = strlen (what); + + if (! is_part_of_name (cont[len]) + && strncasecmp (cont, what, len) == 0) + return cont + len; + + return NULL; +} + +int +avr32_parse_name (char const *name, expressionS *exp, char *nextchar) +{ + char *next = input_line_pointer; + char *next_end; + + pr_debug("parse_name: %s, nextchar=%c (%02x)\n", name, *nextchar, *nextchar); + + if (*nextchar == '(') + { + if (strcasecmp(name, "hi") == 0) + { + *next = *nextchar; + + expression(exp); + + if (exp->X_op == O_constant) + { + pr_debug(" -> constant hi(0x%08lx) -> 0x%04lx\n", + exp->X_add_number, exp->X_add_number >> 16); + exp->X_add_number = (exp->X_add_number >> 16) & 0xffff; + } + else + { + exp->X_md = exp->X_op; + exp->X_op = O_hi; + } + + return 1; + } + else if (strcasecmp(name, "lo") == 0) + { + *next = *nextchar; + + expression(exp); + + if (exp->X_op == O_constant) + exp->X_add_number &= 0xffff; + else + { + exp->X_md = exp->X_op; + exp->X_op = O_lo; + } + + return 1; + } + } + else if (*nextchar == '@') + { + exp->X_md = exp->X_op; + + if ((next_end = avr32_end_of_match (next + 1, "got"))) + exp->X_op = O_got; + else if ((next_end = avr32_end_of_match (next + 1, "tlsgd"))) + exp->X_op = O_tlsgd; + /* Add more as needed */ + else + { + char c; + input_line_pointer++; + c = get_symbol_end(); + as_bad (_("unknown relocation override `%s'"), next + 1); + *input_line_pointer = c; + input_line_pointer = next; + return 0; + } + + exp->X_op_symbol = NULL; + exp->X_add_symbol = symbol_find_or_make (name); + exp->X_add_number = 0; + + *input_line_pointer = *nextchar; + input_line_pointer = next_end; + *nextchar = *input_line_pointer; + *input_line_pointer = '\0'; + return 1; + } + else if (strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0) + { + if (!GOT_symbol) + GOT_symbol = symbol_find_or_make(name); + + exp->X_add_symbol = GOT_symbol; + exp->X_op = O_symbol; + exp->X_add_number = 0; + return 1; + } + + return 0; +} + +static void +s_rseg (int value ATTRIBUTE_UNUSED) +{ + /* Syntax: RSEG segment_name [:type] [NOROOT|ROOT] [(align)] + * Defaults: + * - type: undocumented ("typically CODE or DATA") + * - ROOT + * - align: 1 for code, 0 for others + * + * TODO: NOROOT is ignored. If gas supports discardable segments, it should + * be implemented. + */ + char *name, *end; + int length, type, attr; + int align = 0; + + SKIP_WHITESPACE(); + + end = input_line_pointer; + while (0 == strchr ("\n\t;:( ", *end)) + end++; + if (end == input_line_pointer) + { + as_warn (_("missing name")); + ignore_rest_of_line(); + return; + } + + name = xmalloc (end - input_line_pointer + 1); + memcpy (name, input_line_pointer, end - input_line_pointer); + name[end - input_line_pointer] = '\0'; + input_line_pointer = end; + + SKIP_WHITESPACE(); + + type = SHT_NULL; + attr = 0; + + if (*input_line_pointer == ':') + { + /* Skip the colon */ + ++input_line_pointer; + SKIP_WHITESPACE(); + + /* Possible options at this point: + * - flag (ROOT or NOROOT) + * - a segment type + */ + end = input_line_pointer; + while (0 == strchr ("\n\t;:( ", *end)) + end++; + length = end - input_line_pointer; + if (((length == 4) && (0 == strncasecmp( input_line_pointer, "ROOT", 4))) || + ((length == 6) && (0 == strncasecmp( input_line_pointer, "NOROOT", 6)))) + { + /* Ignore ROOT/NOROOT */ + input_line_pointer = end; + } + else + { + /* Must be a segment type */ + switch (*input_line_pointer) + { + case 'C': + case 'c': + if ((length == 4) && + (0 == strncasecmp (input_line_pointer, "CODE", 4))) + { + attr |= SHF_ALLOC | SHF_EXECINSTR; + type = SHT_PROGBITS; + align = 1; + break; + } + if ((length == 5) && + (0 == strncasecmp (input_line_pointer, "CONST", 5))) + { + attr |= SHF_ALLOC; + type = SHT_PROGBITS; + break; + } + goto de_fault; + + case 'D': + case 'd': + if ((length == 4) && + (0 == strncasecmp (input_line_pointer, "DATA", 4))) + { + attr |= SHF_ALLOC | SHF_WRITE; + type = SHT_PROGBITS; + break; + } + goto de_fault; + + /* TODO: Add FAR*, HUGE*, IDATA and NEAR* if necessary */ + + case 'U': + case 'u': + if ((length == 7) && + (0 == strncasecmp (input_line_pointer, "UNTYPED", 7))) + break; + goto de_fault; + + /* TODO: Add XDATA and ZPAGE if necessary */ + + de_fault: + default: + as_warn (_("unrecognized segment type")); + } + + input_line_pointer = end; + SKIP_WHITESPACE(); + + if (*input_line_pointer == ':') + { + /* ROOT/NOROOT */ + ++input_line_pointer; + SKIP_WHITESPACE(); + + end = input_line_pointer; + while (0 == strchr ("\n\t;:( ", *end)) + end++; + length = end - input_line_pointer; + if (! ((length == 4) && + (0 == strncasecmp( input_line_pointer, "ROOT", 4))) && + ! ((length == 6) && + (0 == strncasecmp( input_line_pointer, "NOROOT", 6)))) + { + as_warn (_("unrecognized segment flag")); + } + + input_line_pointer = end; + SKIP_WHITESPACE(); + } + } + } + + if (*input_line_pointer == '(') + { + align = get_absolute_expression (); + } + + demand_empty_rest_of_line(); + + obj_elf_change_section (name, type, attr, 0, NULL, 0, 0); +#ifdef AVR32_DEBUG + fprintf( stderr, "RSEG: Changed section to %s, type: 0x%x, attr: 0x%x\n", + name, type, attr ); + fprintf( stderr, "RSEG: Aligning to 2**%d\n", align ); +#endif + + if (align > 15) + { + align = 15; + as_warn (_("alignment too large: %u assumed"), align); + } + + /* Hope not, that is */ + assert (now_seg != absolute_section); + + /* Only make a frag if we HAVE to... */ + if (align != 0 && !need_pass_2) + { + if (subseg_text_p (now_seg)) + frag_align_code (align, 0); + else + frag_align (align, 0, 0); + } + + record_alignment (now_seg, align - OCTETS_PER_BYTE_POWER); +} + +/* vim: syntax=c sw=2 + */ Index: binutils-2.16.1-avr32/gas/config/tc-avr32.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/gas/config/tc-avr32.h 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,317 @@ +/* Assembler definitions for AVR32. + Copyright 2003-2006 Atmel Corporation. + + Written by Haavard Skinnemoen, Atmel Norway, + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef BFD_ASSEMBLER + #error AVR32 support requires BFD_ASSEMBLER +#endif + +#if 0 +#define DEBUG +#define DEBUG1 +#define DEBUG2 +#define DEBUG3 +#define DEBUG4 +#define DEBUG5 +#endif + +/* Are we trying to be compatible with the IAR assembler? (--iar) */ +extern int avr32_iarcompat; + +/* By convention, you should define this macro in the `.h' file. For + example, `tc-m68k.h' defines `TC_M68K'. You might have to use this + if it is necessary to add CPU specific code to the object format + file. */ +#define TC_AVR32 + +/* This macro is the BFD target name to use when creating the output + file. This will normally depend upon the `OBJ_FMT' macro. */ +#define TARGET_FORMAT "elf32-avr32" + +/* This macro is the BFD architecture to pass to `bfd_set_arch_mach'. */ +#define TARGET_ARCH bfd_arch_avr32 + +/* This macro is the BFD machine number to pass to + `bfd_set_arch_mach'. If it is not defined, GAS will use 0. */ +#define TARGET_MACH 0 + +/* UNDOCUMENTED: Allow //-style comments */ +#define DOUBLESLASH_LINE_COMMENTS + +/* You should define this macro to be non-zero if the target is big + endian, and zero if the target is little endian. */ +#define TARGET_BYTES_BIG_ENDIAN 1 + +/* FIXME: It seems that GAS only expects a one-byte opcode... + #define NOP_OPCODE 0xd703 */ + +/* If you define this macro, GAS will warn about the use of + nonstandard escape sequences in a string. */ +#undef ONLY_STANDARD_ESCAPES + +#define DWARF2_FORMAT() dwarf2_format_32bit + +/* Instructions are either 2 or 4 bytes long */ +/* #define DWARF2_LINE_MIN_INSN_LENGTH 2 */ + +/* GAS will call this function for any expression that can not be + recognized. When the function is called, `input_line_pointer' + will point to the start of the expression. */ +#define md_operand(x) + +#define md_parse_name(name, expr, c) avr32_parse_name(name, expr, c) +extern int avr32_parse_name(const char *, struct expressionS *, char *); + +/* You may define this macro to generate a fixup for a data + allocation pseudo-op. */ +#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \ + avr32_cons_fix_new(FRAG, OFF, LEN, EXP) +void avr32_cons_fix_new (fragS *, int, int, expressionS *); + +/* `extsym - .' expressions can be emitted using PC-relative relocs */ +#define DIFF_EXPR_OK + +/* This is used to construct expressions out of @gotoff, etc. The + relocation type is stored in X_md */ +#define O_got O_md1 +#define O_hi O_md2 +#define O_lo O_md3 +#define O_tlsgd O_md4 + +/* You may define this macro to parse an expression used in a data + allocation pseudo-op such as `.word'. You can use this to + recognize relocation directives that may appear in such directives. */ +/* #define TC_PARSE_CONS_EXPRESSION(EXPR,N) avr_parse_cons_expression (EXPR,N) + void avr_parse_cons_expression (expressionS *exp, int nbytes); */ + +/* This should just call either `number_to_chars_bigendian' or + `number_to_chars_littleendian', whichever is appropriate. On + targets like the MIPS which support options to change the + endianness, which function to call is a runtime decision. On + other targets, `md_number_to_chars' can be a simple macro. */ +#define md_number_to_chars number_to_chars_bigendian + +/* `md_short_jump_size' + `md_long_jump_size' + `md_create_short_jump' + `md_create_long_jump' + If `WORKING_DOT_WORD' is defined, GAS will not do broken word + processing (*note Broken words::.). Otherwise, you should set + `md_short_jump_size' to the size of a short jump (a jump that is + just long enough to jump around a long jmp) and + `md_long_jump_size' to the size of a long jump (a jump that can go + anywhere in the function), You should define + `md_create_short_jump' to create a short jump around a long jump, + and define `md_create_long_jump' to create a long jump. */ +#define WORKING_DOT_WORD + +/* If you define this macro, it means that `tc_gen_reloc' may return + multiple relocation entries for a single fixup. In this case, the + return value of `tc_gen_reloc' is a pointer to a null terminated + array. */ +#undef RELOC_EXPANSION_POSSIBLE + +/* If you define this macro, GAS will not require pseudo-ops to start with a . + character. */ +#define NO_PSEUDO_DOT (avr32_iarcompat) + +/* The IAR assembler uses $ as the location counter. Unfortunately, we + can't make this dependent on avr32_iarcompat... */ +#define DOLLAR_DOT + +/* Values passed to md_apply_fix3 don't include the symbol value. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + +/* The number of bytes to put into a word in a listing. This affects + the way the bytes are clumped together in the listing. For + example, a value of 2 might print `1234 5678' where a value of 1 + would print `12 34 56 78'. The default value is 4. */ +#define LISTING_WORD_SIZE 4 + +/* extern const struct relax_type md_relax_table[]; +#define TC_GENERIC_RELAX_TABLE md_relax_table */ + +/* + An `.lcomm' directive with no explicit alignment parameter will use + this macro to set P2VAR to the alignment that a request for SIZE + bytes will have. The alignment is expressed as a power of two. If + no alignment should take place, the macro definition should do + nothing. Some targets define a `.bss' directive that is also + affected by this macro. The default definition will set P2VAR to + the truncated power of two of sizes up to eight bytes. + + We want doublewords to be word-aligned, so we're going to modify the + default definition a tiny bit. +*/ +#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR) \ + do \ + { \ + if ((SIZE) >= 4) \ + (P2VAR) = 2; \ + else if ((SIZE) >= 2) \ + (P2VAR) = 1; \ + else \ + (P2VAR) = 0; \ + } \ + while (0) + +/* When relaxing, we need to generate relocations for alignment + directives. */ +#define HANDLE_ALIGN(frag) avr32_handle_align(frag) +extern void avr32_handle_align(fragS *); + +/* See internals doc for explanation. Oh wait... + Now, can you guess where "alignment" comes from? ;-) */ +#define MAX_MEM_FOR_RS_ALIGN_CODE ((1 << alignment) - 1) + +/* We need to stop gas from reducing certain expressions (e.g. GOT + references) */ +#define tc_fix_adjustable(fix) avr32_fix_adjustable(fix) +extern bfd_boolean avr32_fix_adjustable(struct fix *); + +/* The linker needs to be passed a little more information when relaxing. */ +#define TC_FORCE_RELOCATION(fix) avr32_force_reloc(fix) +extern bfd_boolean avr32_force_reloc(struct fix *); + +/* I'm tired of working around all the madness in fixup_segment(). + This hook will do basically the same things as the generic code, + and then it will "goto" right past it. */ +#define TC_VALIDATE_FIX(FIX, SEG, SKIP) \ + do \ + { \ + avr32_process_fixup(FIX, SEG); \ + if (!(FIX)->fx_done) \ + ++seg_reloc_count; \ + goto SKIP; \ + } \ + while (0) +extern void avr32_process_fixup(struct fix *fixP, segT this_segment); + +/* We don't want the gas core to make any assumptions about our way of + doing linkrelaxing. */ +#define TC_LINKRELAX_FIXUP(SEG) 0 + +/* ... but we do want it to insert lots of padding. */ +#define LINKER_RELAXING_SHRINKS_ONLY + +/* Better do it ourselves, really... */ +#define TC_RELAX_ALIGN(SEG, FRAG, ADDR) avr32_relax_align(SEG, FRAG, ADDR) +extern relax_addressT +avr32_relax_align(segT segment, fragS *fragP, relax_addressT address); + +/* This is called by write_object_file() just before symbols are + attempted converted into section symbols. */ +#define tc_frob_file_before_adjust() avr32_frob_file() +extern void avr32_frob_file(void); + +/* If you define this macro, GAS will call it at the end of each input + file. */ +#define md_cleanup() avr32_cleanup() +extern void avr32_cleanup(void); + +/* There's an AVR32-specific hack in operand() which creates O_md + expressions when encountering HWRD or LWRD. We need to generate + proper relocs for them */ +/* #define md_cgen_record_fixup_exp avr32_cgen_record_fixup_exp */ + +/* I needed to add an extra hook in gas_cgen_finish_insn() for + conversion of O_md* operands because md_cgen_record_fixup_exp() + isn't called for relaxable insns */ +/* #define md_cgen_convert_expr(exp, opinfo) avr32_cgen_convert_expr(exp, opinfo) + int avr32_cgen_convert_expr(expressionS *, int); */ + +/* #define tc_gen_reloc gas_cgen_tc_gen_reloc */ + +/* If you define this macro, it should return the position from which + the PC relative adjustment for a PC relative fixup should be + made. On many processors, the base of a PC relative instruction is + the next instruction, so this macro would return the length of an + instruction, plus the address of the PC relative fixup. The latter + can be calculated as fixp->fx_where + fixp->fx_frag->fr_address. */ +extern long md_pcrel_from_section (struct fix *, segT); +#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC) + +#define LOCAL_LABEL(name) (name[0] == '.' && (name[1] == 'L')) +#define LOCAL_LABELS_FB 1 + +struct avr32_relaxer +{ + int (*estimate_size)(fragS *, segT); + long (*relax_frag)(segT, fragS *, long); + void (*convert_frag)(bfd *, segT, fragS *); +}; + +/* AVR32 has quite complex instruction coding, which means we need + * lots of information in order to do the right thing during relaxing + * (basically, we need to be able to reconstruct a whole new opcode if + * necessary) */ +#define TC_FRAG_TYPE struct avr32_frag_data + +struct cpool; + +struct avr32_frag_data +{ + /* TODO: Maybe add an expression object here so that we can use + fix_new_exp() in md_convert_frag? We may have to decide + pcrel-ness in md_estimate_size_before_relax() as well...or we + might do it when parsing. Doing it while parsing may fail + because the sub_symbol is undefined then... */ + int pcrel; + int force_extended; + int reloc_info; + struct avr32_relaxer *relaxer; + expressionS exp; + + /* Points to associated constant pool, for use by LDA and CALL in + non-pic mode, and when relaxing the .cpool directive */ + struct cpool *pool; + unsigned int pool_entry; +}; + +/* We will have to initialize the fields explicitly when needed */ +#define TC_FRAG_INIT(fragP) + +#define md_estimate_size_before_relax(fragP, segT) \ + ((fragP)->tc_frag_data.relaxer->estimate_size(fragP, segT)) +#define md_relax_frag(segment, fragP, stretch) \ + ((fragP)->tc_frag_data.relaxer->relax_frag(segment, fragP, stretch)) +#define md_convert_frag(abfd, segment, fragP) \ + ((fragP)->tc_frag_data.relaxer->convert_frag(abfd, segment, fragP)) + +#define TC_FIX_TYPE struct avr32_fix_data + +struct avr32_fix_data +{ + const struct avr32_ifield *ifield; + unsigned int align; + long min; + long max; +}; + +#define TC_INIT_FIX_DATA(fixP) \ + do \ + { \ + (fixP)->tc_fix_data.ifield = NULL; \ + (fixP)->tc_fix_data.align = 0; \ + (fixP)->tc_fix_data.min = 0; \ + (fixP)->tc_fix_data.max = 0; \ + } \ + while (0) Index: binutils-2.16.1-avr32/gas/configure.tgt =================================================================== --- binutils-2.16.1-avr32.orig/gas/configure.tgt 2006-06-30 09:49:12.000000000 +0200 +++ binutils-2.16.1-avr32/gas/configure.tgt 2006-06-30 09:49:14.000000000 +0200 @@ -34,6 +34,7 @@ case ${cpu} in alpha*) cpu_type=alpha ;; arm*be|arm*b) cpu_type=arm endian=big ;; arm*) cpu_type=arm endian=little ;; + avr32*) cpu_type=avr32 endian=big ;; c4x*) cpu_type=tic4x ;; crisv32) cpu_type=cris arch=crisv32 ;; crx*) cpu_type=crx endian=little ;; @@ -128,6 +129,9 @@ case ${generic_target} in avr-*-*) fmt=elf ;; + avr32-*-linux*) fmt=elf em=linux bfd_gas=yes ;; + avr32*) fmt=elf bfd_gas=yes ;; + cris-*-linux-gnu* | crisv32-*-linux-gnu*) fmt=multi bfd_gas=yes em=linux ;; cris-*-* | crisv32-*-*) fmt=multi bfd_gas=yes ;; Index: binutils-2.16.1-avr32/gas/testsuite/gas/avr32/aliases.d =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/gas/testsuite/gas/avr32/aliases.d 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,19 @@ +#as: +#objdump: -dr +#name: aliases + +.*: +file format .* + +Disassembly of section \.text: + +00000000 : + 0: 19 80 [ \t]+ld\.ub r0,r12\[0x0\] + 2: f9 20 00 00[ \t]+ld\.sb r0,r12\[0\] + 6: 98 80 [ \t]+ld\.uh r0,r12\[0x0\] + 8: 98 00 [ \t]+ld\.sh r0,r12\[0x0\] + a: 78 00 [ \t]+ld\.w r0,r12\[0x0\] + +0000000c : + c: b8 80 [ \t]+st\.b r12\[0x0\],r0 + e: b8 00 [ \t]+st\.h r12\[0x0\],r0 + 10: 99 00 [ \t]+st\.w r12\[0x0\],r0 Index: binutils-2.16.1-avr32/gas/testsuite/gas/avr32/aliases.s =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/gas/testsuite/gas/avr32/aliases.s 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,14 @@ + .text + .global ld_nodisp +ld_nodisp: + ld.ub r0, r12 + ld.sb r0, r12 + ld.uh r0, r12 + ld.sh r0, r12 + ld.w r0, r12 + + .global st_nodisp +st_nodisp: + st.b r12, r0 + st.h r12, r0 + st.w r12, r0 Index: binutils-2.16.1-avr32/gas/testsuite/gas/avr32/allinsn.d =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ binutils-2.16.1-avr32/gas/testsuite/gas/avr32/allinsn.d 2006-06-30 09:49:14.000000000 +0200 @@ -0,0 +1,2900 @@ +#as: +#objdump: -dr +#name: allinsn + +.*: +file format .* + +Disassembly of section \.text: + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 02 3e ld\.d lr,pc\[pc<<0x3\] + *[0-9a-f]*: e0 00 02 00 ld\.d r0,r0\[r0\] + *[0-9a-f]*: ea 05 02 26 ld\.d r6,r5\[r5<<0x2\] + *[0-9a-f]*: e8 04 02 14 ld\.d r4,r4\[r4<<0x1\] + *[0-9a-f]*: fc 0e 02 1e ld\.d lr,lr\[lr<<0x1\] + *[0-9a-f]*: e6 0d 02 2a ld\.d r10,r3\[sp<<0x2\] + *[0-9a-f]*: f4 06 02 28 ld\.d r8,r10\[r6<<0x2\] + *[0-9a-f]*: ee 09 02 02 ld\.d r2,r7\[r9\] + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 03 0f ld\.w pc,pc\[pc\] + *[0-9a-f]*: f8 0c 03 3c ld\.w r12,r12\[r12<<0x3\] + *[0-9a-f]*: ea 05 03 25 ld\.w r5,r5\[r5<<0x2\] + *[0-9a-f]*: e8 04 03 14 ld\.w r4,r4\[r4<<0x1\] + *[0-9a-f]*: fc 0e 03 1e ld\.w lr,lr\[lr<<0x1\] + *[0-9a-f]*: f2 09 03 02 ld\.w r2,r9\[r9\] + *[0-9a-f]*: e4 06 03 0b ld\.w r11,r2\[r6\] + *[0-9a-f]*: e4 0d 03 30 ld\.w r0,r2\[sp<<0x3\] + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 04 0f ld\.sh pc,pc\[pc\] + *[0-9a-f]*: f8 0c 04 3c ld\.sh r12,r12\[r12<<0x3\] + *[0-9a-f]*: ea 05 04 25 ld\.sh r5,r5\[r5<<0x2\] + *[0-9a-f]*: e8 04 04 14 ld\.sh r4,r4\[r4<<0x1\] + *[0-9a-f]*: fc 0e 04 1e ld\.sh lr,lr\[lr<<0x1\] + *[0-9a-f]*: e0 0f 04 2b ld\.sh r11,r0\[pc<<0x2\] + *[0-9a-f]*: fa 06 04 2a ld\.sh r10,sp\[r6<<0x2\] + *[0-9a-f]*: e4 02 04 0c ld\.sh r12,r2\[r2\] + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 05 0f ld\.uh pc,pc\[pc\] + *[0-9a-f]*: f8 0c 05 3c ld\.uh r12,r12\[r12<<0x3\] + *[0-9a-f]*: ea 05 05 25 ld\.uh r5,r5\[r5<<0x2\] + *[0-9a-f]*: e8 04 05 14 ld\.uh r4,r4\[r4<<0x1\] + *[0-9a-f]*: fc 0e 05 1e ld\.uh lr,lr\[lr<<0x1\] + *[0-9a-f]*: fe 0e 05 38 ld\.uh r8,pc\[lr<<0x3\] + *[0-9a-f]*: e2 0f 05 16 ld\.uh r6,r1\[pc<<0x1\] + *[0-9a-f]*: fc 0d 05 16 ld\.uh r6,lr\[sp<<0x1\] + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 06 0f ld\.sb pc,pc\[pc\] + *[0-9a-f]*: f8 0c 06 3c ld\.sb r12,r12\[r12<<0x3\] + *[0-9a-f]*: ea 05 06 25 ld\.sb r5,r5\[r5<<0x2\] + *[0-9a-f]*: e8 04 06 14 ld\.sb r4,r4\[r4<<0x1\] + *[0-9a-f]*: fc 0e 06 1e ld\.sb lr,lr\[lr<<0x1\] + *[0-9a-f]*: e2 0f 06 39 ld\.sb r9,r1\[pc<<0x3\] + *[0-9a-f]*: e6 0b 06 10 ld\.sb r0,r3\[r11<<0x1\] + *[0-9a-f]*: ea 05 06 1a ld\.sb r10,r5\[r5<<0x1\] + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 07 0f ld\.ub pc,pc\[pc\] + *[0-9a-f]*: f8 0c 07 3c ld\.ub r12,r12\[r12<<0x3\] + *[0-9a-f]*: ea 05 07 25 ld\.ub r5,r5\[r5<<0x2\] + *[0-9a-f]*: e8 04 07 14 ld\.ub r4,r4\[r4<<0x1\] + *[0-9a-f]*: fc 0e 07 1e ld\.ub lr,lr\[lr<<0x1\] + *[0-9a-f]*: f8 07 07 36 ld\.ub r6,r12\[r7<<0x3\] + *[0-9a-f]*: ec 0c 07 02 ld\.ub r2,r6\[r12\] + *[0-9a-f]*: ee 0b 07 10 ld\.ub r0,r7\[r11<<0x1\] + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 08 0e st\.d pc\[pc\],lr + *[0-9a-f]*: f8 0c 08 3c st\.d r12\[r12<<0x3\],r12 + *[0-9a-f]*: ea 05 08 26 st\.d r5\[r5<<0x2\],r6 + *[0-9a-f]*: e8 04 08 14 st\.d r4\[r4<<0x1\],r4 + *[0-9a-f]*: fc 0e 08 1e st\.d lr\[lr<<0x1\],lr + *[0-9a-f]*: e2 09 08 14 st\.d r1\[r9<<0x1\],r4 + *[0-9a-f]*: f4 02 08 14 st\.d r10\[r2<<0x1\],r4 + *[0-9a-f]*: f8 06 08 0e st\.d r12\[r6\],lr + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 09 0f st\.w pc\[pc\],pc + *[0-9a-f]*: f8 0c 09 3c st\.w r12\[r12<<0x3\],r12 + *[0-9a-f]*: ea 05 09 25 st\.w r5\[r5<<0x2\],r5 + *[0-9a-f]*: e8 04 09 14 st\.w r4\[r4<<0x1\],r4 + *[0-9a-f]*: fc 0e 09 1e st\.w lr\[lr<<0x1\],lr + *[0-9a-f]*: e2 0a 09 03 st\.w r1\[r10\],r3 + *[0-9a-f]*: e0 0a 09 19 st\.w r0\[r10<<0x1\],r9 + *[0-9a-f]*: e8 05 09 3f st\.w r4\[r5<<0x3\],pc + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 0a 0f st\.h pc\[pc\],pc + *[0-9a-f]*: f8 0c 0a 3c st\.h r12\[r12<<0x3\],r12 + *[0-9a-f]*: ea 05 0a 25 st\.h r5\[r5<<0x2\],r5 + *[0-9a-f]*: e8 04 0a 14 st\.h r4\[r4<<0x1\],r4 + *[0-9a-f]*: fc 0e 0a 1e st\.h lr\[lr<<0x1\],lr + *[0-9a-f]*: e4 09 0a 0b st\.h r2\[r9\],r11 + *[0-9a-f]*: ea 01 0a 2c st\.h r5\[r1<<0x2\],r12 + *[0-9a-f]*: fe 08 0a 23 st\.h pc\[r8<<0x2\],r3 + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 0b 0f st\.b pc\[pc\],pc + *[0-9a-f]*: f8 0c 0b 3c st\.b r12\[r12<<0x3\],r12 + *[0-9a-f]*: ea 05 0b 25 st\.b r5\[r5<<0x2\],r5 + *[0-9a-f]*: e8 04 0b 14 st\.b r4\[r4<<0x1\],r4 + *[0-9a-f]*: fc 0e 0b 1e st\.b lr\[lr<<0x1\],lr + *[0-9a-f]*: e2 08 0b 16 st\.b r1\[r8<<0x1\],r6 + *[0-9a-f]*: fc 0e 0b 31 st\.b lr\[lr<<0x3\],r1 + *[0-9a-f]*: ea 00 0b 2f st\.b r5\[r0<<0x2\],pc + +[0-9a-f]* : + *[0-9a-f]*: fe 0f 0c 0f divs pc,pc,pc + *[0-9a-f]*: f8 0c 0c 0c divs r12,r12,r12 + *[0-9a-f]*: ea 05 0c 05 divs r5,r5,r5 + *[0-9a-f]*: e8 04 0c 04 divs r4,r4,r4 + *[0-9a-f]*: fc 0e 0c 0e divs lr,lr,lr + *[0-9a-f]*: fe 0f 0c 03 divs r3,pc,pc + *[0-9a-f]*: f8 02 0c 09 divs r9,r12,r2 + *[0-9a-f]*: e8 01 0c 07 divs r7,r4,r1 + +[0-9a-f]* : + *[0-9a-f]*: 1e 0f add pc,pc + *[0-9a-f]*: 18 0c add r12,r12 + *[0-9a-f]*: 0a 05 add r5,r5 + *[0-9a-f]*: 08 04 add r4,r4 + *[0-9a-f]*: 1c 0e add lr,lr + *[0-9a-f]*: 12 0c add r12,r9 + *[0-9a-f]*: 06 06 add r6,r3 + *[0-9a-f]*: 18 0a add r10,r12 + +[0-9a-f]* : + *[0-9a-f]*: 1e 1f sub pc,pc + *[0-9a-f]*: 18 1c sub r12,r12 + *[0-9a-f]*: 0a 15 sub r5,r5 + *[0-9a-f]*: 08 14 sub r4,r4 + *[0-9a-f]*: 1c 1e sub lr,lr + *[0-9a-f]*: 0c 1e sub lr,r6 + *[0-9a-f]*: 1a 10 sub r0,sp + *[0-9a-f]*: 18 16 sub r6,r12 + +[0-9a-f]* : + *[0-9a-f]*: 1e 2f rsub pc,pc + *[0-9a-f]*: 18 2c rsub r12,r12 + *[0-9a-f]*: 0a 25 rsub r5,r5 + *[0-9a-f]*: 08 24 rsub r4,r4 + *[0-9a-f]*: 1c 2e rsub lr,lr + *[0-9a-f]*: 1a 2b rsub r11,sp + *[0-9a-f]*: 08 27 rsub r7,r4 + *[0-9a-f]*: 02 29 rsub r9,r1 + +[0-9a-f]* : + *[0-9a-f]*: 1e 3f cp\.w pc,pc + *[0-9a-f]*: 18 3c cp\.w r12,r12 + *[0-9a-f]*: 0a 35 cp\.w r5,r5 + *[0-9a-f]*: 08 34 cp\.w r4,r4 + *[0-9a-f]*: 1c 3e cp\.w lr,lr + *[0-9a-f]*: 04 36 cp\.w r6,r2 + *[0-9a-f]*: 12 30 cp\.w r0,r9 + *[0-9a-f]*: 1a 33 cp\.w r3,sp + +[0-9a-f]* : + *[0-9a-f]*: 1e 4f or pc,pc + *[0-9a-f]*: 18 4c or r12,r12 + *[0-9a-f]*: 0a 45 or r5,r5 + *[0-9a-f]*: 08 44 or r4,r4 + *[0-9a-f]*: 1c 4e or lr,lr + *[0-9a-f]*: 12 44 or r4,r9 + *[0-9a-f]*: 08 4b or r11,r4 + *[0-9a-f]*: 00 44 or r4,r0 + +[0-9a-f]* : + *[0-9a-f]*: 1e 5f eor pc,pc + *[0-9a-f]*: 18 5c eor r12,r12 + *[0-9a-f]*: 0a 55 eor r5,r5 + *[0-9a-f]*: 08 54 eor r4,r4 + *[0-9a-f]*: 1c 5e eor lr,lr + *[0-9a-f]*: 16 5c eor r12,r11 + *[0-9a-f]*: 02 50 eor r0,r1 + *[0-9a-f]*: 1e 55 eor r5,pc + +[0-9a-f]* : + *[0-9a-f]*: 1e 6f and pc,pc + *[0-9a-f]*: 18 6c and r12,r12 + *[0-9a-f]*: 0a 65 and r5,r5 + *[0-9a-f]*: 08 64 and r4,r4 + *[0-9a-f]*: 1c 6e and lr,lr + *[0-9a-f]*: 02 68 and r8,r1 + *[0-9a-f]*: 1a 60 and r0,sp + *[0-9a-f]*: 0a 6a and r10,r5 + +[0-9a-f]* : + *[0-9a-f]*: 1e 7f tst pc,pc + *[0-9a-f]*: 18 7c tst r12,r12 + *[0-9a-f]*: 0a 75 tst r5,r5 + *[0-9a-f]*: 08 74 tst r4,r4 + *[0-9a-f]*: 1c 7e tst lr,lr + *[0-9a-f]*: 18 70 tst r0,r12 + *[0-9a-f]*: 0c 7a tst r10,r6 + *[0-9a-f]*: 08 7d tst sp,r4 + +[0-9a-f]* : + *[0-9a-f]*: 1e 8f andn pc,pc + *[0-9a-f]*: 18 8c andn r12,r12 + *[0-9a-f]*: 0a 85 andn r5,r5 + *[0-9a-f]*: 08 84 andn r4,r4 + *[0-9a-f]*: 1c 8e andn lr,lr + *[0-9a-f]*: 18 89 andn r9,r12 + *[0-9a-f]*: 1a 8b andn r11,sp + *[0-9a-f]*: 0a 8c andn r12,r5 + +[0-9a-f]* : + *[0-9a-f]*: 1e 9f mov pc,pc + *[0-9a-f]*: 18 9c mov r12,r12 + *[0-9a-f]*: 0a 95 mov r5,r5 + *[0-9a-f]*: 08 94 mov r4,r4 + *[0-9a-f]*: 1c 9e mov lr,lr + *[0-9a-f]*: 12 95 mov r5,r9 + *[0-9a-f]*: 16 9b mov r11,r11 + *[0-9a-f]*: 1c 92 mov r2,lr + +[0-9a-f]* : + *[0-9a-f]*: 1e af st\.w pc\+\+,pc + *[0-9a-f]*: 18 ac st\.w r12\+\+,r12 + *[0-9a-f]*: 0a a5 st\.w r5\+\+,r5 + *[0-9a-f]*: 08 a4 st\.w r4\+\+,r4 + *[0-9a-f]*: 1c ae st\.w lr\+\+,lr + *[0-9a-f]*: 02 ab st\.w r1\+\+,r11 + *[0-9a-f]*: 1a a0 st\.w sp\+\+,r0 + *[0-9a-f]*: 1a a1 st\.w sp\+\+,r1 + +[0-9a-f]* : + *[0-9a-f]*: 1e bf st\.h pc\+\+,pc