--- a/gcc/regrename.c +++ b/gcc/regrename.c @@ -1592,9 +1592,6 @@ copyprop_hardreg_forward_1 (basic_block bool changed = false; rtx insn; - rtx prev_pred_test; - int prev_pred_insn_skipped = 0; - for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) { int n_ops, i, alt, predicated; @@ -1633,60 +1630,7 @@ copyprop_hardreg_forward_1 (basic_block || (predicated && recog_data.operand_type[i] == OP_OUT)) recog_data.operand_type[i] = OP_INOUT; } - - /* Added for targets (AVR32) which supports test operands to be modified - in cond_exec instruction. For these targets we cannot make a change to - the test operands if one of the test operands is an output operand This beacuse - changing the test operands might cause the need for inserting a new test - insns in the middle of a sequence of cond_exec insns and if the test operands - are modified these tests will fail. - */ - - if ( IFCVT_ALLOW_MODIFY_TEST_IN_INSN - && predicated ) - { - int insn_skipped = 0; - rtx test = COND_EXEC_TEST (PATTERN (insn)); - - /* Check if the previous insn was a skipped predicated insn with the same - test as this predicated insns. If so we cannot do any modification to - this insn either since we cannot emit the test insn because the operands - are clobbered. */ - if ( prev_pred_insn_skipped - && (rtx_equal_p (test, prev_pred_test) - || rtx_equal_p (test, reversed_condition (prev_pred_test))) ) - { - insn_skipped = 1; - } - else - { - /* Check if the output operand is used in the test expression. */ - for (i = 0; i < n_ops; ++i) - if ( recog_data.operand_type[i] == OP_INOUT - && reg_mentioned_p (recog_data.operand[i], test) ) - { - insn_skipped = 1; - break; - } - - } - - prev_pred_test = test; - prev_pred_insn_skipped = insn_skipped; - if ( insn_skipped ) - { - if (insn == BB_END (bb)) - break; - else - continue; - } - } - else - { - prev_pred_insn_skipped = 0; - } - /* For each earlyclobber operand, zap the value data. */ for (i = 0; i < n_ops; i++) if (recog_op_alt[i][alt].earlyclobber) --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1684,7 +1684,7 @@ A memory reference suitable for the ARMv @item AVR32 family---@file{avr32.h} @table @code @item f -Floating-point registers (f0 to f15) (Reserved for future use) +Floating-point registers (f0 to f15) @item Ku@var{bits} Unsigned constant representable with @var{bits} number of bits (Must be @@ -1706,25 +1706,6 @@ loaded with a move instruction. That is values in the least and most significant words both are in the range @math{-2^{20}} to @math{2^{20}-1}. -@item M -Any 32-bit immediate with the most significant bits set to zero and the -remaining least significant bits set to one. - -@item J -A 32-bit immediate where all the lower 16-bits are zero. - -@item O -A 32-bit immediate with one bit set and the rest of the bits cleared. - -@item N -A 32-bit immediate with one bit cleared and the rest of the bits set. - -@item L -A 32-bit immediate where all the lower 16-bits are set. - -@item Q -Any AVR32 memory reference except for reference used for the atomic memory (RMW) instructions. - @item RKs@var{bits} A memory reference where the address consists of a base register plus a signed immediate displacement with range given by @samp{Ks@var{bits}} @@ -1747,9 +1728,6 @@ A memory reference to a constant pool en A valid operand for use in the @samp{lda.w} instruction macro when relaxing is enabled -@item Y -A memory reference suitable for the atomic memory (RMW) instructions. - @item Z A memory reference valid for coprocessor memory instructions --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -3469,23 +3469,6 @@ placed in either the @code{.bss_below100 @end table -@subsection AVR32 Variable Attributes - -One attribute is currently defined for AVR32 configurations: -@code{rmw_addressable} - -@table @code -@item rmw_addressable -@cindex @code{rmw_addressable} attribute - -This attribute can be used to signal that a variable can be accessed -with the addressing mode of the AVR32 Atomic Read-Modify-Write memory -instructions and hence make it possible for gcc to generate these -instructions without using built-in functions or inline assembly statements. -Variables used within the AVR32 Atomic Read-Modify-Write built-in -functions will automatically get the @code{rmw_addressable} attribute. -@end table - @node Type Attributes @section Specifying Attributes of Types @cindex attribute of types @@ -6436,24 +6419,8 @@ long long __builtin_arm_wzero () @subsection AVR32 Built-in Functions - -Built-in functions for atomic memory (RMW) instructions. Note that these -built-ins will fail for targets where the RMW instructions are not -implemented. Also note that these instructions only that a Ks15 << 2 -memory address and will therefor not work with any runtime computed -memory addresses. The user is responsible for making sure that any -pointers used within these functions points to a valid memory address. - -@smallexample -void __builtin_mems(int */*ptr*/, int /*bit*/) -void __builtin_memc(int */*ptr*/, int /*bit*/) -void __builtin_memt(int */*ptr*/, int /*bit*/) -@end smallexample - -Built-in functions for DSP instructions. Note that these built-ins will -fail for targets where the DSP instructions are not implemented. - @smallexample + int __builtin_sats (int /*Rd*/,int /*sa*/, int /*bn*/) int __builtin_satu (int /*Rd*/,int /*sa*/, int /*bn*/) int __builtin_satrnds (int /*Rd*/,int /*sa*/, int /*bn*/) @@ -6472,12 +6439,7 @@ long long __builtin_mulwh_d(int, short) long long __builtin_mulnwh_d(int, short) long long __builtin_macwh_d(long long, int, short) long long __builtin_machh_d(long long, short, short) -@end smallexample -Other built-in functions for instructions that cannot easily be -generated by the compiler. - -@smallexample void __builtin_ssrf(int); void __builtin_csrf(int); void __builtin_musfr(int); --- a/gcc/config/avr32/predicates.md +++ b/gcc/config/avr32/predicates.md @@ -315,13 +315,13 @@ ;; True is this is valid avr32 symbol operand (define_predicate "avr32_symbol_operand" - (and (match_code "label_ref, symbol_ref, const") - (match_test "avr32_find_symbol(op)"))) + (ior (match_code "label_ref, symbol_ref") + (and (match_code "const") + (match_test "avr32_find_symbol(op)")))) ;; True is this is valid operand for the lda.w and call pseudo insns (define_predicate "avr32_address_operand" - (and (and (match_code "label_ref, symbol_ref") - (match_test "avr32_find_symbol(op)")) + (and (match_code "label_ref, symbol_ref") (ior (match_test "TARGET_HAS_ASM_ADDR_PSEUDOS") (match_test "flag_pic")) )) @@ -384,36 +384,3 @@ (define_predicate "avr32_mov_immediate_operand" (and (match_operand 0 "immediate_operand") (match_test "avr32_const_ok_for_move(INTVAL(op))"))) - - -(define_predicate "avr32_rmw_address_operand" - (ior (and (match_code "symbol_ref") - (match_test "({rtx symbol = avr32_find_symbol(op); \ - symbol && (GET_CODE (symbol) == SYMBOL_REF) && SYMBOL_REF_RMW_ADDR(symbol);})")) - (and (match_operand 0 "immediate_operand") - (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks17\")"))) - { - return TARGET_RMW && !flag_pic; - } -) - -(define_predicate "avr32_rmw_memory_operand" - (and (match_code "mem") - (match_test "(GET_MODE(op) == SImode) && - avr32_rmw_address_operand(XEXP(op, 0), GET_MODE(XEXP(op, 0)))"))) - -(define_predicate "avr32_rmw_memory_or_register_operand" - (ior (match_operand 0 "avr32_rmw_memory_operand") - (match_operand 0 "register_operand"))) - -(define_predicate "avr32_non_rmw_memory_operand" - (and (not (match_operand 0 "avr32_rmw_memory_operand")) - (match_operand 0 "memory_operand"))) - -(define_predicate "avr32_non_rmw_general_operand" - (and (not (match_operand 0 "avr32_rmw_memory_operand")) - (match_operand 0 "general_operand"))) - -(define_predicate "avr32_non_rmw_nonimmediate_operand" - (and (not (match_operand 0 "avr32_rmw_memory_operand")) - (match_operand 0 "nonimmediate_operand"))) --- a/gcc/config/avr32/avr32.h +++ b/gcc/config/avr32/avr32.h @@ -86,10 +86,6 @@ extern struct rtx_def *avr32_acc_cache; #define IS_NAKED(t) (t & AVR32_FT_NAKED) #define IS_NESTED(t) (t & AVR32_FT_NESTED) -#define SYMBOL_FLAG_RMW_ADDR_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT -#define SYMBOL_REF_RMW_ADDR(RTX) \ - ((SYMBOL_REF_FLAGS (RTX) & (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT)) != 0) - typedef struct minipool_labels GTY ((chain_next ("%h.next"), chain_prev ("%h.prev"))) @@ -1259,7 +1255,8 @@ in the reload pass. #define CONSTRAINT_LEN(C, STR) \ ( ((C) == 'K' || (C) == 'I') ? 4 : \ ((C) == 'R') ? 5 : \ - ((C) == 'P') ? -1 : \ + ((C) == 'N' || (C) == 'O' || \ + (C) == 'P' || (C) == 'L') ? -1 : \ DEFAULT_CONSTRAINT_LEN((C), (STR)) ) #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ @@ -1313,15 +1310,11 @@ does not include r0 on the output. (C) == 'T' ? avr32_const_pool_ref_operand(OP, GET_MODE(OP)) : \ (C) == 'U' ? SYMBOL_REF_RCALL_FUNCTION_P(OP) : \ (C) == 'Z' ? avr32_cop_memory_operand(OP, GET_MODE(OP)) : \ - (C) == 'Q' ? avr32_non_rmw_memory_operand(OP, GET_MODE(OP)) : \ - (C) == 'Y' ? avr32_rmw_memory_operand(OP, GET_MODE(OP)) : \ 0) #define EXTRA_MEMORY_CONSTRAINT(C, STR) ( ((C) == 'R') || \ - ((C) == 'Q') || \ ((C) == 'S') || \ - ((C) == 'Y') || \ ((C) == 'Z') ) @@ -3287,10 +3280,7 @@ enum avr32_builtins AVR32_BUILTIN_SATS, AVR32_BUILTIN_SATU, AVR32_BUILTIN_SATRNDS, - AVR32_BUILTIN_SATRNDU, - AVR32_BUILTIN_MEMS, - AVR32_BUILTIN_MEMC, - AVR32_BUILTIN_MEMT + AVR32_BUILTIN_SATRNDU }; --- a/gcc/config/avr32/avr32.md +++ b/gcc/config/avr32/avr32.md @@ -455,8 +455,8 @@ (define_expand "mov" - [(set (match_operand:MOVM 0 "avr32_non_rmw_nonimmediate_operand" "") - (match_operand:MOVM 1 "avr32_non_rmw_general_operand" ""))] + [(set (match_operand:MOVM 0 "register_operand" "") + (match_operand:MOVM 1 "general_operand" ""))] "" { @@ -476,20 +476,6 @@ operands[1] = force_const_mem(SImode, operands[1]); } - /* Check for RMW memory operands. They are not allowed for mov operations - only the atomic memc/s/t operations */ - if ( !reload_in_progress - && avr32_rmw_memory_operand (operands[0], mode) ){ - operands[0] = copy_rtx (operands[0]); - XEXP(operands[0], 0) = force_reg (mode, XEXP(operands[0], 0)); - } - - if ( !reload_in_progress - && avr32_rmw_memory_operand (operands[1], mode) ){ - operands[1] = copy_rtx (operands[1]); - XEXP(operands[1], 0) = force_reg (mode, XEXP(operands[1], 0)); - } - if ( (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS) && !avr32_legitimate_pic_operand_p(operands[1]) ) operands[1] = legitimize_pic_address (operands[1], mode, @@ -502,12 +488,10 @@ (define_insn "mov_internal" - [(set (match_operand:MOVM 0 "avr32_non_rmw_nonimmediate_operand" "=r, r, r,r,r,Q,r") - (match_operand:MOVM 1 "avr32_non_rmw_general_operand" "rKs08,Ks21,J,n,Q,r,W"))] - "(register_operand (operands[0], mode) - || register_operand (operands[1], mode)) - && !avr32_rmw_memory_operand (operands[0], mode) - && !avr32_rmw_memory_operand (operands[1], mode)" + [(set (match_operand:MOVM 0 "nonimmediate_operand" "=r, r, r,r,r,m,r") + (match_operand:MOVM 1 "general_operand" "rKs08,Ks21,J,n,m,r,W"))] + "register_operand (operands[0], mode) + || register_operand (operands[1], mode)" { switch (which_alternative) { case 0: @@ -556,27 +540,6 @@ (set_attr "cc" "none,none,set_z_if_not_v2,set_z,none,none,clobber")]) -(define_expand "reload_out_rmw_memory_operand" - [(set (match_operand:SI 2 "register_operand" "=r") - (match_operand:SI 0 "address_operand" "")) - (set (mem:SI (match_dup 2)) - (match_operand:SI 1 "register_operand" ""))] - "" - { - operands[0] = XEXP(operands[0], 0); - } -) - -(define_expand "reload_in_rmw_memory_operand" - [(set (match_operand:SI 2 "register_operand" "=r") - (match_operand:SI 1 "address_operand" "")) - (set (match_operand:SI 0 "register_operand" "") - (mem:SI (match_dup 2)))] - "" - { - operands[1] = XEXP(operands[1], 0); - } -) ;; These instructions are for loading constants which cannot be loaded @@ -953,7 +916,7 @@ ;;============================================================================= (define_insn "ld_predicable" [(set (match_operand:MOVCC 0 "register_operand" "=r") - (match_operand:MOVCC 1 "avr32_non_rmw_memory_operand" ""))] + (match_operand:MOVCC 1 "memory_operand" ""))] "TARGET_V2_INSNS" "ld%?\t%0, %1" [(set_attr "length" "4") @@ -964,7 +927,7 @@ (define_insn "st_predicable" - [(set (match_operand:MOVCC 0 "avr32_non_rmw_memory_operand" "=") + [(set (match_operand:MOVCC 0 "memory_operand" "=") (match_operand:MOVCC 1 "register_operand" "r"))] "TARGET_V2_INSNS" "st%?\t%0, %1" @@ -1264,13 +1227,13 @@ (define_insn "adddi3" [(set (match_operand:DI 0 "register_operand" "=r,r") - (plus:DI (match_operand:DI 1 "register_operand" "%0,r") + (plus:DI (match_operand:DI 1 "register_operand" "%r,0") (match_operand:DI 2 "register_operand" "r,r")))] "" "@ - add %0, %2\;adc %m0, %m0, %m2 - add %0, %1, %2\;adc %m0, %m1, %m2" - [(set_attr "length" "6,8") + add %0, %1, %2\;adc %m0, %m1, %m2 + add %0, %2\;adc %m0, %m0, %m2" + [(set_attr "length" "8,6") (set_attr "type" "alu2") (set_attr "cc" "set_vncz")]) @@ -1309,14 +1272,17 @@ (set_attr "cc" "")]) (define_insn "*sub3_mul" - [(set (match_operand:INTM 0 "register_operand" "=r") - (minus:INTM (match_operand:INTM 1 "register_operand" "r") - (mult:INTM (match_operand:INTM 2 "register_operand" "r") - (match_operand:SI 3 "immediate_operand" "Ku04" ))))] + [(set (match_operand:INTM 0 "register_operand" "=r,r,r") + (minus:INTM (match_operand:INTM 1 "register_operand" "r,0,r") + (mult:INTM (match_operand:INTM 2 "register_operand" "r,r,0") + (match_operand:SI 3 "immediate_operand" "Ku04,Ku04,Ku04" ))))] "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) || (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)" - "sub %0, %1, %2 << %p3" - [(set_attr "length" "4") + "@ + sub %0, %1, %2 << %p3 + sub %0, %0, %2 << %p3 + sub %0, %1, %0 << %p3" + [(set_attr "length" "4,4,4") (set_attr "cc" "")]) (define_insn "*sub3_lsl" @@ -1332,13 +1298,13 @@ (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=r,r") - (minus:DI (match_operand:DI 1 "register_operand" "%0,r") + (minus:DI (match_operand:DI 1 "register_operand" "%r,0") (match_operand:DI 2 "register_operand" "r,r")))] "" "@ - sub %0, %2\;sbc %m0, %m0, %m2 - sub %0, %1, %2\;sbc %m0, %m1, %m2" - [(set_attr "length" "6,8") + sub %0, %1, %2\;sbc %m0, %m1, %m2 + sub %0, %2\;sbc %m0, %m0, %m2" + [(set_attr "length" "8,6") (set_attr "type" "alu2") (set_attr "cc" "set_vncz")]) @@ -1506,7 +1472,7 @@ (set_attr "length" "4") (set_attr "cc" "none")]) -(define_insn "*mulaccsidi3" +(define_insn "mulaccsidi3" [(set (match_operand:DI 0 "register_operand" "+r") (plus:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) @@ -1518,7 +1484,7 @@ (set_attr "length" "4") (set_attr "cc" "none")]) -(define_insn "*umulaccsidi3" +(define_insn "umulaccsidi3" [(set (match_operand:DI 0 "register_operand" "+r") (plus:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) @@ -1890,24 +1856,57 @@ (define_insn "andsi3" - [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r,r,r, r, r,r,r,r,r") - (and:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,r,0,0, 0, 0,0,0,0,r" ) - (match_operand:SI 2 "nonmemory_operand" " N,M,N,Ku16,Ks17,J,L,r,i,r")))] + [(set (match_operand:SI 0 "register_operand" "=r, r, r, r") + (and:SI (match_operand:SI 1 "register_operand" "%0, r, 0, r") + (match_operand:SI 2 "nonmemory_operand" "r, M, i, r")))] "" - "@ - memc\t%0, %z2 - bfextu\t%0, %1, 0, %z2 - cbr\t%0, %z2 - andl\t%0, %2, COH - andl\t%0, lo(%2) - andh\t%0, hi(%2), COH - andh\t%0, hi(%2) - and\t%0, %2 - andh\t%0, hi(%2)\;andl\t%0, lo(%2) - and\t%0, %1, %2" - - [(set_attr "length" "4,4,2,4,4,4,4,2,8,4") - (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z,set_z,set_z,set_z,set_z")]) + { + switch (which_alternative){ + case 0: + return "and\t%0, %2"; + case 1: + { + int i, first_set = -1; + /* Search for first bit set in mask */ + for ( i = 31; i >= 0; --i ) + if ( INTVAL(operands[2]) & (1 << i) ){ + first_set = i; + break; + } + operands[2] = gen_rtx_CONST_INT(SImode, first_set + 1); + return "bfextu\t%0, %1, 0, %2"; + } + case 2: + if ( one_bit_cleared_operand(operands[2], VOIDmode) ){ + int bitpos; + for ( bitpos = 0; bitpos < 32; bitpos++ ) + if ( !(INTVAL(operands[2]) & (1 << bitpos)) ) + break; + operands[2] = gen_rtx_CONST_INT(SImode, bitpos); + return "cbr\t%0, %2"; + } else if ( (INTVAL(operands[2]) >= 0) && + (INTVAL(operands[2]) <= 65535) ) + return "andl\t%0, %2, COH"; + else if ( (INTVAL(operands[2]) < 0) && + (INTVAL(operands[2]) >= -65536 ) ) + return "andl\t%0, lo(%2)"; + else if ( ((INTVAL(operands[2]) & 0xffff) == 0xffff) ) + return "andh\t%0, hi(%2)"; + else if ( ((INTVAL(operands[2]) & 0xffff) == 0x0) ) + return "andh\t%0, hi(%2), COH"; + else + return "andh\t%0, hi(%2)\;andl\t%0, lo(%2)"; + case 3: + return "and\t%0, %1, %2"; + default: + abort(); + } + } + + [(set_attr "length" "2,4,8,4") + (set_attr "cc" "set_z")]) + + (define_insn "anddi3" [(set (match_operand:DI 0 "register_operand" "=&r,&r") @@ -1926,21 +1925,37 @@ ;;============================================================================= (define_insn "iorsi3" - [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r,r, r,r,r,r") - (ior:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,0,0, 0,0,0,r" ) - (match_operand:SI 2 "nonmemory_operand" " O,O,Ku16,J,r,i,r")))] + [(set (match_operand:SI 0 "register_operand" "=r,r,r") + (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r" ) + (match_operand:SI 2 "nonmemory_operand" "r ,i,r")))] "" - "@ - mems\t%0, %p2 - sbr\t%0, %p2 - orl\t%0, %2 - orh\t%0, hi(%2) - or\t%0, %2 - orh\t%0, hi(%2)\;orl\t%0, lo(%2) - or\t%0, %1, %2" - - [(set_attr "length" "4,2,4,4,2,8,4") - (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z,set_z")]) + { + switch (which_alternative){ + case 0: + return "or\t%0, %2"; + case 1: + if ( one_bit_set_operand(operands[2], VOIDmode) ){ + int bitpos; + for (bitpos = 0; bitpos < 32; bitpos++) + if (INTVAL(operands[2]) & (1 << bitpos)) + break; + operands[2] = gen_rtx_CONST_INT( SImode, bitpos); + return "sbr\t%0, %2"; + } else if ( (INTVAL(operands[2]) >= 0) && + (INTVAL(operands[2]) <= 65535) ) + return "orl\t%0, %2"; + else if ( ((INTVAL(operands[2]) & 0xffff) == 0x0) ) + return "orh\t%0, hi(%2)"; + else + return "orh\t%0, hi(%2)\;orl\t%0, lo(%2)"; + case 2: + return "or\t%0, %1, %2"; + default: + abort(); + } + } + [(set_attr "length" "2,8,4") + (set_attr "cc" "set_z")]) (define_insn "iordi3" @@ -1960,21 +1975,31 @@ ;;============================================================================= (define_insn "xorsi3" - [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r, r,r,r,r") - (xor:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,0, 0,0,0,r" ) - (match_operand:SI 2 "nonmemory_operand" " O,Ku16,J,r,i,r")))] + [(set (match_operand:SI 0 "register_operand" "=r,r,r") + (xor:SI (match_operand:SI 1 "register_operand" "0,0,r") + (match_operand:SI 2 "nonmemory_operand" "r,i,r")))] "" - "@ - memt\t%0, %p2 - eorl\t%0, %2 - eorh\t%0, hi(%2) - eor\t%0, %2 - eorh\t%0, hi(%2)\;eorl\t%0, lo(%2) - eor\t%0, %1, %2" - - [(set_attr "length" "4,4,4,2,8,4") - (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z")]) + { + switch (which_alternative){ + case 0: + return "eor %0, %2"; + case 1: + if ( (INTVAL(operands[2]) >= 0) && + (INTVAL(operands[2]) <= 65535) ) + return "eorl %0, %2"; + else if ( ((INTVAL(operands[2]) & 0xffff) == 0x0) ) + return "eorh %0, hi(%2)"; + else + return "eorh %0, hi(%2)\;eorl %0, lo(%2)"; + case 2: + return "eor %0, %1, %2"; + default: + abort(); + } + } + [(set_attr "length" "2,8,4") + (set_attr "cc" "set_z")]) (define_insn "xordi3" [(set (match_operand:DI 0 "register_operand" "=&r,&r") @@ -2334,12 +2359,12 @@ (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (not:SI (match_operand:SI 1 "register_operand" "0,r")))] + (not:SI (match_operand:SI 1 "register_operand" "r,0")))] "" "@ - com\t%0 - rsub\t%0, %1, -1" - [(set_attr "length" "2,4") + rsub\t%0, %1, -1 + com\t%0" + [(set_attr "length" "4,2") (set_attr "cc" "set_z")]) @@ -3310,7 +3335,7 @@ (define_insn "indirect_jump_internal" [(set (pc) - (match_operand:SI 0 "avr32_non_rmw_general_operand" "r,m,W"))] + (match_operand:SI 0 "general_operand" "r,m,W"))] "" { switch( which_alternative ){ --- a/gcc/config/avr32/avr32.opt +++ b/gcc/config/avr32/avr32.opt @@ -79,8 +79,3 @@ mcond-exec-before-reload Target Report Undocumented Mask(COND_EXEC_BEFORE_RELOAD) Enable experimental conditional execution preparation before the reload stage. -mrmw-addressable-data -Target Report Mask(RMW_ADDRESSABLE_DATA) -Signal that all data is in range for the Atomic Read-Modify-Write memory instructions, and that -gcc can safely generate these whenever possible. - --- a/gcc/config/avr32/avr32.c +++ b/gcc/config/avr32/avr32.c @@ -358,9 +358,6 @@ need agree with that used by other compi #undef TARGET_RETURN_IN_MSB #define TARGET_RETURN_IN_MSB avr32_return_in_msb -#undef TARGET_ENCODE_SECTION_INFO -#define TARGET_ENCODE_SECTION_INFO avr32_encode_section_info - #undef TARGET_ARG_PARTIAL_BYTES #define TARGET_ARG_PARTIAL_BYTES avr32_arg_partial_bytes @@ -397,24 +394,6 @@ need agree with that used by other compi #undef TARGET_MAX_ANCHOR_OFFSET #define TARGET_MAX_ANCHOR_OFFSET ((1 << 15) - 1) -#undef TARGET_SECONDARY_RELOAD -#define TARGET_SECONDARY_RELOAD avr32_secondary_reload - -enum reg_class -avr32_secondary_reload (bool in_p, rtx x, enum reg_class class ATTRIBUTE_UNUSED, - enum machine_mode mode, secondary_reload_info *sri) -{ - - if ( avr32_rmw_memory_operand (x, mode) ) - { - if (!in_p) - sri->icode = CODE_FOR_reload_out_rmw_memory_operand; - else - sri->icode = CODE_FOR_reload_in_rmw_memory_operand; - } - return NO_REGS; - -} /* * Switches to the appropriate section for output of constant pool @@ -655,7 +634,6 @@ const struct attribute_spec avr32_attrib {"interrupt", 0, 1, false, false, false, avr32_handle_isr_attribute}, {"acall", 0, 1, false, true, true, avr32_handle_acall_attribute}, {"naked", 0, 0, true, false, false, avr32_handle_fndecl_attribute}, - {"rmw_addressable", 0, 0, true, false, false, NULL}, {NULL, 0, 0, false, false, false, NULL} }; @@ -1071,9 +1049,6 @@ avr32_init_builtins (void) AVR32_BUILTIN_MACWH_D); def_builtin ("__builtin_machh_d", longlong_ftype_longlong_short_short, AVR32_BUILTIN_MACHH_D); - def_builtin ("__builtin_mems", void_ftype_ptr_int, AVR32_BUILTIN_MEMS); - def_builtin ("__builtin_memt", void_ftype_ptr_int, AVR32_BUILTIN_MEMT); - def_builtin ("__builtin_memc", void_ftype_ptr_int, AVR32_BUILTIN_MEMC); /* Add all builtins that are more or less simple operations on two operands. */ @@ -1808,56 +1783,6 @@ avr32_expand_builtin (tree exp, return target; } - case AVR32_BUILTIN_MEMS: - case AVR32_BUILTIN_MEMC: - case AVR32_BUILTIN_MEMT: - { - if (!TARGET_RMW) - error ("Trying to use __builtin_mem(s/c/t) when target does not support RMW insns."); - - switch (fcode) { - case AVR32_BUILTIN_MEMS: - icode = CODE_FOR_iorsi3; - break; - case AVR32_BUILTIN_MEMC: - icode = CODE_FOR_andsi3; - break; - case AVR32_BUILTIN_MEMT: - icode = CODE_FOR_xorsi3; - break; - } - - arg0 = TREE_VALUE (arglist); - arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - if ( GET_CODE (op0) == SYMBOL_REF ) - // This symbol must be RMW addressable - SYMBOL_REF_FLAGS (op0) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT); - op0 = gen_rtx_MEM(SImode, op0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - mode0 = insn_data[icode].operand[1].mode; - - - if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) - { - error ("Parameter 1 to __builtin_mem(s/c/t) must be a Ks15<<2 address or a rmw addressable symbol."); - } - - if ( !CONST_INT_P (op1) - || INTVAL (op1) > 31 - || INTVAL (op1) < 0 ) - error ("Parameter 2 to __builtin_mem(s/c/t) must be a constant between 0 and 31."); - - if ( fcode == AVR32_BUILTIN_MEMC ) - op1 = GEN_INT((~(1 << INTVAL(op1)))&0xffffffff); - else - op1 = GEN_INT((1 << INTVAL(op1))&0xffffffff); - pat = GEN_FCN (icode) (op0, op0, op1); - if (!pat) - return 0; - emit_insn (pat); - return op0; - } } @@ -2257,13 +2182,6 @@ avr32_const_ok_for_constraint_p (HOST_WI return avr32_mask_upper_bits_operand (GEN_INT (value), VOIDmode); case 'J': return avr32_hi16_immediate_operand (GEN_INT (value), VOIDmode); - case 'O': - return one_bit_set_operand (GEN_INT (value), VOIDmode); - case 'N': - return one_bit_cleared_operand (GEN_INT (value), VOIDmode); - case 'L': - /* The lower 16-bits are set. */ - return ((value & 0xffff) == 0xffff) ; } return 0; @@ -4089,9 +4007,6 @@ avr32_legitimate_address (enum machine_m { case REG: return avr32_address_register_rtx_p (x, strict); - case CONST_INT: - return ((mode==SImode) - && CONST_OK_FOR_CONSTRAINT_P(INTVAL(x), 'K', "Ks17")); case CONST: { rtx label = avr32_find_symbol (x); @@ -4104,10 +4019,7 @@ avr32_legitimate_address (enum machine_m /* TODO! Can this ever happen??? */ || ((GET_CODE (label) == LABEL_REF) && GET_CODE (XEXP (label, 0)) == CODE_LABEL - && is_minipool_label (XEXP (label, 0))) - /*|| ((GET_CODE (label) == SYMBOL_REF) - && mode == SImode - && SYMBOL_REF_RMW_ADDR(label))*/)) + && is_minipool_label (XEXP (label, 0))))) { return TRUE; } @@ -4127,9 +4039,12 @@ avr32_legitimate_address (enum machine_m && (symbol_mentioned_p (get_pool_constant (x)) || label_mentioned_p (get_pool_constant (x))))) return TRUE; - else if (SYMBOL_REF_RCALL_FUNCTION_P (x) - || (mode == SImode - && SYMBOL_REF_RMW_ADDR (x))) + /* + A symbol_ref is only legal if it is a function. If all of them are + legal, a pseudo reg that is a constant will be replaced by a + symbol_ref and make illegale code. SYMBOL_REF_FLAG is set by + ENCODE_SECTION_INFO. */ + else if (SYMBOL_REF_RCALL_FUNCTION_P (x)) return TRUE; break; } @@ -4223,8 +4138,9 @@ avr32_legitimate_constant_p (rtx x) else return 0; case LABEL_REF: + return flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS; case SYMBOL_REF: - return avr32_find_symbol (x) && (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS); + return flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS; case CONST: case HIGH: case CONST_VECTOR: @@ -4303,16 +4219,18 @@ avr32_return_addr (int count, rtx frame void avr32_encode_section_info (tree decl, rtx rtl, int first) { - default_encode_section_info(decl, rtl, first); - if ( TREE_CODE (decl) == VAR_DECL - && (GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF) - && (lookup_attribute ("rmw_addressable", DECL_ATTRIBUTES (decl)) - || TARGET_RMW_ADDRESSABLE_DATA) ){ - if ( !TARGET_RMW || flag_pic ) - return; - SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT); - } + if (first && DECL_P (decl)) + { + /* Set SYMBOL_REG_FLAG for local functions */ + if (!TREE_PUBLIC (decl) && TREE_CODE (decl) == FUNCTION_DECL) + { + if ((*targetm.binds_local_p) (decl)) + { + SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; + } + } + } } void @@ -4891,19 +4809,6 @@ avr32_print_operand (FILE * stream, rtx value = bitpos; } break; - case 'z': - { - /* Set to bit position of first bit cleared in immediate */ - int i, bitpos = 32; - for (i = 0; i < 32; i++) - if (!(value & (1 << i))) - { - bitpos = i; - break; - } - value = bitpos; - } - break; case 'r': { /* Reglist 8 */ @@ -5133,9 +5038,6 @@ avr32_print_operand (FILE * stream, rtx fprintf (stream, " + %ld", INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))); break; - case CONST_INT: - avr32_print_operand (stream, XEXP (x, 0), 0); - break; default: error = 1; }