diff -Nur u-boot-1.1.4/board/atstk1000/atstk1000.c u-boot-1.1.4-avr32-20060621/board/atstk1000/atstk1000.c --- u-boot-1.1.4/board/atstk1000/atstk1000.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/atstk1000.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +static const struct sdram_info sdram = { + .phys_addr = CFG_SDRAM_BASE, + .row_bits = 11, + .col_bits = 8, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, +}; + +void board_init_memories(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->sdram_size = sdram_init(&sdram); +} + +void board_init_info(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_phy_id[0] = 0x10; + gd->bd->bi_phy_id[1] = 0x11; +} diff -Nur u-boot-1.1.4/board/atstk1000/atstk1002.c u-boot-1.1.4-avr32-20060621/board/atstk1000/atstk1002.c --- u-boot-1.1.4/board/atstk1000/atstk1002.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/atstk1002.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include + +#define USART0_PIOMASK ((1 << 8) | (1 << 9)) + +void board_init_pio(void) +{ + writel(USART0_PIOMASK, PIOA_BASE + 0x70); + writel(USART0_PIOMASK, PIOA_BASE + 0x04); +} diff -Nur u-boot-1.1.4/board/atstk1000/config.mk u-boot-1.1.4-avr32-20060621/board/atstk1000/config.mk --- u-boot-1.1.4/board/atstk1000/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/config.mk 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1 @@ +TEXT_BASE = 0x00000000 diff -Nur u-boot-1.1.4/board/atstk1000/eth.c u-boot-1.1.4-avr32-20060621/board/atstk1000/eth.c --- u-boot-1.1.4/board/atstk1000/eth.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/eth.c 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Ethernet initialization for the ATSTK1000 starterkit + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +extern int macb_eth_initialize(int id, unsigned int phy_addr); + +#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & CFG_CMD_NET) +void atstk1000_eth_initialize(bd_t *bi) +{ + int id = 0; + +#ifdef CFG_MACB0 + macb_eth_initialize(id++, bi->bi_phy_id[0]); +#endif +#ifdef CFG_MACB1 + macb_eth_initialize(id++, bi->bi_phy_id[1]); +#endif +} +#endif diff -Nur u-boot-1.1.4/board/atstk1000/flash.c u-boot-1.1.4-avr32-20060621/board/atstk1000/flash.c --- u-boot-1.1.4/board/atstk1000/flash.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/flash.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CONFIG_ATSTK1000_EXT_FLASH +#include +#include +#include + +flash_info_t flash_info[1]; + +static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info) +{ + unsigned long flags; + + local_irq_save(flags); + + dcache_flush_unlocked(); + + writew(0xaa, flash + 0x555); + writew(0x55, flash + 0xaaa); + writew(0x90, flash + 0x555); + info->flash_id = readl(flash); + writew(0xff, flash); + + readw(flash); + + local_irq_restore(flags); +} + +unsigned long flash_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long addr; + unsigned int i; + + gd->bd->bi_flashstart = CFG_FLASH_BASE; + gd->bd->bi_flashsize = CFG_FLASH_SIZE; + gd->bd->bi_flashoffset = __edata_lma - _text; + + flash_info[0].size = CFG_FLASH_SIZE; + flash_info[0].sector_count = 135; + + flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]); + + for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) + flash_info[0].start[i] = addr; + for (; i < flash_info[0].sector_count; i++, addr += 0x10000) + flash_info[0].start[i] = addr; + + return CFG_FLASH_SIZE; +} + +void flash_print_info(flash_info_t *info) +{ + printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n", + info->flash_id >> 16, info->flash_id & 0xffff); + printf("Size: %ld MB in %d sectors\n", + info->size >> 10, info->sector_count); +} + +int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last) +{ + unsigned long flags; + unsigned long start_time; + uint16_t *fb, *sb; + unsigned int i; + int ret; + uint16_t status; + + if ((s_first < 0) || (s_first > s_last) + || (s_last >= info->sector_count)) { + puts("Error: first and/or last sector out of range\n"); + return ERR_INVAL; + } + + for (i = s_first; i < s_last; i++) + if (info->protect[i]) { + printf("Error: sector %d is protected\n", i); + return ERR_PROTECTED; + } + + fb = (uint16_t *)uncached(info->start[0]); + + dcache_flush_unlocked(); + + for (i = s_first; (i <= s_last) && !ctrlc(); i++) { + printf("Erasing sector %3d...", i); + + sb = (uint16_t *)uncached(info->start[i]); + + local_irq_save(flags); + + start_time = get_timer(0); + + /* Unlock sector */ + writew(0xaa, fb + 0x555); + writew(0x70, sb); + + /* Erase sector */ + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x80, fb + 0x555); + writew(0xaa, fb + 0x555); + writew(0x55, fb + 0xaaa); + writew(0x30, sb); + + /* Wait for completion */ + ret = ERR_OK; + do { + /* TODO: Timeout */ + status = readw(sb); + } while ((status != 0xffff) && !(status & 0x28)); + + writew(0xf0, fb); + + /* + * Make sure the command actually makes it to the bus + * before we re-enable interrupts. + */ + readw(fb); + + local_irq_restore(flags); + + if (status != 0xffff) { + printf("Flash erase error at address 0x%p: 0x%02x\n", + sb, status); + ret = ERR_PROG_ERROR; + break; + } + } + + if (ctrlc()) + printf("User interrupt!\n"); + + return ERR_OK; +} + +int __flashprog write_buff(flash_info_t *info, uchar *src, + ulong addr, ulong count) +{ + unsigned long flags; + uint16_t *base, *p, *s, *end; + uint16_t word, status; + int ret = ERR_OK; + + if (addr < info->start[0] + || (addr + count) > (info->start[0] + info->size) + || (addr + count) < addr) { + puts("Error: invalid address range\n"); + return ERR_INVAL; + } + + if (addr & 1 || count & 1 || (unsigned int)src & 1) { + puts("Error: misaligned source, destination or count\n"); + return ERR_ALIGN; + } + + base = (uint16_t *)uncached(info->start[0]); + end = (uint16_t *)uncached(addr + count); + + local_irq_save(flags); + + dcache_flush_unlocked(); + sync_write_buffer(); + + for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; + p < end && !ctrlc(); p++, s++) { + word = *s; + + writew(0xaa, base + 0x555); + writew(0x55, base + 0xaaa); + writew(0xa0, base + 0x555); + writew(word, p); + + sync_write_buffer(); + + /* Wait for completion */ + do { + /* TODO: Timeout */ + status = readw(p); + } while ((status != word) && !(status & 0x28)); + + writew(0xf0, base); + readw(base); + + if (status != word) { + printf("Flash write error at address 0x%p: 0x%02x\n", + p, status); + ret = ERR_PROG_ERROR; + break; + } + } + + local_irq_restore(flags); + + return ret; +} + +#endif /* CONFIG_ATSTK1000_EXT_FLASH */ diff -Nur u-boot-1.1.4/board/atstk1000/Makefile u-boot-1.1.4-avr32-20060621/board/atstk1000/Makefile --- u-boot-1.1.4/board/atstk1000/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/Makefile 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,58 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +ifeq ($(SOC),ap7000) +DAUGHTERBOARD := atstk1002 +endif +ifndef DAUGHTERBOARD +DAUGHTERBOARD := unknown +endif + +LIB := lib$(BOARD).a + +SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c +OBJS := $(addsuffix .o,$(basename $(SRC))) + +.PHONY: all +all: .depend $(LIB) u-boot.lds + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +u-boot.lds: u-boot.lds.S ../../include/config.h + $(CPP) $(AFLAGS) -P -o $@ $< + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend u-boot.lds + +######################################################################### + +.depend: Makefile $(SRC) + $(CC) -M $(CPPFLAGS) $(SRC) > $@ + +-include .depend + +######################################################################### diff -Nur u-boot-1.1.4/board/atstk1000/u-boot.lds.S u-boot-1.1.4-avr32-20060621/board/atstk1000/u-boot.lds.S --- u-boot-1.1.4/board/atstk1000/u-boot.lds.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/atstk1000/u-boot.lds.S 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,86 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = CFG_FLASH_BASE; + _text = .; + .text : { + *(.text) + *(.text.exception) + } + + . = ALIGN(CFG_ICACHE_LINESZ); + __flashprog_start = .; + .flashprog : { + *(.flashprog) + } + . = ALIGN(CFG_ICACHE_LINESZ); + __flashprog_end = .; + + . = ALIGN(8); + .rodata : { + *(.rodata) + *(.rodata.*) + } + _etext = .; + + __data_lma = ALIGN(8); + . = CFG_INTRAM_BASE; + _data = .; + .data : AT(__data_lma) { + *(.data) + *(.data.*) + } + + . = ALIGN(8); + __got_start = .; + __got_lma = __data_lma + (__got_start - _data); + .got : AT(__got_lma) { + *(.got.plt) + *(.got) + } + __got_end = .; + + __u_boot_cmd_start = .; + __u_boot_cmd_lma = __got_lma + (__u_boot_cmd_start - __got_start); + .u_boot_cmd : AT(__u_boot_cmd_lma) { + *(.u_boot_cmd) + } + __u_boot_cmd_end = .; + + . = ALIGN(8); + _edata = .; + __edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start); + + .bss : { + *(.bss) + } + . = ALIGN(8); + _end = .; +} diff -Nur u-boot-1.1.4/board/omap730p2/Makefile u-boot-1.1.4-avr32-20060621/board/omap730p2/Makefile --- u-boot-1.1.4/board/omap730p2/Makefile 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/board/omap730p2/Makefile 1970-01-01 01:00:00.000000000 +0100 @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := omap730p2.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff -Nur u-boot-1.1.4/common/cmd_bootm.c u-boot-1.1.4-avr32-20060621/common/cmd_bootm.c --- u-boot-1.1.4/common/cmd_bootm.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/common/cmd_bootm.c 2006-06-21 11:58:22.000000000 +0200 @@ -250,6 +250,8 @@ if (hdr->ih_arch != IH_CPU_M68K) #elif defined(__microblaze__) if (hdr->ih_arch != IH_CPU_MICROBLAZE) +#elif defined(__avr32__) + if (hdr->ih_arch != IH_CPU_AVR32) #elif defined(__nios2__) if (hdr->ih_arch != IH_CPU_NIOS2) #else @@ -1243,6 +1245,7 @@ case IH_CPU_MICROBLAZE: arch = "Microblaze"; break; case IH_CPU_NIOS: arch = "Nios"; break; case IH_CPU_NIOS2: arch = "Nios-II"; break; + case IH_CPU_AVR32: arch = "AVR32"; break; default: arch = "Unknown Architecture"; break; } diff -Nur u-boot-1.1.4/config.mk u-boot-1.1.4-avr32-20060621/config.mk --- u-boot-1.1.4/config.mk 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/config.mk 2006-06-21 11:58:26.000000000 +0200 @@ -139,10 +139,10 @@ endif endif -AFLAGS_DEBUG := -Wa,-gstabs +AFLAGS_DEBUG := -Wa,-g AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) -LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +LDFLAGS += -Bstatic -T $(LDSCRIPT) $(PLATFORM_LDFLAGS) # Location of a usable BFD library, where we define "usable" as # "built for ${HOST}, supports ${TARGET}". Sensible values are diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/ap7000/devices.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/devices.c --- u-boot-1.1.4/cpu/at32ap7xxx/ap7000/devices.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/devices.c 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,448 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +#include "../sm.h" + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +const struct clock_domain chip_clock[] = { + [CLOCK_CPU] = { + .reg = SM_PM_CPU_MASK, + .id = CLOCK_CPU, + .bridge = NO_DEVICE, + }, + [CLOCK_AHB] = { + .reg = SM_PM_AHB_MASK, + .id = CLOCK_AHB, + .bridge = NO_DEVICE, + }, + [CLOCK_APBA] = { + .reg = SM_PM_APBA_MASK, + .id = CLOCK_APBA, + .bridge = DEVICE_APBA_BRIDGE, + }, + [CLOCK_APBB] = { + .reg = SM_PM_APBB_MASK, + .id = CLOCK_APBB, + .bridge = DEVICE_APBB_BRIDGE, + }, +}; + +static const struct resource hebi_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 0 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 13 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 14 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 }, + }, + }, +}; +static const struct resource apba_bridge_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 1 }, + } + }, { + .type = RESOURCE_CLOCK, + .u = { + /* AHB-AHB Bridge */ + .clock = { CLOCK_AHB, 4 }, + }, + }, +}; +static const struct resource apbb_bridge_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 2 }, + }, + }, +}; +static const struct resource hramc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 3 }, + }, + }, +}; +static const struct resource pioa_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 10 }, + }, + }, +}; +static const struct resource piob_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 11 }, + }, + }, +}; +static const struct resource pioc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 12 }, + }, + }, +}; +static const struct resource piod_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 13 }, + }, + }, +}; +static const struct resource pioe_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 14 }, + }, + }, +}; +static const struct resource sm_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 0 }, + }, + }, +}; +static const struct resource intc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 1 }, + }, + }, +}; +static const struct resource hmatrix_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 2 }, + }, + }, +}; +#if defined(CFG_HPDC) +static const struct resource hpdc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 16 }, + }, + }, +}; +#endif +#if defined(CFG_MACB0) +static const struct resource macb0_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 8 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 6 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 }, + }, + }, +}; +#endif +#if defined(CFG_MACB1) +static const struct resource macb1_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 9 }, + }, + }, { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 7 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 }, + }, + }, +}; +#endif +#if defined(CFG_LCDC) +static const struct resource lcdc_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 7 }, + }, + }, +}; +#endif +#if defined(CFG_USART0) +static const struct resource usart0_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 3 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 }, + }, + }, +}; +#endif +#if defined(CFG_USART1) +static const struct resource usart1_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 4 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 }, + }, + }, +}; +#endif +#if defined(CFG_USART2) +static const struct resource usart2_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 5 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 }, + }, + }, +}; +#endif +#if defined(CFG_USART3) +static const struct resource usart3_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBA, 6 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 }, + }, + }, +}; +#endif +#if defined(CFG_MMCI) +static const struct resource mmci_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_APBB, 9 }, + }, + }, { + .type = RESOURCE_GPIO, + .u = { + .gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 }, + }, + }, +}; +#endif +#if defined(CFG_DMAC) +static const struct resource dmac_resource[] = { + { + .type = RESOURCE_CLOCK, + .u = { + .clock = { CLOCK_AHB, 10 }, + }, + }, +}; +#endif + +const struct device chip_device[] = { + [DEVICE_HEBI] = { + .regs = (void *)HSMC_BASE, + .nr_resources = ARRAY_SIZE(hebi_resource), + .resource = hebi_resource, + }, + [DEVICE_APBA_BRIDGE] = { + .nr_resources = ARRAY_SIZE(apba_bridge_resource), + .resource = apba_bridge_resource, + }, + [DEVICE_APBB_BRIDGE] = { + .nr_resources = ARRAY_SIZE(apbb_bridge_resource), + .resource = apbb_bridge_resource, + }, + [DEVICE_HRAMC] = { + .nr_resources = ARRAY_SIZE(hramc_resource), + .resource = hramc_resource, + }, + [DEVICE_PIOA] = { + .regs = (void *)PIOA_BASE, + .nr_resources = ARRAY_SIZE(pioa_resource), + .resource = pioa_resource, + }, + [DEVICE_PIOB] = { + .regs = (void *)PIOB_BASE, + .nr_resources = ARRAY_SIZE(piob_resource), + .resource = piob_resource, + }, + [DEVICE_PIOC] = { + .regs = (void *)PIOC_BASE, + .nr_resources = ARRAY_SIZE(pioc_resource), + .resource = pioc_resource, + }, + [DEVICE_PIOD] = { + .regs = (void *)PIOD_BASE, + .nr_resources = ARRAY_SIZE(piod_resource), + .resource = piod_resource, + }, + [DEVICE_PIOE] = { + .regs = (void *)PIOE_BASE, + .nr_resources = ARRAY_SIZE(pioe_resource), + .resource = pioe_resource, + }, + [DEVICE_SM] = { + .regs = (void *)SM_BASE, + .nr_resources = ARRAY_SIZE(sm_resource), + .resource = sm_resource, + }, + [DEVICE_INTC] = { + .regs = (void *)INTC_BASE, + .nr_resources = ARRAY_SIZE(intc_resource), + .resource = intc_resource, + }, + [DEVICE_HMATRIX] = { + .regs = (void *)HMATRIX_BASE, + .nr_resources = ARRAY_SIZE(hmatrix_resource), + .resource = hmatrix_resource, + }, +#if defined(CFG_HPDC) + [DEVICE_HPDC] = { + .nr_resources = ARRAY_SIZE(hpdc_resource), + .resource = hpdc_resource, + }, +#endif +#if defined(CFG_MACB0) + [DEVICE_MACB0] = { + .regs = (void *)MACB0_BASE, + .nr_resources = ARRAY_SIZE(macb0_resource), + .resource = macb0_resource, + }, +#endif +#if defined(CFG_MACB1) + [DEVICE_MACB1] = { + .regs = (void *)MACB1_BASE, + .nr_resources = ARRAY_SIZE(macb1_resource), + .resource = macb1_resource, + }, +#endif +#if defined(CFG_LCDC) + [DEVICE_LCDC] = { + .nr_resources = ARRAY_SIZE(lcdc_resource), + .resource = lcdc_resource, + }, +#endif +#if defined(CFG_USART0) + [DEVICE_USART0] = { + .regs = (void *)USART0_BASE, + .nr_resources = ARRAY_SIZE(usart0_resource), + .resource = usart0_resource, + }, +#endif +#if defined(CFG_USART1) + [DEVICE_USART1] = { + .regs = (void *)USART1_BASE, + .nr_resources = ARRAY_SIZE(usart1_resource), + .resource = usart1_resource, + }, +#endif +#if defined(CFG_USART2) + [DEVICE_USART2] = { + .regs = (void *)USART2_BASE, + .nr_resources = ARRAY_SIZE(usart2_resource), + .resource = usart2_resource, + }, +#endif +#if defined(CFG_USART3) + [DEVICE_USART3] = { + .regs = (void *)USART3_BASE, + .nr_resources = ARRAY_SIZE(usart3_resource), + .resource = usart3_resource, + }, +#endif +#if defined(CFG_MMCI) + [DEVICE_MMCI] = { + .regs = (void *)MMCI_BASE, + .nr_resources = ARRAY_SIZE(mmci_resource), + .resource = mmci_resource, + }, +#endif +#if defined(CFG_DMAC) + [DEVICE_DMAC] = { + .regs = (void *)DMAC_BASE, + .nr_resources = ARRAY_SIZE(dmac_resource), + .resource = dmac_resource, + }, +#endif +}; diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/ap7000/hebi.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/hebi.c --- u-boot-1.1.4/cpu/at32ap7xxx/ap7000/hebi.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/hebi.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +#include +#include +#include + +void cpu_enable_sdram(void) +{ + const struct device *hmatrix; + + hmatrix = get_device(DEVICE_HMATRIX); + + /* Set the SDRAM_ENABLE bit in the HEBI SFR */ + hmatrix2_writel(hmatrix, SFR4, 1 << 1); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/ap7000/Makefile u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/Makefile --- u-boot-1.1.4/cpu/at32ap7xxx/ap7000/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/ap7000/Makefile 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,42 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(SOC).a + +SRC = hebi.c devices.c +OBJ = $(addsuffix .o,$(basename $(SRC))) + +all: .depend $(LIB) + +$(LIB): $(OBJ) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SRC) + $(CC) -M $(CFLAGS) $(SRC) > $@ + +sinclude .depend + +######################################################################### diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/config.mk u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/config.mk --- u-boot-1.1.4/cpu/at32ap7xxx/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/config.mk 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,22 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -ffixed-r5 -mno-pic diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/cpu.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/cpu.c --- u-boot-1.1.4/cpu/at32ap7xxx/cpu.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/cpu.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "hsmc3.h" + +int cpu_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + const struct device *hebi; + extern void _evba(void); + char *p; + + gd->cpu_hz = CFG_OSC0_HZ; + + /* fff03400: 00010001 04030402 00050005 10011103 */ + hebi = get_device(DEVICE_HEBI); + hsmc3_writel(hebi, MODE0, 0x00031103); + hsmc3_writel(hebi, CYCLE0, 0x000c000d); + hsmc3_writel(hebi, PULSE0, 0x0b0a0906); + hsmc3_writel(hebi, SETUP0, 0x00010002); + + pm_init(); + + sysreg_write(SYSREG_EVBA, &_evba); + asm volatile("csrf %0" : : "i"(SYSREG_SR_EM_OFFSET)); + gd->console_uart = get_device(CFG_CONSOLE_UART_DEV); + + /* Lock everything that mess with the flash in the icache */ + for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ); + p += CFG_ICACHE_LINESZ) + asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory"); + + return 0; +} + +void enable_interrupts(void) +{ + asm volatile("csrf %0" : : "n"(SYSREG_SR_GM_OFFSET)); +} + +int disable_interrupts(void) +{ + unsigned long sr; + + sr = sysreg_read(SYSREG_SR); + asm volatile("ssrf %0" : : "n"(SYSREG_SR_GM_OFFSET)); + + return SYSREG_GETBF(SR_GM, sr); +} + +void prepare_to_boot(void) +{ + /* Flush both caches and the write buffer */ + asm volatile("cache %0[4], 010\n\t" + "cache %0[0], 000\n\t" + "sync 0" : : "r"(0) : "memory"); +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + /* This will reset the CPU core, caches, MMU and all internal busses */ + dbgreg_write(DBGREG_DC, DBGREG_BIT(DC_RES)); + + /* Flush the pipeline before we declare it a failure */ + asm volatile("sub pc, pc, 4"); + + return -1; +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/dcache_clean.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/dcache_clean.c --- u-boot-1.1.4/cpu/at32ap7xxx/dcache_clean.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/dcache_clean.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +void dcache_clean_range(volatile void *start, size_t size) +{ + unsigned long v, begin, end, linesz; + + linesz = CFG_DCACHE_LINESZ; + + /* You asked for it, you got it */ + begin = (unsigned long)start & ~(linesz - 1); + end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + + for (v = begin; v < end; v += linesz) + dcache_clean_line((void *)v); + + sync_write_buffer(); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/dcache_invalidate.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/dcache_invalidate.c --- u-boot-1.1.4/cpu/at32ap7xxx/dcache_invalidate.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/dcache_invalidate.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +void dcache_invalidate_range(volatile void *start, size_t size) +{ + unsigned long v, begin, end, linesz; + + linesz = CFG_DCACHE_LINESZ; + + /* You asked for it, you got it */ + begin = (unsigned long)start & ~(linesz - 1); + end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); + + for (v = begin; v < end; v += linesz) + dcache_invalidate_line((void *)v); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/device.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/device.c --- u-boot-1.1.4/cpu/at32ap7xxx/device.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/device.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +#include "sm.h" + +struct device_state { + int refcount; +}; + +static struct device_state device_state[NR_DEVICES]; + +static int claim_resource(const struct resource *res) +{ + int ret = 0; + + switch (res->type) { + case RESOURCE_GPIO: + ret = gpio_set_func(res->u.gpio.gpio_dev, + res->u.gpio.start, + res->u.gpio.nr_pins, + res->u.gpio.func); + break; + case RESOURCE_CLOCK: + ret = pm_enable_clock(res->u.clock.id, res->u.clock.index); + break; + } + + return ret; +} + +static void free_resource(const struct resource *res) +{ + switch (res->type) { + case RESOURCE_GPIO: + gpio_free(res->u.gpio.gpio_dev, res->u.gpio.start, + res->u.gpio.nr_pins); + break; + case RESOURCE_CLOCK: + pm_disable_clock(res->u.clock.id, res->u.clock.index); + break; + } +} + +static int init_dev(const struct device *dev) +{ + unsigned int i; + int ret = 0; + + for (i = 0; i < dev->nr_resources; i++) { + ret = claim_resource(&dev->resource[i]); + if (ret) + goto cleanup; + } + + return 0; + +cleanup: + while (i--) + free_resource(&dev->resource[i]); + + return ret; +} + +const struct device *get_device(enum device_id devid) +{ + struct device_state *devstate; + const struct device *dev; + unsigned long flags; + int initialized = 0; + int ret = 0; + + devstate = &device_state[devid]; + dev = &chip_device[devid]; + + local_irq_save(flags); + if (devstate->refcount++) + initialized = 1; + local_irq_restore(flags); + + if (!initialized) + ret = init_dev(dev); + + return ret ? NULL : dev; +} + +void put_device(const struct device *dev) +{ + struct device_state *devstate; + unsigned long devid, flags; + + devid = (unsigned long)(dev - chip_device) / sizeof(struct device); + devstate = &device_state[devid]; + + local_irq_save(flags); + devstate--; + if (!devstate) { + unsigned int i; + for (i = 0; i < dev->nr_resources; i++) + free_resource(&dev->resource[i]); + } + local_irq_restore(flags); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/entry.S u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/entry.S --- u-boot-1.1.4/cpu/at32ap7xxx/entry.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/entry.S 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + + .section .text.exception,"ax" + .global _evba + .type _evba,@function + .align 10 +_evba: + .irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 + .align 2 + rjmp unknown_exception + .endr + + .type unknown_exception, @function +unknown_exception: + pushm r0-r12 + sub r8, sp, REG_R12 - REG_R0 - 4 + mov r9, lr + mfsr r10, SYSREG_RAR_EX + mfsr r11, SYSREG_RSR_EX + pushm r8-r11 + mfsr r12, SYSREG_ECR + mov r11, sp + rcall do_unknown_exception +1: rjmp 1b diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/exception.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/exception.c --- u-boot-1.1.4/cpu/at32ap7xxx/exception.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/exception.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +static const char * const cpu_modes[8] = { + "Application", "Supervisor", "Interrupt level 0", "Interrupt level 1", + "Interrupt level 2", "Interrupt level 3", "Exception", "NMI" +}; + +static void dump_mem(const char *str, unsigned long bottom, unsigned long top) +{ + unsigned long p; + int i; + + printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); + + for (p = bottom & ~31; p < top; ) { + printf("%04lx: ", p & 0xffff); + + for (i = 0; i < 8; i++, p += 4) { + unsigned int val; + + if (p < bottom || p >= top) + printf(" "); + else { + val = *(unsigned long *)p; + printf("%08x ", val); + } + } + printf("\n"); + } +} + +void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) +{ + unsigned int mode; + + printf("\n *** Unhandled exception %u at PC=0x%08lx\n", ecr, regs->pc); + + switch (ecr) { + case ECR_BUS_ERROR_WRITE: + case ECR_BUS_ERROR_READ: + printf("Bus error at address 0x%08lx\n", + sysreg_read(SYSREG_BEAR)); + break; + case ECR_TLB_MULTIPLE: + case ECR_INSN_ADDR: + case ECR_TLB_PROTECTION_X: + case ECR_DATA_ADDR_R: + case ECR_DATA_ADDR_W: + case ECR_TLB_PROTECTION_R: + case ECR_TLB_PROTECTION_W: + case ECR_DIRTY_PAGE: + case ECR_TLB_MISS_X: + case ECR_TLB_MISS_R: + case ECR_TLB_MISS_W: + printf("MMU exception at address 0x%08lx\n", + sysreg_read(SYSREG_TLBEAR)); + break; + } + + printf(" pc: %08lx lr: %08lx sp: %08lx r12: %08lx\n", + regs->pc, regs->lr, regs->sp, regs->r12); + printf(" r11: %08lx r10: %08lx r9: %08lx r8: %08lx\n", + regs->r11, regs->r10, regs->r9, regs->r8); + printf(" r7: %08lx r6: %08lx r5: %08lx r4: %08lx\n", + regs->r7, regs->r6, regs->r5, regs->r4); + printf(" r3: %08lx r2: %08lx r1: %08lx r0: %08lx\n", + regs->r3, regs->r2, regs->r1, regs->r0); + printf("Flags: %c%c%c%c%c\n", + regs->sr & SR_Q ? 'Q' : 'q', + regs->sr & SR_V ? 'V' : 'v', + regs->sr & SR_N ? 'N' : 'n', + regs->sr & SR_Z ? 'Z' : 'z', + regs->sr & SR_C ? 'C' : 'c'); + printf("Mode bits: %c%c%c%c%c%c%c%c%c\n", + regs->sr & SR_H ? 'H' : 'h', + regs->sr & SR_R ? 'R' : 'r', + regs->sr & SR_J ? 'J' : 'j', + regs->sr & SR_EM ? 'E' : 'e', + regs->sr & SR_I3M ? '3' : '.', + regs->sr & SR_I2M ? '2' : '.', + regs->sr & SR_I1M ? '1' : '.', + regs->sr & SR_I0M ? '0' : '.', + regs->sr & SR_GM ? 'G' : 'g'); + mode = (regs->sr >> SYSREG_SR_M0_OFFSET) & 7; + printf("CPU Mode: %s\n", cpu_modes[mode]); + + /* Avoid exception loops */ + if (regs->sp >= CFG_INIT_SP_ADDR + || regs->sp < (CFG_INIT_SP_ADDR - CONFIG_STACKSIZE)) + printf("\nStack pointer seems bogus, won't do stack dump\n"); + else + dump_mem("\nStack: ", regs->sp, CFG_INIT_SP_ADDR); + + panic("Unhandled exception\n"); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/hsdramc1.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsdramc1.h --- u-boot-1.1.4/cpu/at32ap7xxx/hsdramc1.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsdramc1.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_HSDRAMC1_H__ +#define __ASM_AVR32_HSDRAMC1_H__ + +/* HSDRAMC1 register offsets */ +#define HSDRAMC1_MR 0x0000 +#define HSDRAMC1_TR 0x0004 +#define HSDRAMC1_CR 0x0008 +#define HSDRAMC1_HSR 0x000c +#define HSDRAMC1_LPR 0x0010 +#define HSDRAMC1_IER 0x0014 +#define HSDRAMC1_IDR 0x0018 +#define HSDRAMC1_IMR 0x001c +#define HSDRAMC1_ISR 0x0020 +#define HSDRAMC1_MDR 0x0024 +#define HSDRAMC1_VERSION 0x00fc + +/* Bitfields in MR */ +#define HSDRAMC1_MODE_OFFSET 0 +#define HSDRAMC1_MODE_SIZE 3 + +/* Bitfields in TR */ +#define HSDRAMC1_COUNT_OFFSET 0 +#define HSDRAMC1_COUNT_SIZE 12 + +/* Bitfields in CR */ +#define HSDRAMC1_NC_OFFSET 0 +#define HSDRAMC1_NC_SIZE 2 +#define HSDRAMC1_NR_OFFSET 2 +#define HSDRAMC1_NR_SIZE 2 +#define HSDRAMC1_NB_OFFSET 4 +#define HSDRAMC1_NB_SIZE 1 +#define HSDRAMC1_CAS_OFFSET 5 +#define HSDRAMC1_CAS_SIZE 2 +#define HSDRAMC1_DBW_OFFSET 7 +#define HSDRAMC1_DBW_SIZE 1 +#define HSDRAMC1_TWR_OFFSET 8 +#define HSDRAMC1_TWR_SIZE 4 +#define HSDRAMC1_TRC_OFFSET 12 +#define HSDRAMC1_TRC_SIZE 4 +#define HSDRAMC1_TRP_OFFSET 16 +#define HSDRAMC1_TRP_SIZE 4 +#define HSDRAMC1_TRCD_OFFSET 20 +#define HSDRAMC1_TRCD_SIZE 4 +#define HSDRAMC1_TRAS_OFFSET 24 +#define HSDRAMC1_TRAS_SIZE 4 +#define HSDRAMC1_TXSR_OFFSET 28 +#define HSDRAMC1_TXSR_SIZE 4 + +/* Bitfields in HSR */ +#define HSDRAMC1_DA_OFFSET 0 +#define HSDRAMC1_DA_SIZE 1 + +/* Bitfields in LPR */ +#define HSDRAMC1_LPCB_OFFSET 0 +#define HSDRAMC1_LPCB_SIZE 2 +#define HSDRAMC1_PASR_OFFSET 4 +#define HSDRAMC1_PASR_SIZE 3 +#define HSDRAMC1_TCSR_OFFSET 8 +#define HSDRAMC1_TCSR_SIZE 2 +#define HSDRAMC1_DS_OFFSET 10 +#define HSDRAMC1_DS_SIZE 2 +#define HSDRAMC1_TIMEOUT_OFFSET 12 +#define HSDRAMC1_TIMEOUT_SIZE 2 + +/* Bitfields in IER */ + +/* Bitfields in IDR */ +#define HSDRAMC1_RES_OFFSET 0 +#define HSDRAMC1_RES_SIZE 1 + +/* Bitfields in IMR */ + +/* Bitfields in ISR */ + +/* Bitfields in MDR */ +#define HSDRAMC1_MD_OFFSET 0 +#define HSDRAMC1_MD_SIZE 2 + +/* Bitfields in VERSION */ +#define HSDRAMC1_VERSION_OFFSET 0 +#define HSDRAMC1_VERSION_SIZE 12 +#define HSDRAMC1_MFN_OFFSET 16 +#define HSDRAMC1_MFN_SIZE 3 + +/* Constants for MODE */ +#define HSDRAMC1_MODE_NORMAL 0 +#define HSDRAMC1_MODE_NOP 1 +#define HSDRAMC1_MODE_BANKS_PRECHARGE 2 +#define HSDRAMC1_MODE_LOAD_MODE 3 +#define HSDRAMC1_MODE_AUTO_REFRESH 4 +#define HSDRAMC1_MODE_EXT_LOAD_MODE 5 +#define HSDRAMC1_MODE_POWER_DOWN 6 + +/* Constants for NC */ +#define HSDRAMC1_NC_8_COLUMN_BITS 0 +#define HSDRAMC1_NC_9_COLUMN_BITS 1 +#define HSDRAMC1_NC_10_COLUMN_BITS 2 +#define HSDRAMC1_NC_11_COLUMN_BITS 3 + +/* Constants for NR */ +#define HSDRAMC1_NR_11_ROW_BITS 0 +#define HSDRAMC1_NR_12_ROW_BITS 1 +#define HSDRAMC1_NR_13_ROW_BITS 2 + +/* Constants for NB */ +#define HSDRAMC1_NB_TWO_BANKS 0 +#define HSDRAMC1_NB_FOUR_BANKS 1 + +/* Constants for CAS */ +#define HSDRAMC1_CAS_ONE_CYCLE 1 +#define HSDRAMC1_CAS_TWO_CYCLES 2 + +/* Constants for DBW */ +#define HSDRAMC1_DBW_32_BITS 0 +#define HSDRAMC1_DBW_16_BITS 1 + +/* Constants for TIMEOUT */ +#define HSDRAMC1_TIMEOUT_AFTER_END 0 +#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END 1 +#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END 2 + +/* Constants for MD */ +#define HSDRAMC1_MD_SDRAM 0 +#define HSDRAMC1_MD_LOW_POWER_SDRAM 1 + +/* Bit manipulation macros */ +#define HSDRAMC1_BIT(name) (1 << HSDRAMC1_##name##_OFFSET) +#define HSDRAMC1_BF(name,value) (((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) << HSDRAMC1_##name##_OFFSET) +#define HSDRAMC1_BFEXT(name,value) (((value) >> HSDRAMC1_##name##_OFFSET) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) +#define HSDRAMC1_BFINS(name,value,old) (((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1) << HSDRAMC1_##name##_OFFSET)) | HSDRAMC1_BF(name,value)) + +/* Register access macros */ +#define hsdramc1_readl(port,reg) readl((port)->regs + HSDRAMC1_##reg) +#define hsdramc1_writel(port,reg,value) writel((value), (port)->regs + HSDRAMC1_##reg) + +#endif /* __ASM_AVR32_HSDRAMC1_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsdramc.c --- u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsdramc.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CFG_HSDRAMC +#include +#include + +#include + +#include "hsdramc1.h" + +struct hsdramc { + const struct device *hebi; + void *regs; +}; + +static struct hsdramc hsdramc; + +unsigned long sdram_init(const struct sdram_info *info) +{ + unsigned long *sdram = (unsigned long *)uncached(info->phys_addr); + unsigned long sdram_size; + unsigned long tmp; + unsigned long bus_hz; + unsigned int i; + + hsdramc.hebi = get_device(DEVICE_HEBI); + if (!hsdramc.hebi) + return 0; + + /* FIXME: Both of these lines are complete hacks */ + hsdramc.regs = hsdramc.hebi->regs + 0x400; + bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id); + + cpu_enable_sdram(); + + sdram_size = 1 << (info->row_bits + info->col_bits + + info->bank_bits + 2); + + tmp = (HSDRAMC1_BF(NC, info->col_bits - 8) + | HSDRAMC1_BF(NR, info->row_bits - 11) + | HSDRAMC1_BF(NB, info->bank_bits - 1) + | HSDRAMC1_BF(CAS, info->cas) + | HSDRAMC1_BF(TWR, info->twr) + | HSDRAMC1_BF(TRC, info->trc) + | HSDRAMC1_BF(TRP, info->trp) + | HSDRAMC1_BF(TRCD, info->trcd) + | HSDRAMC1_BF(TRAS, info->tras) + | HSDRAMC1_BF(TXSR, info->txsr)); + hsdramc1_writel(&hsdramc, CR, tmp); + + /* + * Initialization sequence for SDRAM, from the data sheet: + * + * 1. A minimum pause of 200 us is provided to precede any + * signal toggle. + */ + udelay(200); + + /* + * 2. A Precharge All command is issued to the SDRAM + */ + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE); + hsdramc1_readl(&hsdramc, MR); + writel(0, sdram); + + /* + * 3. Eight auto-refresh (CBR) cycles are provided + */ + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH); + hsdramc1_readl(&hsdramc, MR); + for (i = 0; i < 8; i++) + writel(0, sdram); + + /* + * 4. A mode register set (MRS) cycle is issued to program + * SDRAM parameters, in particular CAS latency and burst + * length. + * + * CAS from info struct, burst length 1, serial burst type + */ + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE); + hsdramc1_readl(&hsdramc, MR); + writel(0, sdram + (info->cas << 4)); + + /* + * 5. A Normal Mode command is provided, 3 clocks after tMRD + * is met. + * + * From the timing diagram, it looks like tMRD is 3 + * cycles...try a dummy read from APB. + */ + hsdramc1_readl(&hsdramc, MR); + hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL); + hsdramc1_readl(&hsdramc, MR); + writel(0, sdram); + + /* + * 6. Write refresh rate into SDRAMC refresh timer count + * register (refresh rate = timing between refresh cycles). + * + * 15.6 us is a typical value for a burst of length one + */ + hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000); + + printf("SDRAM: %u MB at address 0x%08lx\n", + sdram_size >> 20, info->phys_addr); + + printf("Testing SDRAM..."); + for (i = 0; i < sdram_size / 4; i++) + sdram[i] = i; + + for (i = 0; i < sdram_size / 4; i++) { + tmp = sdram[i]; + if (tmp != i) { + printf("FAILED at address 0x%08lx\n", + info->phys_addr + i * 4); + printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i); + return 0; + } + } + + puts("OK\n"); + + return sdram_size; +} + +#endif /* CFG_HSDRAMC */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/hsmc3.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsmc3.h --- u-boot-1.1.4/cpu/at32ap7xxx/hsmc3.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/hsmc3.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,156 @@ +/* + * Register definitions for HSMC3 + * + * Static Memory Controller + */ +#ifndef __ASM_AVR32_HSMC3_H__ +#define __ASM_AVR32_HSMC3_H__ + +/* HSMC3 register offsets */ +#define HSMC3_SETUP0 0x0000 +#define HSMC3_PULSE0 0x0004 +#define HSMC3_CYCLE0 0x0008 +#define HSMC3_MODE0 0x000c +#define HSMC3_SETUP1 0x0010 +#define HSMC3_PULSE1 0x0014 +#define HSMC3_CYCLE1 0x0018 +#define HSMC3_MODE1 0x001c +#define HSMC3_SETUP2 0x0020 +#define HSMC3_PULSE2 0x0024 +#define HSMC3_CYCLE2 0x0028 +#define HSMC3_MODE2 0x002c +#define HSMC3_SETUP3 0x0030 +#define HSMC3_PULSE3 0x0034 +#define HSMC3_CYCLE3 0x0038 +#define HSMC3_MODE3 0x003c +#define HSMC3_SETUP4 0x0040 +#define HSMC3_PULSE4 0x0044 +#define HSMC3_CYCLE4 0x0048 +#define HSMC3_MODE4 0x004c +#define HSMC3_SETUP5 0x0050 +#define HSMC3_PULSE5 0x0054 +#define HSMC3_CYCLE5 0x0058 +#define HSMC3_MODE5 0x005c + +/* Bitfields in SETUP0 */ +#define HSMC3_NWE_SETUP_OFFSET 0 +#define HSMC3_NWE_SETUP_SIZE 6 +#define HSMC3_NCS_WR_SETUP_OFFSET 8 +#define HSMC3_NCS_WR_SETUP_SIZE 6 +#define HSMC3_NRD_SETUP_OFFSET 16 +#define HSMC3_NRD_SETUP_SIZE 6 +#define HSMC3_NCS_RD_SETUP_OFFSET 24 +#define HSMC3_NCS_RD_SETUP_SIZE 6 + +/* Bitfields in PULSE0 */ +#define HSMC3_NWE_PULSE_OFFSET 0 +#define HSMC3_NWE_PULSE_SIZE 7 +#define HSMC3_NCS_WR_PULSE_OFFSET 8 +#define HSMC3_NCS_WR_PULSE_SIZE 7 +#define HSMC3_NRD_PULSE_OFFSET 16 +#define HSMC3_NRD_PULSE_SIZE 7 +#define HSMC3_NCS_RD_PULSE_OFFSET 24 +#define HSMC3_NCS_RD_PULSE_SIZE 7 + +/* Bitfields in CYCLE0 */ +#define HSMC3_NWE_CYCLE_OFFSET 0 +#define HSMC3_NWE_CYCLE_SIZE 9 +#define HSMC3_NRD_CYCLE_OFFSET 16 +#define HSMC3_NRD_CYCLE_SIZE 9 + +/* Bitfields in MODE0 */ +#define HSMC3_READ_MODE_OFFSET 0 +#define HSMC3_READ_MODE_SIZE 1 +#define HSMC3_WRITE_MODE_OFFSET 1 +#define HSMC3_WRITE_MODE_SIZE 1 +#define HSMC3_EXNW_MODE_OFFSET 4 +#define HSMC3_EXNW_MODE_SIZE 2 +#define HSMC3_BAT_OFFSET 8 +#define HSMC3_BAT_SIZE 1 +#define HSMC3_DBW_OFFSET 12 +#define HSMC3_DBW_SIZE 2 +#define HSMC3_TDF_CYCLES_OFFSET 16 +#define HSMC3_TDF_CYCLES_SIZE 4 +#define HSMC3_TDF_MODE_OFFSET 20 +#define HSMC3_TDF_MODE_SIZE 1 +#define HSMC3_PMEN_OFFSET 24 +#define HSMC3_PMEN_SIZE 1 +#define HSMC3_PS_OFFSET 28 +#define HSMC3_PS_SIZE 2 + +/* Bitfields in SETUP1 */ + +/* Bitfields in PULSE1 */ + +/* Bitfields in CYCLE1 */ + +/* Bitfields in MODE1 */ +#define HSMC3_PD_OFFSET 28 +#define HSMC3_PD_SIZE 2 + +/* Bitfields in SETUP2 */ + +/* Bitfields in PULSE2 */ + +/* Bitfields in CYCLE2 */ + +/* Bitfields in MODE2 */ + +/* Bitfields in SETUP3 */ + +/* Bitfields in PULSE3 */ + +/* Bitfields in CYCLE3 */ + +/* Bitfields in MODE3 */ + +/* Bitfields in SETUP4 */ + +/* Bitfields in PULSE4 */ + +/* Bitfields in CYCLE4 */ + +/* Bitfields in MODE4 */ + +/* Bitfields in SETUP5 */ + +/* Bitfields in PULSE5 */ + +/* Bitfields in CYCLE5 */ + +/* Bitfields in MODE5 */ + +/* Constants for READ_MODE */ +#define HSMC3_READ_MODE_NCS_CONTROLLED 0 +#define HSMC3_READ_MODE_NRD_CONTROLLED 1 + +/* Constants for WRITE_MODE */ +#define HSMC3_WRITE_MODE_NCS_CONTROLLED 0 +#define HSMC3_WRITE_MODE_NWE_CONTROLLED 1 + +/* Constants for EXNW_MODE */ +#define HSMC3_EXNW_MODE_DISABLED 0 +#define HSMC3_EXNW_MODE_RESERVED 1 +#define HSMC3_EXNW_MODE_FROZEN 2 +#define HSMC3_EXNW_MODE_READY 3 + +/* Constants for BAT */ +#define HSMC3_BAT_BYTE_SELECT 0 +#define HSMC3_BAT_BYTE_WRITE 1 + +/* Constants for DBW */ +#define HSMC3_DBW_8_BITS 0 +#define HSMC3_DBW_16_BITS 1 +#define HSMC3_DBW_32_BITS 2 + +/* Bit manipulation macros */ +#define HSMC3_BIT(name) (1 << HSMC3_##name##_OFFSET) +#define HSMC3_BF(name,value) (((value) & ((1 << HSMC3_##name##_SIZE) - 1)) << HSMC3_##name##_OFFSET) +#define HSMC3_BFEXT(name,value) (((value) >> HSMC3_##name##_OFFSET) & ((1 << HSMC3_##name##_SIZE) - 1)) +#define HSMC3_BFINS(name,value,old) (((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) << HSMC3_##name##_OFFSET)) | HSMC3_BF(name,value)) + +/* Register access macros */ +#define hsmc3_readl(port,reg) readl((port)->regs + HSMC3_##reg) +#define hsmc3_writel(port,reg,value) writel((value), (port)->regs + HSMC3_##reg) + +#endif /* __ASM_AVR32_HSMC3_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/Makefile u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/Makefile --- u-boot-1.1.4/cpu/at32ap7xxx/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/Makefile 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,46 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.S +START_OBJ = start.o +SRC = cpu.c hsdramc.c mmc.c entry.S exception.c +SRC += dcache_clean.c dcache_invalidate.c +SRC += device.c pm.c pio.c +OBJ = $(addsuffix .o,$(basename $(SRC))) + +all: .depend $(START_OBJ) $(LIB) + +$(LIB): $(OBJ) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(START) $(SRC) + $(CC) -M $(CFLAGS) $(START) $(SRC) > $@ + +sinclude .depend + +######################################################################### diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/mmc.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/mmc.c --- u-boot-1.1.4/cpu/at32ap7xxx/mmc.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/mmc.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,499 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define xDEBUG +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "mmci.h" + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args) +#else +#define pr_debug(...) do { } while(0) +#endif + +#ifdef CONFIG_MMC + +#ifndef CFG_MMC_CLK_OD +#define CFG_MMC_CLK_OD 150000 +#endif + +#ifndef CFG_MMC_CLK_PP +#define CFG_MMC_CLK_PP 5000000 +#endif + +#ifndef CFG_MMC_BLKLEN +#define CFG_MMC_BLKLEN 512 +#endif + +#ifndef CFG_OP_COND +#define CFG_OP_COND 0x00100000 +#endif + +#define MMC_DEFAULT_RCA 1 + +static unsigned long status; +static unsigned long mmc_bread(int dev, unsigned long start, + lbaint_t blkcnt, unsigned long *buffer); + +struct mmci { + void *regs; + unsigned int rca; + block_dev_desc_t blkdev; + const struct device *dev; +}; + +struct mmci mmci = { + .regs = (void *)MMCI_BASE, + .blkdev = { + .if_type = IF_TYPE_MMC, + .block_read = mmc_bread, + }, +}; + +block_dev_desc_t *mmc_get_dev(int dev) +{ + return &mmci.blkdev; +} + +static void mci_set_mode(unsigned long hz, unsigned long blklen) +{ + unsigned long bus_hz; + unsigned long clkdiv; + + bus_hz = pm_get_clock_freq(mmci.dev->resource[0].u.clock.id); + clkdiv = (bus_hz / hz) / 2 - 1; + + pr_debug("mmc: setting clock %lu Hz, block size %lu\n", + hz, blklen); + + if (clkdiv & ~255UL) { + clkdiv = 255; + printf("mmc: clock %lu too low; setting CLKDIV to 255\n", + hz); + } + + blklen &= 0xfffc; + mmci_writel(&mmci, MCI_MR, (MMCI_MKBF(MCI_MR_CLKDIV, clkdiv) + | MMCI_MKBF(MCI_MR_BLKLEN, blklen))); +} + +#define RESP_NO_CRC 1 +#define R1 MMCI_MKBF(MCI_CMDR_RSPTYP, 1) +#define R2 MMCI_MKBF(MCI_CMDR_RSPTYP, 2) +#define R3 (R1 | RESP_NO_CRC) +#define R6 R1 +#define NID MMCI_MKBF(MCI_CMDR_MAXLAT, 0) +#define NCR MMCI_MKBF(MCI_CMDR_MAXLAT, 1) +#define TRCMD_START MMCI_MKBF(MCI_CMDR_TRCMD, 1) +#define TRDIR_READ MMCI_MKBF(MCI_CMDR_TRDIR, 1) +#define TRTYP_BLOCK MMCI_MKBF(MCI_CMDR_TRTYP, 0) +#define INIT_CMD MMCI_MKBF(MCI_CMDR_SPCMD, 1) +#define OPEN_DRAIN MMCI_MKBF(MCI_CMDR_OPDCMD, 1) + +#define ERROR_FLAGS (MMCI_BIT(MCI_SR_DTOE) \ + | MMCI_BIT(MCI_SR_RDIRE) \ + | MMCI_BIT(MCI_SR_RENDE) \ + | MMCI_BIT(MCI_SR_RINDE) \ + | MMCI_BIT(MCI_SR_RTOE)) + +static int +mmc_cmd(unsigned long cmd, unsigned long arg, + void *resp, unsigned long flags) +{ + unsigned long *response = resp; + int i, response_words = 0; + unsigned long error_flags; + + pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n", + cmd, arg, flags); + + error_flags = ERROR_FLAGS; + if (!(flags & RESP_NO_CRC)) + error_flags |= MMCI_BIT(MCI_SR_RCRCE); + + flags &= ~MMCI_MKBF(MCI_CMDR_CMDNB, ~0UL); + + if (MMCI_GETBF(MCI_CMDR_RSPTYP, flags) == 1) + response_words = 1; + else if (MMCI_GETBF(MCI_CMDR_RSPTYP, flags) == 2) + response_words = 4; + + mmci_writel(&mmci, MCI_ARGR, arg); + mmci_writel(&mmci, MCI_CMDR, cmd | flags); + do { + udelay(40); + status = mmci_readl(&mmci, MCI_SR); + } while (!(status & MMCI_BIT(MCI_SR_CMDRDY))); + + pr_debug("mmc: status 0x%08lx\n", status); + + if (status & ERROR_FLAGS) { + printf("mmc: command %lu failed (status: 0x%08lx)\n", + cmd, status); + return -EIO; + } + + if (response_words) + pr_debug("mmc: response:"); + + for (i = 0; i < response_words; i++) { + response[i] = mmci_readl(&mmci, MCI_RSPR); + pr_debug(" %08lx", response[i]); + } + pr_debug("\n"); + + return 0; +} + +static int mmc_acmd(unsigned long cmd, unsigned long arg, + void *resp, unsigned long flags) +{ + unsigned long aresp[4]; + int ret; + + /* + * Seems like the APP_CMD part of an ACMD has 64 cycles max + * latency even though the ACMD part doesn't. This isn't + * entirely clear in the SD Card spec, but some cards refuse + * to work if we attempt to use 5 cycles max latency here... + */ + ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp, + R1 | NCR | (flags & OPEN_DRAIN)); + if (ret) + return ret; + if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD) + return -ENODEV; + + ret = mmc_cmd(cmd, arg, resp, flags); + return ret; +} + +static unsigned long +mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, + unsigned long *buffer) +{ + int ret, i = 0; + unsigned long resp[4]; + unsigned long card_status, data; + unsigned long wordcount; + struct mmci *mmc = &mmci; + + if (blkcnt == 0) + return 0; + + pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n", + dev, start, blkcnt); + + /* Put the device into Transfer state */ + ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc->rca << 16, resp, R1 | NCR); + if (ret) goto fail; + + /* Set block length */ + ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc->blkdev.blksz, resp, R1 | NCR); + if (ret) goto fail; + + pr_debug("MCI_DTOR = %08lx\n", mmci_readl(&mmci, MCI_DTOR)); + + for (i = 0; i < blkcnt; i++, start++) { + ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, + start * mmc->blkdev.blksz, resp, + (R1 | NCR | TRCMD_START | TRDIR_READ + | TRTYP_BLOCK)); + if (ret) goto fail; + + ret = -EIO; + wordcount = 0; + do { + do { + status = mmci_readl(&mmci, MCI_SR); + if (status & (ERROR_FLAGS + | MMCI_BIT(MCI_SR_OVRE))) + goto fail; + } while (!(status & MMCI_BIT(MCI_SR_RXRDY))); + + if (status & MMCI_BIT(MCI_SR_RXRDY)) { + data = mmci_readl(&mmci, MCI_RDR); + // pr_debug("%x\n", data); + *buffer++ = data; + wordcount++; + } + } while(wordcount < (512 / 4)); + + pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount); + + do { + status = mmci_readl(&mmci, MCI_SR); + } while (!(status & MMCI_BIT(MCI_SR_BLKE))); + + putc('.'); + } + +out: + /* Put the device back into Standby state */ + mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + return i; + +fail: + printf("mmc: bread failed, SR = %08lx", status); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc->rca << 16, &card_status, R1 | NCR); + printf(", card status = %08lx\n", card_status); + goto out; +} + +static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) +{ + cid->mid = resp[0] >> 24; + cid->oid = (resp[0] >> 8) & 0xffff; + cid->pnm[0] = resp[0]; + cid->pnm[1] = resp[1] >> 24; + cid->pnm[2] = resp[1] >> 16; + cid->pnm[3] = resp[1] >> 8; + cid->pnm[4] = resp[1]; + cid->pnm[5] = resp[2] >> 24; + cid->pnm[6] = 0; + cid->prv = resp[2] >> 16; + cid->psn = (resp[2] << 16) | (resp[3] >> 16); + cid->mdt = resp[3] >> 8; +} + +static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) +{ + cid->mid = resp[0] >> 24; + cid->oid = (resp[0] >> 8) & 0xffff; + cid->pnm[0] = resp[0]; + cid->pnm[1] = resp[1] >> 24; + cid->pnm[2] = resp[1] >> 16; + cid->pnm[3] = resp[1] >> 8; + cid->pnm[4] = resp[1]; + cid->pnm[5] = 0; + cid->pnm[6] = 0; + cid->prv = resp[2] >> 24; + cid->psn = (resp[2] << 8) | (resp[3] >> 24); + cid->mdt = (resp[3] >> 8) & 0x0fff; +} + +static void mmc_dump_cid(const struct mmc_cid *cid) +{ + printf("Manufacturer ID: %02lX\n", cid->mid); + printf("OEM/Application ID: %04lX\n", cid->oid); + printf("Product name: %s\n", cid->pnm); + printf("Product Revision: %lu.%lu\n", + cid->prv >> 4, cid->prv & 0x0f); + printf("Product Serial Number: %lu\n", cid->psn); + printf("Manufacturing Date: %02lu/%02lu\n", + cid->mdt >> 4, cid->mdt & 0x0f); +} + +static void mmc_dump_csd(const struct mmc_csd *csd) +{ + unsigned long *csd_raw = (unsigned long *)csd; + printf("CSD data: %08lx %08lx %08lx %08lx\n", + csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); + printf("CSD structure version: 1.%u\n", csd->csd_structure); + printf("MMC System Spec version: %u\n", csd->spec_vers); + printf("Card command classes: %03x\n", csd->ccc); + printf("Read block length: %u\n", 1 << csd->read_bl_len); + if (csd->read_bl_partial) + puts("Supports partial reads\n"); + else + puts("Does not support partial reads\n"); + printf("Write block length: %u\n", 1 << csd->write_bl_len); + if (csd->write_bl_partial) + puts("Supports partial writes\n"); + else + puts("Does not support partial writes\n"); + if (csd->wp_grp_enable) + printf("Supports group WP: %u\n", csd->wp_grp_size + 1); + else + puts("Does not support group WP\n"); + printf("Card capacity: %u bytes\n", + (csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) * + (1 << csd->read_bl_len)); + printf("File format: %u/%u\n", + csd->file_format_grp, csd->file_format); + puts("Write protection: "); + if (csd->perm_write_protect) + puts(" permanent"); + if (csd->tmp_write_protect) + puts(" temporary"); + putc('\n'); +} + +static int mmc_idle_cards(void) +{ + int ret; + + /* Reset and initialize all cards */ + ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); + if (ret) + return ret; + + /* Keep the bus idle for 74 clock cycles */ + return mmc_cmd(0, 0, NULL, INIT_CMD); +} + +static int sd_init_card(struct mmci *mmc, struct mmc_cid *cid, int verbose) +{ + unsigned long resp[4]; + int i, ret = 0; + + mmc_idle_cards(); + for (i = 0; i < 100; i++) { + ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_OP_COND, + resp, R3 | NID); + if (ret || (resp[0] & 0x80000000)) + break; + ret = -ETIMEDOUT; + } + + if (ret) + return ret; + + ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID); + if (ret) + return ret; + sd_parse_cid(cid, resp); + if (verbose) + mmc_dump_cid(cid); + + /* Get RCA of the card that responded */ + ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); + if (ret) + return ret; + + mmc->rca = resp[0] >> 16; + if (verbose) + printf("SD Card detected (RCA %u)\n", mmc->rca); + return 0; +} + +static int mmc_init_card(struct mmci *mmc, struct mmc_cid *cid, int verbose) +{ + unsigned long resp[4]; + int i, ret = 0; + + mmc_idle_cards(); + for (i = 0; i < 100; i++) { + ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_OP_COND, resp, + R3 | NID | OPEN_DRAIN); + if (ret || (resp[0] & 0x80000000)) + break; + ret = -ETIMEDOUT; + } + + if (ret) + return ret; + + /* Get CID of all cards. FIXME: Support more than one card */ + ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN); + if (ret) + return ret; + mmc_parse_cid(cid, resp); + if (verbose) + mmc_dump_cid(cid); + + /* Set Relative Address of the card that responded */ + ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc->rca << 16, resp, + R1 | NCR | OPEN_DRAIN); + return ret; +} + +int mmc_init(int verbose) +{ + struct mmc_cid cid; + struct mmc_csd csd; + int ret; + + if (!mmci.dev) { + mmci.dev = get_device(DEVICE_MMCI); + mmci.regs = mmci.dev->regs; + } + + /* Initialize controller */ + mmci_writel(&mmci, MCI_CR, MMCI_BIT(MCI_CR_SWRST)); + mmci_writel(&mmci, MCI_CR, MMCI_BIT(MCI_CR_MCIEN)); + mmci_writel(&mmci, MCI_DTOR, 0x5f); + mmci_writel(&mmci, MCI_IDR, ~0UL); + mci_set_mode(CFG_MMC_CLK_OD, CFG_MMC_BLKLEN); + + ret = sd_init_card(&mmci, &cid, verbose); + if (ret) { + mmci.rca = MMC_DEFAULT_RCA; + ret = mmc_init_card(&mmci, &cid, verbose); + } + if (ret) + return ret; + + /* Get CSD from the card */ + ret = mmc_cmd(MMC_CMD_SEND_CSD, mmci.rca << 16, &csd, R2 | NCR); + if (ret) + return ret; + if (verbose) + mmc_dump_csd(&csd); + + /* Initialize the blockdev structure */ + sprintf(mmci.blkdev.vendor, + "Man %02x%04x Snr %08x", + cid.mid, cid.oid, cid.psn); + strncpy(mmci.blkdev.product, cid.pnm, sizeof(mmci.blkdev.product)); + sprintf(mmci.blkdev.revision, + "%x %x", cid.prv >> 4, cid.prv & 0x0f); + mmci.blkdev.dev = 0; + mmci.blkdev.blksz = 1 << csd.read_bl_len; + mmci.blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2)); + + mci_set_mode(CFG_MMC_CLK_PP, mmci.blkdev.blksz); + +#if 0 + if (fat_register_device(&mmci.blkdev, 1)) + printf("Could not register MMC fat device\n"); +#else + init_part(&mmci.blkdev); +#endif + + return 0; +} + +int mmc_read(ulong src, uchar *dst, int size) +{ + return -ENOSYS; +} + +int mmc_write(uchar *src, ulong dst, int size) +{ + return -ENOSYS; +} + +int mmc2info(ulong addr) +{ + return 0; +} + +#endif /* CONFIG_MMC */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/mmci.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/mmci.h --- u-boot-1.1.4/cpu/at32ap7xxx/mmci.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/mmci.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PERIPH_MMCI_H__ +#define __ASM_AVR32_PERIPH_MMCI_H__ + +#define MMCI_MCI_ARGR 0x00000010 +# define MMCI_MCI_ARGR_ARG_OFFSET 0 +# define MMCI_MCI_ARGR_ARG_SIZE 32 +#define MMCI_MCI_CMDR 0x00000014 +# define MMCI_MCI_CMDR_CMDNB_OFFSET 0 +# define MMCI_MCI_CMDR_CMDNB_SIZE 6 +# define MMCI_MCI_CMDR_MAXLAT_OFFSET 12 +# define MMCI_MCI_CMDR_MAXLAT_SIZE 1 +# define MMCI_MCI_CMDR_OPDCMD_OFFSET 11 +# define MMCI_MCI_CMDR_OPDCMD_SIZE 1 +# define MMCI_MCI_CMDR_RSPTYP_OFFSET 6 +# define MMCI_MCI_CMDR_RSPTYP_SIZE 2 +# define MMCI_MCI_CMDR_SPCMD_OFFSET 8 +# define MMCI_MCI_CMDR_SPCMD_SIZE 3 +# define MMCI_MCI_CMDR_TRCMD_OFFSET 16 +# define MMCI_MCI_CMDR_TRCMD_SIZE 2 +# define MMCI_MCI_CMDR_TRDIR_OFFSET 18 +# define MMCI_MCI_CMDR_TRDIR_SIZE 1 +# define MMCI_MCI_CMDR_TRTYP_OFFSET 19 +# define MMCI_MCI_CMDR_TRTYP_SIZE 2 +#define MMCI_MCI_CR 0x00000000 +# define MMCI_MCI_CR_MCIDIS_OFFSET 1 +# define MMCI_MCI_CR_MCIDIS_SIZE 1 +# define MMCI_MCI_CR_MCIEN_OFFSET 0 +# define MMCI_MCI_CR_MCIEN_SIZE 1 +# define MMCI_MCI_CR_PWSDIS_OFFSET 3 +# define MMCI_MCI_CR_PWSDIS_SIZE 1 +# define MMCI_MCI_CR_PWSEN_OFFSET 2 +# define MMCI_MCI_CR_PWSEN_SIZE 1 +# define MMCI_MCI_CR_SWRST_OFFSET 7 +# define MMCI_MCI_CR_SWRST_SIZE 1 +#define MMCI_MCI_DTOR 0x00000008 +# define MMCI_MCI_DTOR_DTOCYC_OFFSET 0 +# define MMCI_MCI_DTOR_DTOCYC_SIZE 4 +# define MMCI_MCI_DTOR_DTOMUL_OFFSET 4 +# define MMCI_MCI_DTOR_DTOMUL_SIZE 3 +#define MMCI_MCI_IDR 0x00000048 +# define MMCI_MCI_IDR_BLKE_OFFSET 3 +# define MMCI_MCI_IDR_BLKE_SIZE 1 +# define MMCI_MCI_IDR_CMDRDY_OFFSET 0 +# define MMCI_MCI_IDR_CMDRDY_SIZE 1 +# define MMCI_MCI_IDR_DCRCE_OFFSET 21 +# define MMCI_MCI_IDR_DCRCE_SIZE 1 +# define MMCI_MCI_IDR_DTIP_OFFSET 4 +# define MMCI_MCI_IDR_DTIP_SIZE 1 +# define MMCI_MCI_IDR_DTOE_OFFSET 22 +# define MMCI_MCI_IDR_DTOE_SIZE 1 +# define MMCI_MCI_IDR_ENDRX_OFFSET 6 +# define MMCI_MCI_IDR_ENDRX_SIZE 1 +# define MMCI_MCI_IDR_ENDTX_OFFSET 7 +# define MMCI_MCI_IDR_ENDTX_SIZE 1 +# define MMCI_MCI_IDR_NOTBUSY_OFFSET 5 +# define MMCI_MCI_IDR_NOTBUSY_SIZE 1 +# define MMCI_MCI_IDR_OVRE_OFFSET 30 +# define MMCI_MCI_IDR_OVRE_SIZE 1 +# define MMCI_MCI_IDR_RCRCE_OFFSET 18 +# define MMCI_MCI_IDR_RCRCE_SIZE 1 +# define MMCI_MCI_IDR_RDIRE_OFFSET 17 +# define MMCI_MCI_IDR_RDIRE_SIZE 1 +# define MMCI_MCI_IDR_RENDE_OFFSET 19 +# define MMCI_MCI_IDR_RENDE_SIZE 1 +# define MMCI_MCI_IDR_RINDE_OFFSET 16 +# define MMCI_MCI_IDR_RINDE_SIZE 1 +# define MMCI_MCI_IDR_RTOE_OFFSET 20 +# define MMCI_MCI_IDR_RTOE_SIZE 1 +# define MMCI_MCI_IDR_RXBUFF_OFFSET 14 +# define MMCI_MCI_IDR_RXBUFF_SIZE 1 +# define MMCI_MCI_IDR_RXRDY_OFFSET 1 +# define MMCI_MCI_IDR_RXRDY_SIZE 1 +# define MMCI_MCI_IDR_TXBUFE_OFFSET 15 +# define MMCI_MCI_IDR_TXBUFE_SIZE 1 +# define MMCI_MCI_IDR_TXRDY_OFFSET 2 +# define MMCI_MCI_IDR_TXRDY_SIZE 1 +# define MMCI_MCI_IDR_UNRE_OFFSET 31 +# define MMCI_MCI_IDR_UNRE_SIZE 1 +#define MMCI_MCI_IER 0x00000044 +# define MMCI_MCI_IER_BLKE_OFFSET 3 +# define MMCI_MCI_IER_BLKE_SIZE 1 +# define MMCI_MCI_IER_CMDRDY_OFFSET 0 +# define MMCI_MCI_IER_CMDRDY_SIZE 1 +# define MMCI_MCI_IER_DCRCE_OFFSET 21 +# define MMCI_MCI_IER_DCRCE_SIZE 1 +# define MMCI_MCI_IER_DTIP_OFFSET 4 +# define MMCI_MCI_IER_DTIP_SIZE 1 +# define MMCI_MCI_IER_DTOE_OFFSET 22 +# define MMCI_MCI_IER_DTOE_SIZE 1 +# define MMCI_MCI_IER_ENDRX_OFFSET 6 +# define MMCI_MCI_IER_ENDRX_SIZE 1 +# define MMCI_MCI_IER_ENDTX_OFFSET 7 +# define MMCI_MCI_IER_ENDTX_SIZE 1 +# define MMCI_MCI_IER_NOTBUSY_OFFSET 5 +# define MMCI_MCI_IER_NOTBUSY_SIZE 1 +# define MMCI_MCI_IER_OVRE_OFFSET 30 +# define MMCI_MCI_IER_OVRE_SIZE 1 +# define MMCI_MCI_IER_RCRCE_OFFSET 18 +# define MMCI_MCI_IER_RCRCE_SIZE 1 +# define MMCI_MCI_IER_RDIRE_OFFSET 17 +# define MMCI_MCI_IER_RDIRE_SIZE 1 +# define MMCI_MCI_IER_RENDE_OFFSET 19 +# define MMCI_MCI_IER_RENDE_SIZE 1 +# define MMCI_MCI_IER_RINDE_OFFSET 16 +# define MMCI_MCI_IER_RINDE_SIZE 1 +# define MMCI_MCI_IER_RTOE_OFFSET 20 +# define MMCI_MCI_IER_RTOE_SIZE 1 +# define MMCI_MCI_IER_RXBUFF_OFFSET 14 +# define MMCI_MCI_IER_RXBUFF_SIZE 1 +# define MMCI_MCI_IER_RXRDY_OFFSET 1 +# define MMCI_MCI_IER_RXRDY_SIZE 1 +# define MMCI_MCI_IER_TXBUFE_OFFSET 15 +# define MMCI_MCI_IER_TXBUFE_SIZE 1 +# define MMCI_MCI_IER_TXRDY_OFFSET 2 +# define MMCI_MCI_IER_TXRDY_SIZE 1 +# define MMCI_MCI_IER_UNRE_OFFSET 31 +# define MMCI_MCI_IER_UNRE_SIZE 1 +#define MMCI_MCI_IMR 0x0000004c +# define MMCI_MCI_IMR_BLKE_OFFSET 3 +# define MMCI_MCI_IMR_BLKE_SIZE 1 +# define MMCI_MCI_IMR_CMDRDY_OFFSET 0 +# define MMCI_MCI_IMR_CMDRDY_SIZE 1 +# define MMCI_MCI_IMR_DCRCE_OFFSET 21 +# define MMCI_MCI_IMR_DCRCE_SIZE 1 +# define MMCI_MCI_IMR_DTIP_OFFSET 4 +# define MMCI_MCI_IMR_DTIP_SIZE 1 +# define MMCI_MCI_IMR_DTOE_OFFSET 22 +# define MMCI_MCI_IMR_DTOE_SIZE 1 +# define MMCI_MCI_IMR_ENDRX_OFFSET 6 +# define MMCI_MCI_IMR_ENDRX_SIZE 1 +# define MMCI_MCI_IMR_ENDTX_OFFSET 7 +# define MMCI_MCI_IMR_ENDTX_SIZE 1 +# define MMCI_MCI_IMR_NOTBUSY_OFFSET 5 +# define MMCI_MCI_IMR_NOTBUSY_SIZE 1 +# define MMCI_MCI_IMR_OVRE_OFFSET 30 +# define MMCI_MCI_IMR_OVRE_SIZE 1 +# define MMCI_MCI_IMR_RCRCE_OFFSET 18 +# define MMCI_MCI_IMR_RCRCE_SIZE 1 +# define MMCI_MCI_IMR_RDIRE_OFFSET 17 +# define MMCI_MCI_IMR_RDIRE_SIZE 1 +# define MMCI_MCI_IMR_RENDE_OFFSET 19 +# define MMCI_MCI_IMR_RENDE_SIZE 1 +# define MMCI_MCI_IMR_RINDE_OFFSET 16 +# define MMCI_MCI_IMR_RINDE_SIZE 1 +# define MMCI_MCI_IMR_RTOE_OFFSET 20 +# define MMCI_MCI_IMR_RTOE_SIZE 1 +# define MMCI_MCI_IMR_RXBUFF_OFFSET 14 +# define MMCI_MCI_IMR_RXBUFF_SIZE 1 +# define MMCI_MCI_IMR_RXRDY_OFFSET 1 +# define MMCI_MCI_IMR_RXRDY_SIZE 1 +# define MMCI_MCI_IMR_TXBUFE_OFFSET 15 +# define MMCI_MCI_IMR_TXBUFE_SIZE 1 +# define MMCI_MCI_IMR_TXRDY_OFFSET 2 +# define MMCI_MCI_IMR_TXRDY_SIZE 1 +# define MMCI_MCI_IMR_UNRE_OFFSET 31 +# define MMCI_MCI_IMR_UNRE_SIZE 1 +#define MMCI_MCI_MR 0x00000004 +# define MMCI_MCI_MR_BLKLEN_OFFSET 16 +# define MMCI_MCI_MR_BLKLEN_SIZE 16 +# define MMCI_MCI_MR_CLKDIV_OFFSET 0 +# define MMCI_MCI_MR_CLKDIV_SIZE 8 +# define MMCI_MCI_MR_PDCMODE_OFFSET 15 +# define MMCI_MCI_MR_PDCMODE_SIZE 1 +# define MMCI_MCI_MR_PDCPADV_OFFSET 14 +# define MMCI_MCI_MR_PDCPADV_SIZE 1 +# define MMCI_MCI_MR_PWSDIV_OFFSET 8 +# define MMCI_MCI_MR_PWSDIV_SIZE 3 +#define MMCI_MCI_RDR 0x00000030 +# define MMCI_MCI_RDR_DATA_OFFSET 0 +# define MMCI_MCI_RDR_DATA_SIZE 32 +#define MMCI_MCI_RSPR 0x00000020 +# define MMCI_MCI_RSPR_RSP_OFFSET 0 +# define MMCI_MCI_RSPR_RSP_SIZE 32 +#define MMCI_MCI_RSPR1 0x00000024 +# define MMCI_MCI_RSPR1_RSP_OFFSET 0 +# define MMCI_MCI_RSPR1_RSP_SIZE 32 +#define MMCI_MCI_RSPR2 0x00000028 +# define MMCI_MCI_RSPR2_RSP_OFFSET 0 +# define MMCI_MCI_RSPR2_RSP_SIZE 32 +#define MMCI_MCI_RSPR3 0x0000002c +# define MMCI_MCI_RSPR3_RSP_OFFSET 0 +# define MMCI_MCI_RSPR3_RSP_SIZE 32 +#define MMCI_MCI_SDCR 0x0000000c +# define MMCI_MCI_SDCR_SCDBUS_OFFSET 7 +# define MMCI_MCI_SDCR_SCDBUS_SIZE 1 +# define MMCI_MCI_SDCR_SCDSEL_OFFSET 0 +# define MMCI_MCI_SDCR_SCDSEL_SIZE 4 +#define MMCI_MCI_SR 0x00000040 +# define MMCI_MCI_SR_BLKE_OFFSET 3 +# define MMCI_MCI_SR_BLKE_SIZE 1 +# define MMCI_MCI_SR_CMDRDY_OFFSET 0 +# define MMCI_MCI_SR_CMDRDY_SIZE 1 +# define MMCI_MCI_SR_DCRCE_OFFSET 21 +# define MMCI_MCI_SR_DCRCE_SIZE 1 +# define MMCI_MCI_SR_DTIP_OFFSET 4 +# define MMCI_MCI_SR_DTIP_SIZE 1 +# define MMCI_MCI_SR_DTOE_OFFSET 22 +# define MMCI_MCI_SR_DTOE_SIZE 1 +# define MMCI_MCI_SR_ENDRX_OFFSET 6 +# define MMCI_MCI_SR_ENDRX_SIZE 1 +# define MMCI_MCI_SR_ENDTX_OFFSET 7 +# define MMCI_MCI_SR_ENDTX_SIZE 1 +# define MMCI_MCI_SR_NOTBUSY_OFFSET 5 +# define MMCI_MCI_SR_NOTBUSY_SIZE 1 +# define MMCI_MCI_SR_OVRE_OFFSET 30 +# define MMCI_MCI_SR_OVRE_SIZE 1 +# define MMCI_MCI_SR_RCRCE_OFFSET 18 +# define MMCI_MCI_SR_RCRCE_SIZE 1 +# define MMCI_MCI_SR_RDIRE_OFFSET 17 +# define MMCI_MCI_SR_RDIRE_SIZE 1 +# define MMCI_MCI_SR_RENDE_OFFSET 19 +# define MMCI_MCI_SR_RENDE_SIZE 1 +# define MMCI_MCI_SR_RINDE_OFFSET 16 +# define MMCI_MCI_SR_RINDE_SIZE 1 +# define MMCI_MCI_SR_RTOE_OFFSET 20 +# define MMCI_MCI_SR_RTOE_SIZE 1 +# define MMCI_MCI_SR_RXBUFF_OFFSET 14 +# define MMCI_MCI_SR_RXBUFF_SIZE 1 +# define MMCI_MCI_SR_RXRDY_OFFSET 1 +# define MMCI_MCI_SR_RXRDY_SIZE 1 +# define MMCI_MCI_SR_TXBUFE_OFFSET 15 +# define MMCI_MCI_SR_TXBUFE_SIZE 1 +# define MMCI_MCI_SR_TXRDY_OFFSET 2 +# define MMCI_MCI_SR_TXRDY_SIZE 1 +# define MMCI_MCI_SR_UNRE_OFFSET 31 +# define MMCI_MCI_SR_UNRE_SIZE 1 +#define MMCI_MCI_TDR 0x00000034 +# define MMCI_MCI_TDR_DATA_OFFSET 0 +# define MMCI_MCI_TDR_DATA_SIZE 32 +#define MMCI_MCI_VERSION 0x000000fc +# define MMCI_MCI_VERSION_MFN_OFFSET 16 +# define MMCI_MCI_VERSION_MFN_SIZE 3 +# define MMCI_MCI_VERSION_VERSION_OFFSET 0 +# define MMCI_MCI_VERSION_VERSION_SIZE 12 + +#define MMCI_BIT(name) (1 << MMCI_##name##_OFFSET) +#define MMCI_MKBF(name,value) (((value) & ((1 << MMCI_##name##_SIZE) - 1)) << MMCI_##name##_OFFSET) +#define MMCI_GETBF(name,value) (((value) >> MMCI_##name##_OFFSET) & ((1 << MMCI_##name##_SIZE) - 1)) +#define MMCI_INSBF(name,value,old) (((old) & ~(((1 << MMCI_##name##_SIZE) - 1) << MMCI_##name##_OFFSET)) | MMCI_MKBF(name, value)) + +#define mmci_readl(port,reg) readl((port)->regs + MMCI_##reg) +#define mmci_writel(port,reg,value) writel((value), (port)->regs + MMCI_##reg) + +#endif /* __ASM_AVR32_PERIPH_MMCI_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/pio2.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pio2.h --- u-boot-1.1.4/cpu/at32ap7xxx/pio2.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pio2.h 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,172 @@ +/* + * Register definitions for PIO2 + * + * Parallel Input/Output 2 + */ +#ifndef __ASM_AVR32_PIO2_H__ +#define __ASM_AVR32_PIO2_H__ + +/* PIO2 register offsets */ +#define PIO2_PER 0x0000 +#define PIO2_PDR 0x0004 +#define PIO2_PSR 0x0008 +#define PIO2_OER 0x0010 +#define PIO2_ODR 0x0014 +#define PIO2_OSR 0x0018 +#define PIO2_IFER 0x0020 +#define PIO2_IFDR 0x0024 +#define PIO2_ISFR 0x0028 +#define PIO2_SODR 0x0030 +#define PIO2_CODR 0x0034 +#define PIO2_ODSR 0x0038 +#define PIO2_PDSR 0x003c +#define PIO2_IER 0x0040 +#define PIO2_IDR 0x0044 +#define PIO2_IMR 0x0048 +#define PIO2_ISR 0x004c +#define PIO2_MDER 0x0050 +#define PIO2_MDDR 0x0054 +#define PIO2_MDSR 0x0058 +#define PIO2_PUDR 0x0060 +#define PIO2_PUER 0x0064 +#define PIO2_PUSR 0x0068 +#define PIO2_ASR 0x0070 +#define PIO2_BSR 0x0074 +#define PIO2_ABSR 0x0078 +#define PIO2_OWER 0x00a0 +#define PIO2_OWDR 0x00a4 +#define PIO2_OWSR 0x00a8 + +/* Bitfields in PER */ + +/* Bitfields in PDR */ + +/* Bitfields in PSR */ + +/* Bitfields in OER */ + +/* Bitfields in ODR */ + +/* Bitfields in OSR */ + +/* Bitfields in IFER */ + +/* Bitfields in IFDR */ + +/* Bitfields in ISFR */ + +/* Bitfields in SODR */ + +/* Bitfields in CODR */ + +/* Bitfields in ODSR */ + +/* Bitfields in PDSR */ + +/* Bitfields in IER */ + +/* Bitfields in IDR */ + +/* Bitfields in IMR */ + +/* Bitfields in ISR */ + +/* Bitfields in MDER */ + +/* Bitfields in MDDR */ + +/* Bitfields in MDSR */ + +/* Bitfields in PUDR */ + +/* Bitfields in PUER */ + +/* Bitfields in PUSR */ + +/* Bitfields in ASR */ + +/* Bitfields in BSR */ + +/* Bitfields in ABSR */ +#define PIO2_P0_OFFSET 0 +#define PIO2_P0_SIZE 1 +#define PIO2_P1_OFFSET 1 +#define PIO2_P1_SIZE 1 +#define PIO2_P2_OFFSET 2 +#define PIO2_P2_SIZE 1 +#define PIO2_P3_OFFSET 3 +#define PIO2_P3_SIZE 1 +#define PIO2_P4_OFFSET 4 +#define PIO2_P4_SIZE 1 +#define PIO2_P5_OFFSET 5 +#define PIO2_P5_SIZE 1 +#define PIO2_P6_OFFSET 6 +#define PIO2_P6_SIZE 1 +#define PIO2_P7_OFFSET 7 +#define PIO2_P7_SIZE 1 +#define PIO2_P8_OFFSET 8 +#define PIO2_P8_SIZE 1 +#define PIO2_P9_OFFSET 9 +#define PIO2_P9_SIZE 1 +#define PIO2_P10_OFFSET 10 +#define PIO2_P10_SIZE 1 +#define PIO2_P11_OFFSET 11 +#define PIO2_P11_SIZE 1 +#define PIO2_P12_OFFSET 12 +#define PIO2_P12_SIZE 1 +#define PIO2_P13_OFFSET 13 +#define PIO2_P13_SIZE 1 +#define PIO2_P14_OFFSET 14 +#define PIO2_P14_SIZE 1 +#define PIO2_P15_OFFSET 15 +#define PIO2_P15_SIZE 1 +#define PIO2_P16_OFFSET 16 +#define PIO2_P16_SIZE 1 +#define PIO2_P17_OFFSET 17 +#define PIO2_P17_SIZE 1 +#define PIO2_P18_OFFSET 18 +#define PIO2_P18_SIZE 1 +#define PIO2_P19_OFFSET 19 +#define PIO2_P19_SIZE 1 +#define PIO2_P20_OFFSET 20 +#define PIO2_P20_SIZE 1 +#define PIO2_P21_OFFSET 21 +#define PIO2_P21_SIZE 1 +#define PIO2_P22_OFFSET 22 +#define PIO2_P22_SIZE 1 +#define PIO2_P23_OFFSET 23 +#define PIO2_P23_SIZE 1 +#define PIO2_P24_OFFSET 24 +#define PIO2_P24_SIZE 1 +#define PIO2_P25_OFFSET 25 +#define PIO2_P25_SIZE 1 +#define PIO2_P26_OFFSET 26 +#define PIO2_P26_SIZE 1 +#define PIO2_P27_OFFSET 27 +#define PIO2_P27_SIZE 1 +#define PIO2_P28_OFFSET 28 +#define PIO2_P28_SIZE 1 +#define PIO2_P29_OFFSET 29 +#define PIO2_P29_SIZE 1 +#define PIO2_P30_OFFSET 30 +#define PIO2_P30_SIZE 1 +#define PIO2_P31_OFFSET 31 +#define PIO2_P31_SIZE 1 + +/* Bitfields in OWER */ + +/* Bitfields in OWDR */ + +/* Bitfields in OWSR */ + +/* Bit manipulation macros */ +#define PIO2_BIT(name) (1 << PIO2_##name##_OFFSET) +#define PIO2_BF(name,value) (((value) & ((1 << PIO2_##name##_SIZE) - 1)) << PIO2_##name##_OFFSET) +#define PIO2_BFEXT(name,value) (((value) >> PIO2_##name##_OFFSET) & ((1 << PIO2_##name##_SIZE) - 1)) +#define PIO2_BFINS(name,value,old) (((old) & ~(((1 << PIO2_##name##_SIZE) - 1) << PIO2_##name##_OFFSET)) | PIO2_BF(name,value)) + +/* Register access macros */ +#define pio2_readl(port,reg) readl((port)->regs + PIO2_##reg) +#define pio2_writel(port,reg,value) writel((value), (port)->regs + PIO2_##reg) + +#endif /* __ASM_AVR32_PIO2_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/pio.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pio.c --- u-boot-1.1.4/cpu/at32ap7xxx/pio.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pio.c 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include +#include + +#include "pio2.h" + +struct pio_state { + const struct device *dev; + u32 alloc_mask; +}; + +static struct pio_state pio_state[CFG_NR_PIOS]; + +int gpio_set_func(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins, enum gpio_func func) +{ + const struct device *gpio; + struct pio_state *state; + u32 mask; + + state = &pio_state[gpio_devid - DEVICE_PIOA]; + + gpio = get_device(gpio_devid); + if (!gpio) + return -EBUSY; + + state->dev = gpio; + mask = ((1 << nr_pins) - 1) << start; + + if (mask & state->alloc_mask) { + put_device(gpio); + return -EBUSY; + } + state->alloc_mask |= mask; + + switch (func) { + case GPIO_FUNC_GPIO: + /* TODO */ + return -EINVAL; + case GPIO_FUNC_A: + pio2_writel(gpio, ASR, mask); + pio2_writel(gpio, PDR, mask); + pio2_writel(gpio, PUDR, mask); + break; + case GPIO_FUNC_B: + pio2_writel(gpio, BSR, mask); + pio2_writel(gpio, PDR, mask); + pio2_writel(gpio, PUDR, mask); + break; + } + + return 0; +} + +void gpio_free(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins) +{ + const struct device *gpio; + struct pio_state *state; + u32 mask; + + state = &pio_state[gpio_devid - DEVICE_PIOA]; + gpio = state->dev; + mask = ((1 << nr_pins) - 1) << start; + + pio2_writel(gpio, ODR, mask); + pio2_writel(gpio, PER, mask); + + state->alloc_mask &= ~mask; + put_device(gpio); +} diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/pm.c u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pm.c --- u-boot-1.1.4/cpu/at32ap7xxx/pm.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/pm.c 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CFG_POWER_MANAGER +#include +#include + +#include +#include + +#include "sm.h" + +/* Sanity checks */ +#if (CFG_CLKDIV_CPU > CFG_CLKDIV_AHB) \ + || (CFG_CLKDIV_AHB > CFG_CLKDIV_APBA) \ + || (CFG_CLKDIV_AHB > CFG_CLKDIV_APBB) +# error Constraint fCPU >= fAHB >= fAPB{A,B} violated +#endif +#if (CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1) +# error Invalid PLL multiplier and/or divider +#endif + +struct clock_domain_state { + const struct device *bridge; + unsigned long freq; + u32 mask; +}; +static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS]; + +int pm_enable_clock(enum clock_domain_id id, unsigned int index) +{ + DECLARE_GLOBAL_DATA_PTR; + const struct clock_domain *ckd = &chip_clock[id]; + struct clock_domain_state *state = &ckd_state[id]; + + if (ckd->bridge != NO_DEVICE) { + state->bridge = get_device(ckd->bridge); + if (!state->bridge) + return -EBUSY; + } + + state->mask |= 1 << index; + if (gd->sm) + writel(state->mask, gd->sm->regs + ckd->reg); + + return 0; +} + +void pm_disable_clock(enum clock_domain_id id, unsigned int index) +{ + DECLARE_GLOBAL_DATA_PTR; + const struct clock_domain *ckd = &chip_clock[id]; + struct clock_domain_state *state = &ckd_state[id]; + + state->mask &= ~(1 << index); + if (gd->sm) + writel(state->mask, gd->sm->regs + ckd->reg); + + if (ckd->bridge) + put_device(state->bridge); +} + +unsigned long pm_get_clock_freq(enum clock_domain_id domain) +{ + return ckd_state[domain].freq; +} + +void pm_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + uint32_t cksel = 0; + unsigned long pll0_hz; + + /* Make sure we don't disable any device we're already using */ + get_device(DEVICE_HRAMC); + get_device(DEVICE_HEBI); + + /* Enable the PICO as well */ + ckd_state[CLOCK_CPU].mask |= 1; + + gd->sm = get_device(DEVICE_SM); + if (!gd->sm) + panic("Unable to claim system manager device!\n"); + + /* Disable any devices that haven't been explicitly claimed */ + sm_writel(gd->sm, PM_APBB_MASK, ckd_state[CLOCK_APBB].mask); + sm_writel(gd->sm, PM_APBA_MASK, ckd_state[CLOCK_APBA].mask); + sm_writel(gd->sm, PM_AHB_MASK, ckd_state[CLOCK_AHB].mask); + sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask); + + /* Initialize the PLL */ + pll0_hz = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL; + + sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) + | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) + | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) + | SM_BF(PLLOPT, CFG_PLL0_OPT) + | SM_BF(PLLOSC, 0) + | SM_BIT(PLLEN))); + + /* Wait for lock */ + while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ; + + /* Set up clocks for the CPU and all peripheral buses */ + if (CFG_CLKDIV_CPU) { + cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); + ckd_state[CLOCK_CPU].freq = pll0_hz / (1 << CFG_CLKDIV_CPU); + } else { + ckd_state[CLOCK_CPU].freq = pll0_hz; + } + if (CFG_CLKDIV_AHB) { + cksel |= SM_BIT(AHBDIV) | SM_BF(AHBSEL, CFG_CLKDIV_AHB - 1); + ckd_state[CLOCK_AHB].freq = pll0_hz / (1 << CFG_CLKDIV_AHB); + } else { + ckd_state[CLOCK_AHB].freq = pll0_hz; + } + if (CFG_CLKDIV_APBA) { + cksel |= SM_BIT(APBADIV) | SM_BF(APBASEL, CFG_CLKDIV_APBA - 1); + ckd_state[CLOCK_APBA].freq = pll0_hz / (1 << CFG_CLKDIV_APBA); + } else { + ckd_state[CLOCK_APBA].freq = pll0_hz; + } + if (CFG_CLKDIV_APBB) { + cksel |= SM_BIT(APBBDIV) | SM_BF(APBBSEL, CFG_CLKDIV_APBB - 1); + ckd_state[CLOCK_APBB].freq = pll0_hz / (1 << CFG_CLKDIV_APBB); + } else { + ckd_state[CLOCK_APBB].freq = pll0_hz; + } + sm_writel(gd->sm, PM_CKSEL, cksel); + + /* CFG_HZ currently depends on cpu_hz */ + gd->cpu_hz = ckd_state[CLOCK_CPU].freq; + + /* Use PLL0 as main clock */ + sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL)); +} + +#endif /* CFG_POWER_MANAGER */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/sm.h u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/sm.h --- u-boot-1.1.4/cpu/at32ap7xxx/sm.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/sm.h 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,240 @@ +/* + * Register definitions for SM + * + * System Manager + */ +#ifndef __ASM_AVR32_SM_H__ +#define __ASM_AVR32_SM_H__ + +/* SM register offsets */ +#define SM_PM_MCCTRL 0x0000 +#define SM_PM_CKSEL 0x0004 +#define SM_PM_CPU_MASK 0x0008 +#define SM_PM_AHB_MASK 0x000c +#define SM_PM_APBA_MASK 0x0010 +#define SM_PM_APBB_MASK 0x0014 +#define SM_PM_PLL0 0x0020 +#define SM_PM_PLL1 0x0024 +#define SM_PM_VCTRL 0x0030 +#define SM_PM_VMREF 0x0034 +#define SM_PM_VMV 0x0038 +#define SM_PM_IER 0x0040 +#define SM_PM_IDR 0x0044 +#define SM_PM_IMR 0x0048 +#define SM_PM_ISR 0x004c +#define SM_PM_ICR 0x0050 +#define SM_PM_GCCTRL 0x0060 +#define SM_RTC_CTRL 0x0080 +#define SM_RTC_VAL 0x0084 +#define SM_RTC_TOP 0x0088 +#define SM_RTC_IER 0x0090 +#define SM_RTC_IDR 0x0094 +#define SM_RTC_IMR 0x0098 +#define SM_RTC_ISR 0x009c +#define SM_RTC_ICR 0x00a0 +#define SM_WDT_CTRL 0x00b0 +#define SM_WDT_CLR 0x00b4 +#define SM_WDT_EXT 0x00b8 +#define SM_RC_RCAUSE 0x00c0 +#define SM_EIM_IER 0x0100 +#define SM_EIM_IDR 0x0104 +#define SM_EIM_IMR 0x0108 +#define SM_EIM_ISR 0x010c +#define SM_EIM_ICR 0x0110 +#define SM_EIM_MODE 0x0114 +#define SM_EIM_EDGE 0x0118 +#define SM_EIM_LEVEL 0x011c +#define SM_EIM_TEST 0x0120 +#define SM_EIM_NMIC 0x0124 + +/* Bitfields in PM_MCCTRL */ + +/* Bitfields in PM_CKSEL */ +#define SM_CPUSEL_OFFSET 0 +#define SM_CPUSEL_SIZE 3 +#define SM_CPUDIV_OFFSET 7 +#define SM_CPUDIV_SIZE 1 +#define SM_AHBSEL_OFFSET 8 +#define SM_AHBSEL_SIZE 3 +#define SM_AHBDIV_OFFSET 15 +#define SM_AHBDIV_SIZE 1 +#define SM_APBASEL_OFFSET 16 +#define SM_APBASEL_SIZE 3 +#define SM_APBADIV_OFFSET 23 +#define SM_APBADIV_SIZE 1 +#define SM_APBBSEL_OFFSET 24 +#define SM_APBBSEL_SIZE 3 +#define SM_APBBDIV_OFFSET 31 +#define SM_APBBDIV_SIZE 1 + +/* Bitfields in PM_CPU_MASK */ + +/* Bitfields in PM_AHB_MASK */ + +/* Bitfields in PM_APBA_MASK */ + +/* Bitfields in PM_APBB_MASK */ + +/* Bitfields in PM_PLL0 */ +#define SM_PLLEN_OFFSET 0 +#define SM_PLLEN_SIZE 1 +#define SM_PLLOSC_OFFSET 1 +#define SM_PLLOSC_SIZE 1 +#define SM_PLLOPT_OFFSET 2 +#define SM_PLLOPT_SIZE 3 +#define SM_PLLDIV_OFFSET 8 +#define SM_PLLDIV_SIZE 8 +#define SM_PLLMUL_OFFSET 16 +#define SM_PLLMUL_SIZE 8 +#define SM_PLLCOUNT_OFFSET 24 +#define SM_PLLCOUNT_SIZE 6 +#define SM_PLLTEST_OFFSET 31 +#define SM_PLLTEST_SIZE 1 + +/* Bitfields in PM_PLL1 */ + +/* Bitfields in PM_VCTRL */ +#define SM_VAUTO_OFFSET 0 +#define SM_VAUTO_SIZE 1 +#define SM_PM_VCTRL_VAL_OFFSET 8 +#define SM_PM_VCTRL_VAL_SIZE 7 + +/* Bitfields in PM_VMREF */ +#define SM_REFSEL_OFFSET 0 +#define SM_REFSEL_SIZE 4 + +/* Bitfields in PM_VMV */ +#define SM_PM_VMV_VAL_OFFSET 0 +#define SM_PM_VMV_VAL_SIZE 8 + +/* Bitfields in PM_IER */ + +/* Bitfields in PM_IDR */ + +/* Bitfields in PM_IMR */ + +/* Bitfields in PM_ISR */ + +/* Bitfields in PM_ICR */ +#define SM_LOCK0_OFFSET 0 +#define SM_LOCK0_SIZE 1 +#define SM_LOCK1_OFFSET 1 +#define SM_LOCK1_SIZE 1 +#define SM_WAKE_OFFSET 2 +#define SM_WAKE_SIZE 1 +#define SM_VOK_OFFSET 3 +#define SM_VOK_SIZE 1 +#define SM_VMRDY_OFFSET 4 +#define SM_VMRDY_SIZE 1 +#define SM_CKRDY_OFFSET 5 +#define SM_CKRDY_SIZE 1 + +/* Bitfields in PM_GCCTRL */ +#define SM_OSCSEL_OFFSET 0 +#define SM_OSCSEL_SIZE 1 +#define SM_PLLSEL_OFFSET 1 +#define SM_PLLSEL_SIZE 1 +#define SM_CEN_OFFSET 2 +#define SM_CEN_SIZE 1 +#define SM_CPC_OFFSET 3 +#define SM_CPC_SIZE 1 +#define SM_DIVEN_OFFSET 4 +#define SM_DIVEN_SIZE 1 +#define SM_DIV_OFFSET 8 +#define SM_DIV_SIZE 8 + +/* Bitfields in RTC_CTRL */ +#define SM_PCLR_OFFSET 1 +#define SM_PCLR_SIZE 1 +#define SM_TOPEN_OFFSET 2 +#define SM_TOPEN_SIZE 1 +#define SM_CLKEN_OFFSET 3 +#define SM_CLKEN_SIZE 1 +#define SM_PSEL_OFFSET 8 +#define SM_PSEL_SIZE 16 + +/* Bitfields in RTC_VAL */ +#define SM_RTC_VAL_VAL_OFFSET 0 +#define SM_RTC_VAL_VAL_SIZE 31 + +/* Bitfields in RTC_TOP */ +#define SM_RTC_TOP_VAL_OFFSET 0 +#define SM_RTC_TOP_VAL_SIZE 32 + +/* Bitfields in RTC_IER */ + +/* Bitfields in RTC_IDR */ + +/* Bitfields in RTC_IMR */ + +/* Bitfields in RTC_ISR */ + +/* Bitfields in RTC_ICR */ +#define SM_TOPI_OFFSET 0 +#define SM_TOPI_SIZE 1 + +/* Bitfields in WDT_CTRL */ +#define SM_KEY_OFFSET 24 +#define SM_KEY_SIZE 8 + +/* Bitfields in WDT_CLR */ + +/* Bitfields in WDT_EXT */ + +/* Bitfields in RC_RCAUSE */ +#define SM_POR_OFFSET 0 +#define SM_POR_SIZE 1 +#define SM_BOD_OFFSET 1 +#define SM_BOD_SIZE 1 +#define SM_EXT_OFFSET 2 +#define SM_EXT_SIZE 1 +#define SM_WDT_OFFSET 3 +#define SM_WDT_SIZE 1 +#define SM_NTAE_OFFSET 4 +#define SM_NTAE_SIZE 1 +#define SM_SERP_OFFSET 5 +#define SM_SERP_SIZE 1 + +/* Bitfields in EIM_IER */ + +/* Bitfields in EIM_IDR */ + +/* Bitfields in EIM_IMR */ + +/* Bitfields in EIM_ISR */ + +/* Bitfields in EIM_ICR */ + +/* Bitfields in EIM_MODE */ + +/* Bitfields in EIM_EDGE */ +#define SM_INT0_OFFSET 0 +#define SM_INT0_SIZE 1 +#define SM_INT1_OFFSET 1 +#define SM_INT1_SIZE 1 +#define SM_INT2_OFFSET 2 +#define SM_INT2_SIZE 1 +#define SM_INT3_OFFSET 3 +#define SM_INT3_SIZE 1 + +/* Bitfields in EIM_LEVEL */ + +/* Bitfields in EIM_TEST */ +#define SM_TESTEN_OFFSET 31 +#define SM_TESTEN_SIZE 1 + +/* Bitfields in EIM_NMIC */ +#define SM_EN_OFFSET 0 +#define SM_EN_SIZE 1 + +/* Bit manipulation macros */ +#define SM_BIT(name) (1 << SM_##name##_OFFSET) +#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET) +#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1)) +#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value)) + +/* Register access macros */ +#define sm_readl(port,reg) readl((port)->regs + SM_##reg) +#define sm_writel(port,reg,value) writel((value), (port)->regs + SM_##reg) + +#endif /* __ASM_AVR32_SM_H__ */ diff -Nur u-boot-1.1.4/cpu/at32ap7xxx/start.S u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/start.S --- u-boot-1.1.4/cpu/at32ap7xxx/start.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/cpu/at32ap7xxx/start.S 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include + +#ifndef PART_SPECIFIC_BOOTSTRAP +# define PART_SPECIFIC_BOOTSTRAP +#endif + +#define SYSREG_MMUCR_I_OFFSET 2 +#define SYSREG_MMUCR_S_OFFSET 4 + +#define SR_INIT (SYSREG_BIT(SR_GM) /* | SYSREG_BIT(SR_EM) */ | SYSREG_BIT(SR_M0)) +#define CPUCR_INIT (SYSREG_BIT(CPUCR_BI) | SYSREG_BIT(CPUCR_BE) \ + | SYSREG_BIT(CPUCR_FE) | SYSREG_BIT(CPUCR_RE) \ + | SYSREG_BIT(CPUCR_IBE) | SYSREG_BIT(CPUCR_IEE)) + + .text + .global _start +_start: + PART_SPECIFIC_BOOTSTRAP + + /* Reset the Status Register */ + mov r0, lo(SR_INIT) + orh r0, hi(SR_INIT) + mtsr SYSREG_SR, r0 + + /* Reset CPUCR and invalidate the BTB */ + mov r2, CPUCR_INIT + mtsr SYSREG_CPUCR, r2 + + /* Flush the caches */ + mov r1, 0 + cache r1[4], 8 + cache r1[0], 0 + sync 0 + + /* Reset the MMU to default settings */ + mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I) + mtsr SYSREG_MMUCR, r0 + + /* Internal RAM should not need any initialization. We might + have to initialize external RAM here if the part doesn't + have internal RAM (or we may use the data cache) */ + + /* Jump to cacheable segment */ + lddpc pc, 1f + + .align 2 +1: .long 2f + +2: lddpc sp, sp_init + + /* + * Relocate the data section and initialize .bss. Everything + * is guaranteed to be at least doubleword aligned by the + * linker script. + */ + lddpc r12, .Ldata_vma + lddpc r11, .Ldata_lma + lddpc r10, .Ldata_end + sub r10, r12 +4: ld.d r8, r11++ + sub r10, 8 + st.d r12++, r8 + brne 4b + + mov r8, 0 + mov r9, 0 + lddpc r10, .Lbss_end + sub r10, r12 +4: sub r10, 8 + st.d r12++, r8 + brne 4b + + /* Initialize the GOT pointer */ + lddpc r6, got_init +3: rsub r6, pc + ld.w pc, r6[start_u_boot@got] + + .align 2 + .type sp_init,@object +sp_init: + .long CFG_INIT_SP_ADDR +got_init: + .long 3b - _GLOBAL_OFFSET_TABLE_ +.Ldata_lma: + .long __data_lma +.Ldata_vma: + .long _data +.Ldata_end: + .long _edata +.Lbss_end: + .long _end diff -Nur u-boot-1.1.4/disk/part.c u-boot-1.1.4-avr32-20060621/disk/part.c --- u-boot-1.1.4/disk/part.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/disk/part.c 2006-06-21 11:58:26.000000000 +0200 @@ -126,6 +126,7 @@ #if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ (CONFIG_COMMANDS & CFG_CMD_USB) || \ + (CONFIG_COMMANDS & CFG_CMD_MMC) || \ defined(CONFIG_SYSTEMACE) ) #if defined(CONFIG_MAC_PARTITION) || \ diff -Nur u-boot-1.1.4/drivers/atmel_usart.c u-boot-1.1.4-avr32-20060621/drivers/atmel_usart.c --- u-boot-1.1.4/drivers/atmel_usart.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/drivers/atmel_usart.c 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include + +#ifdef CONFIG_USART3_SERIAL +#include +#include + +#include "atmel_usart.h" + +#define USART_MODE_NORMAL 0 +#define USART_CLKS_MCK 0 +#define USART_CHRL_8BITS 3 +#define USART_PAR_NONE 4 +#define USART_NBSTOP_1BIT 0 + +void serial_setbrg(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long divisor; + unsigned long usart_hz; + + /* + * Master Clock + * Baud Rate = -------------- + * 16 * CD + */ + usart_hz = pm_get_clock_freq(gd->console_uart->resource[0].u.clock.id); + divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate; + usart3_writel(gd->console_uart, US_BRGR, + USART3_MKBF(US_BRGR_CD, divisor)); +} + +int serial_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + usart3_writel(gd->console_uart, US_CR, + USART3_BIT(US_CR_RSTRX) | USART3_BIT(US_CR_RSTTX)); + + serial_setbrg(); + + usart3_writel(gd->console_uart, US_CR, + USART3_BIT(US_CR_RXEN) | USART3_BIT(US_CR_TXEN)); + usart3_writel(gd->console_uart, US_MR, + USART3_MKBF(US_MR_USART_MODE, USART_MODE_NORMAL) + | USART3_MKBF(US_MR_USCLKS, USART_CLKS_MCK) + | USART3_MKBF(US_MR_CHRL, USART_CHRL_8BITS) + | USART3_MKBF(US_MR_PAR, USART_PAR_NONE) + | USART3_MKBF(US_MR_NBSTOP, USART_NBSTOP_1BIT)); + + return 0; +} + +void serial_putc(char c) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (c == '\n') + serial_putc('\r'); + + while (!(usart3_readl(gd->console_uart, US_CSR) + & USART3_BIT(US_CSR_TXRDY))) ; + usart3_writel(gd->console_uart, US_THR, c); +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +int serial_getc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + while (!(usart3_readl(gd->console_uart, US_CSR) + & USART3_BIT(US_CSR_RXRDY))) ; + return usart3_readl(gd->console_uart, US_RHR); +} + +int serial_tstc(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + return (usart3_readl(gd->console_uart, US_CSR) + & USART3_BIT(US_CSR_RXRDY)) != 0; +} + +#endif /* CONFIG_USART3_SERIAL */ diff -Nur u-boot-1.1.4/drivers/atmel_usart.h u-boot-1.1.4-avr32-20060621/drivers/atmel_usart.h --- u-boot-1.1.4/drivers/atmel_usart.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/drivers/atmel_usart.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PERIPH_USART3_H__ +#define __ASM_AVR32_PERIPH_USART3_H__ + +#define USART3_US_BRGR 0x0020 +# define USART3_US_BRGR_CD_OFFSET 0 +# define USART3_US_BRGR_CD_SIZE 16 +#define USART3_US_CR 0x0000 +# define USART3_US_CR_COMM_RX_OFFSET 31 +# define USART3_US_CR_COMM_RX_SIZE 1 +# define USART3_US_CR_COMM_TX_OFFSET 30 +# define USART3_US_CR_COMM_TX_SIZE 1 +# define USART3_US_CR_DTRDIS_OFFSET 17 +# define USART3_US_CR_DTRDIS_SIZE 1 +# define USART3_US_CR_DTREN_OFFSET 16 +# define USART3_US_CR_DTREN_SIZE 1 +# define USART3_US_CR_RETTO_OFFSET 15 +# define USART3_US_CR_RETTO_SIZE 1 +# define USART3_US_CR_RSTIT_OFFSET 13 +# define USART3_US_CR_RSTIT_SIZE 1 +# define USART3_US_CR_RSTNACK_OFFSET 14 +# define USART3_US_CR_RSTNACK_SIZE 1 +# define USART3_US_CR_RSTRX_OFFSET 2 +# define USART3_US_CR_RSTRX_SIZE 1 +# define USART3_US_CR_RSTSTA_OFFSET 8 +# define USART3_US_CR_RSTSTA_SIZE 1 +# define USART3_US_CR_RSTTX_OFFSET 3 +# define USART3_US_CR_RSTTX_SIZE 1 +# define USART3_US_CR_RTSDIS_OFFSET 19 +# define USART3_US_CR_RTSDIS_SIZE 1 +# define USART3_US_CR_RTSEN_OFFSET 18 +# define USART3_US_CR_RTSEN_SIZE 1 +# define USART3_US_CR_RXDIS_OFFSET 5 +# define USART3_US_CR_RXDIS_SIZE 1 +# define USART3_US_CR_RXEN_OFFSET 4 +# define USART3_US_CR_RXEN_SIZE 1 +# define USART3_US_CR_SENDA_OFFSET 12 +# define USART3_US_CR_SENDA_SIZE 1 +# define USART3_US_CR_STPBRK_OFFSET 10 +# define USART3_US_CR_STPBRK_SIZE 1 +# define USART3_US_CR_STTBRK_OFFSET 9 +# define USART3_US_CR_STTBRK_SIZE 1 +# define USART3_US_CR_STTTO_OFFSET 11 +# define USART3_US_CR_STTTO_SIZE 1 +# define USART3_US_CR_TXDIS_OFFSET 7 +# define USART3_US_CR_TXDIS_SIZE 1 +# define USART3_US_CR_TXEN_OFFSET 6 +# define USART3_US_CR_TXEN_SIZE 1 +#define USART3_US_CSR 0x0014 +# define USART3_US_CSR_COMM_RX_OFFSET 31 +# define USART3_US_CSR_COMM_RX_SIZE 1 +# define USART3_US_CSR_COMM_TX_OFFSET 30 +# define USART3_US_CSR_COMM_TX_SIZE 1 +# define USART3_US_CSR_CTS_OFFSET 23 +# define USART3_US_CSR_CTS_SIZE 1 +# define USART3_US_CSR_CTSIC_OFFSET 19 +# define USART3_US_CSR_CTSIC_SIZE 1 +# define USART3_US_CSR_DCD_OFFSET 22 +# define USART3_US_CSR_DCD_SIZE 1 +# define USART3_US_CSR_DCDIC_OFFSET 18 +# define USART3_US_CSR_DCDIC_SIZE 1 +# define USART3_US_CSR_DSR_OFFSET 21 +# define USART3_US_CSR_DSR_SIZE 1 +# define USART3_US_CSR_DSRIC_OFFSET 17 +# define USART3_US_CSR_DSRIC_SIZE 1 +# define USART3_US_CSR_ENDRX_OFFSET 3 +# define USART3_US_CSR_ENDRX_SIZE 1 +# define USART3_US_CSR_ENDTX_OFFSET 4 +# define USART3_US_CSR_ENDTX_SIZE 1 +# define USART3_US_CSR_FRAME_OFFSET 6 +# define USART3_US_CSR_FRAME_SIZE 1 +# define USART3_US_CSR_ITERATION_OFFSET 10 +# define USART3_US_CSR_ITERATION_SIZE 1 +# define USART3_US_CSR_NACK_OFFSET 13 +# define USART3_US_CSR_NACK_SIZE 1 +# define USART3_US_CSR_OVRE_OFFSET 5 +# define USART3_US_CSR_OVRE_SIZE 1 +# define USART3_US_CSR_PARE_OFFSET 7 +# define USART3_US_CSR_PARE_SIZE 1 +# define USART3_US_CSR_RI_OFFSET 20 +# define USART3_US_CSR_RI_SIZE 1 +# define USART3_US_CSR_RIIC_OFFSET 16 +# define USART3_US_CSR_RIIC_SIZE 1 +# define USART3_US_CSR_RXBRK_OFFSET 2 +# define USART3_US_CSR_RXBRK_SIZE 1 +# define USART3_US_CSR_RXBUFF_OFFSET 12 +# define USART3_US_CSR_RXBUFF_SIZE 1 +# define USART3_US_CSR_RXRDY_OFFSET 0 +# define USART3_US_CSR_RXRDY_SIZE 1 +# define USART3_US_CSR_TIMEOUT_OFFSET 8 +# define USART3_US_CSR_TIMEOUT_SIZE 1 +# define USART3_US_CSR_TXBUFE_OFFSET 11 +# define USART3_US_CSR_TXBUFE_SIZE 1 +# define USART3_US_CSR_TXEMPTY_OFFSET 9 +# define USART3_US_CSR_TXEMPTY_SIZE 1 +# define USART3_US_CSR_TXRDY_OFFSET 1 +# define USART3_US_CSR_TXRDY_SIZE 1 +#define USART3_US_FIDI 0x0040 +# define USART3_US_FIDI_FI_DI_RATIO_OFFSET 0 +# define USART3_US_FIDI_FI_DI_RATIO_SIZE 11 +#define USART3_US_IDR 0x000C +# define USART3_US_IDR_COMM_RX_OFFSET 31 +# define USART3_US_IDR_COMM_RX_SIZE 1 +# define USART3_US_IDR_COMM_TX_OFFSET 30 +# define USART3_US_IDR_COMM_TX_SIZE 1 +# define USART3_US_IDR_CTSIC_OFFSET 19 +# define USART3_US_IDR_CTSIC_SIZE 1 +# define USART3_US_IDR_DCDIC_OFFSET 18 +# define USART3_US_IDR_DCDIC_SIZE 1 +# define USART3_US_IDR_DSRIC_OFFSET 17 +# define USART3_US_IDR_DSRIC_SIZE 1 +# define USART3_US_IDR_ENDRX_OFFSET 3 +# define USART3_US_IDR_ENDRX_SIZE 1 +# define USART3_US_IDR_ENDTX_OFFSET 4 +# define USART3_US_IDR_ENDTX_SIZE 1 +# define USART3_US_IDR_FRAME_OFFSET 6 +# define USART3_US_IDR_FRAME_SIZE 1 +# define USART3_US_IDR_ITERATION_OFFSET 10 +# define USART3_US_IDR_ITERATION_SIZE 1 +# define USART3_US_IDR_NACK_OFFSET 13 +# define USART3_US_IDR_NACK_SIZE 1 +# define USART3_US_IDR_OVRE_OFFSET 5 +# define USART3_US_IDR_OVRE_SIZE 1 +# define USART3_US_IDR_PARE_OFFSET 7 +# define USART3_US_IDR_PARE_SIZE 1 +# define USART3_US_IDR_RIIC_OFFSET 16 +# define USART3_US_IDR_RIIC_SIZE 1 +# define USART3_US_IDR_RXBRK_OFFSET 2 +# define USART3_US_IDR_RXBRK_SIZE 1 +# define USART3_US_IDR_RXBUFF_OFFSET 12 +# define USART3_US_IDR_RXBUFF_SIZE 1 +# define USART3_US_IDR_RXRDY_OFFSET 0 +# define USART3_US_IDR_RXRDY_SIZE 1 +# define USART3_US_IDR_TIMEOUT_OFFSET 8 +# define USART3_US_IDR_TIMEOUT_SIZE 1 +# define USART3_US_IDR_TXBUFE_OFFSET 11 +# define USART3_US_IDR_TXBUFE_SIZE 1 +# define USART3_US_IDR_TXEMPTY_OFFSET 9 +# define USART3_US_IDR_TXEMPTY_SIZE 1 +# define USART3_US_IDR_TXRDY_OFFSET 1 +# define USART3_US_IDR_TXRDY_SIZE 1 +#define USART3_US_IER 0x0008 +# define USART3_US_IER_COMM_RX_OFFSET 31 +# define USART3_US_IER_COMM_RX_SIZE 1 +# define USART3_US_IER_COMM_TX_OFFSET 30 +# define USART3_US_IER_COMM_TX_SIZE 1 +# define USART3_US_IER_CTSIC_OFFSET 19 +# define USART3_US_IER_CTSIC_SIZE 1 +# define USART3_US_IER_DCDIC_OFFSET 18 +# define USART3_US_IER_DCDIC_SIZE 1 +# define USART3_US_IER_DSRIC_OFFSET 17 +# define USART3_US_IER_DSRIC_SIZE 1 +# define USART3_US_IER_ENDRX_OFFSET 3 +# define USART3_US_IER_ENDRX_SIZE 1 +# define USART3_US_IER_ENDTX_OFFSET 4 +# define USART3_US_IER_ENDTX_SIZE 1 +# define USART3_US_IER_FRAME_OFFSET 6 +# define USART3_US_IER_FRAME_SIZE 1 +# define USART3_US_IER_ITERATION_OFFSET 10 +# define USART3_US_IER_ITERATION_SIZE 1 +# define USART3_US_IER_NACK_OFFSET 13 +# define USART3_US_IER_NACK_SIZE 1 +# define USART3_US_IER_OVRE_OFFSET 5 +# define USART3_US_IER_OVRE_SIZE 1 +# define USART3_US_IER_PARE_OFFSET 7 +# define USART3_US_IER_PARE_SIZE 1 +# define USART3_US_IER_RIIC_OFFSET 16 +# define USART3_US_IER_RIIC_SIZE 1 +# define USART3_US_IER_RXBRK_OFFSET 2 +# define USART3_US_IER_RXBRK_SIZE 1 +# define USART3_US_IER_RXBUFF_OFFSET 12 +# define USART3_US_IER_RXBUFF_SIZE 1 +# define USART3_US_IER_RXRDY_OFFSET 0 +# define USART3_US_IER_RXRDY_SIZE 1 +# define USART3_US_IER_TIMEOUT_OFFSET 8 +# define USART3_US_IER_TIMEOUT_SIZE 1 +# define USART3_US_IER_TXBUFE_OFFSET 11 +# define USART3_US_IER_TXBUFE_SIZE 1 +# define USART3_US_IER_TXEMPTY_OFFSET 9 +# define USART3_US_IER_TXEMPTY_SIZE 1 +# define USART3_US_IER_TXRDY_OFFSET 1 +# define USART3_US_IER_TXRDY_SIZE 1 +#define USART3_US_IF 0x004C +# define USART3_US_IF_IRDA_FILTER_OFFSET 0 +# define USART3_US_IF_IRDA_FILTER_SIZE 8 +#define USART3_US_IMR 0x0010 +# define USART3_US_IMR_COMM_RX_OFFSET 31 +# define USART3_US_IMR_COMM_RX_SIZE 1 +# define USART3_US_IMR_COMM_TX_OFFSET 30 +# define USART3_US_IMR_COMM_TX_SIZE 1 +# define USART3_US_IMR_CTSIC_OFFSET 19 +# define USART3_US_IMR_CTSIC_SIZE 1 +# define USART3_US_IMR_DCDIC_OFFSET 18 +# define USART3_US_IMR_DCDIC_SIZE 1 +# define USART3_US_IMR_DSRIC_OFFSET 17 +# define USART3_US_IMR_DSRIC_SIZE 1 +# define USART3_US_IMR_ENDRX_OFFSET 3 +# define USART3_US_IMR_ENDRX_SIZE 1 +# define USART3_US_IMR_ENDTX_OFFSET 4 +# define USART3_US_IMR_ENDTX_SIZE 1 +# define USART3_US_IMR_FRAME_OFFSET 6 +# define USART3_US_IMR_FRAME_SIZE 1 +# define USART3_US_IMR_ITERATION_OFFSET 10 +# define USART3_US_IMR_ITERATION_SIZE 1 +# define USART3_US_IMR_NACK_OFFSET 13 +# define USART3_US_IMR_NACK_SIZE 1 +# define USART3_US_IMR_OVRE_OFFSET 5 +# define USART3_US_IMR_OVRE_SIZE 1 +# define USART3_US_IMR_PARE_OFFSET 7 +# define USART3_US_IMR_PARE_SIZE 1 +# define USART3_US_IMR_RIIC_OFFSET 16 +# define USART3_US_IMR_RIIC_SIZE 1 +# define USART3_US_IMR_RXBRK_OFFSET 2 +# define USART3_US_IMR_RXBRK_SIZE 1 +# define USART3_US_IMR_RXBUFF_OFFSET 12 +# define USART3_US_IMR_RXBUFF_SIZE 1 +# define USART3_US_IMR_RXRDY_OFFSET 0 +# define USART3_US_IMR_RXRDY_SIZE 1 +# define USART3_US_IMR_TIMEOUT_OFFSET 8 +# define USART3_US_IMR_TIMEOUT_SIZE 1 +# define USART3_US_IMR_TXBUFE_OFFSET 11 +# define USART3_US_IMR_TXBUFE_SIZE 1 +# define USART3_US_IMR_TXEMPTY_OFFSET 9 +# define USART3_US_IMR_TXEMPTY_SIZE 1 +# define USART3_US_IMR_TXRDY_OFFSET 1 +# define USART3_US_IMR_TXRDY_SIZE 1 +#define USART3_US_MR 0x0004 +# define USART3_US_MR_CHMODE_OFFSET 14 +# define USART3_US_MR_CHMODE_SIZE 2 +# define USART3_US_MR_CHRL_OFFSET 6 +# define USART3_US_MR_CHRL_SIZE 2 +# define USART3_US_MR_CLKO_OFFSET 18 +# define USART3_US_MR_CLKO_SIZE 1 +# define USART3_US_MR_DSNACK_OFFSET 21 +# define USART3_US_MR_DSNACK_SIZE 1 +# define USART3_US_MR_FILTER_OFFSET 28 +# define USART3_US_MR_FILTER_SIZE 1 +# define USART3_US_MR_INACK_OFFSET 20 +# define USART3_US_MR_INACK_SIZE 1 +# define USART3_US_MR_MAX_ITERATION_OFFSET 24 +# define USART3_US_MR_MAX_ITERATION_SIZE 3 +# define USART3_US_MR_MODE9_OFFSET 17 +# define USART3_US_MR_MODE9_SIZE 1 +# define USART3_US_MR_MSBF_OFFSET 16 +# define USART3_US_MR_MSBF_SIZE 1 +# define USART3_US_MR_NBSTOP_OFFSET 12 +# define USART3_US_MR_NBSTOP_SIZE 2 +# define USART3_US_MR_OVER_OFFSET 19 +# define USART3_US_MR_OVER_SIZE 1 +# define USART3_US_MR_PAR_OFFSET 9 +# define USART3_US_MR_PAR_SIZE 3 +# define USART3_US_MR_SYNC_OFFSET 8 +# define USART3_US_MR_SYNC_SIZE 1 +# define USART3_US_MR_USART_MODE_OFFSET 0 +# define USART3_US_MR_USART_MODE_SIZE 4 +# define USART3_US_MR_USCLKS_OFFSET 4 +# define USART3_US_MR_USCLKS_SIZE 2 +#define USART3_US_NER 0x0044 +# define USART3_US_NER_NB_ERRORS_OFFSET 0 +# define USART3_US_NER_NB_ERRORS_SIZE 8 +#define USART3_US_RHR 0x0018 +# define USART3_US_RHR_RXCHR_OFFSET 0 +# define USART3_US_RHR_RXCHR_SIZE 9 +#define USART3_US_RTOR 0x0024 +# define USART3_US_RTOR_TO_OFFSET 0 +# define USART3_US_RTOR_TO_SIZE 16 +#define USART3_US_THR 0x001C +# define USART3_US_THR_TXCHR_OFFSET 0 +# define USART3_US_THR_TXCHR_SIZE 9 +#define USART3_US_TTGR 0x0028 +# define USART3_US_TTGR_TG_OFFSET 0 +# define USART3_US_TTGR_TG_SIZE 8 +#define USART3_US_XXR 0x00000048 +# define USART3_US_XXR_XON_XOFF_OFFSET 0 +# define USART3_US_XXR_XON_XOFF_SIZE 16 + +#define USART3_BIT(name) (1 << USART3_##name##_OFFSET) +#define USART3_MKBF(name,value) (((value) & ((1 << USART3_##name##_SIZE) - 1)) << USART3_##name##_OFFSET) +#define USART3_GETBF(name,value) (((value) >> USART3_##name##_OFFSET) & ((1 << USART3_##name##_SIZE) - 1)) +#define USART3_INSBF(name,value,old) (((old) & ~(((1 << USART3_##name##_SIZE) - 1) << USART3_##name##_OFFSET)) | USART3_MKBF(name, value)) + +#define usart3_readl(port,reg) readl((port)->regs + USART3_##reg) +#define usart3_writel(port,reg,value) writel((value), (port)->regs + USART3_##reg) + +#endif /* __ASM_AVR32_PERIPH_USART3_H__ */ diff -Nur u-boot-1.1.4/drivers/macb.c u-boot-1.1.4-avr32-20060621/drivers/macb.c --- u-boot-1.1.4/drivers/macb.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/drivers/macb.c 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,585 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include + +#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & (CFG_CMD_NET | CFG_CMD_MII)) + +/* + * The u-boot networking stack is a little weird. It seems like the + * networking core allocates receive buffers up front without any + * regard to the hardware that's supposed to actually receive those + * packets. + * + * The MACB receives packets into 128-byte receive buffers, so the + * buffers allocated by the core isn't very practical to use. We'll + * allocate our own, but we need one such buffer in case a packet + * wraps around the DMA ring so that we have to copy it. + * + * Therefore, define CFG_RX_ETH_BUFFER to 1 in the board-specific + * configuration header. This way, the core allocates one RX buffer + * and one TX buffer, each of which can hold a ethernet packet of + * maximum size. + * + * For some reason, the networking core unconditionally specifies a + * 32-byte packet "alignment" (which really should be called + * "padding"). MACB shouldn't need that, but we'll refrain from any + * core modifications here... + */ + +#include +#include + +#include +#include +#include +#include + +#include "macb.h" + +#define CFG_MACB_RX_BUFFER_SIZE 4096 +#define CFG_MACB_RX_RING_SIZE (CFG_MACB_RX_BUFFER_SIZE / 128) +#define CFG_MACB_TX_RING_SIZE 16 +#define CFG_MACB_TX_TIMEOUT 1000 +#define CFG_MACB_AUTONEG_TIMEOUT 5000000 + +struct macb_dma_desc { + u32 addr; + u32 ctrl; +}; + +#define RXADDR_USED 0x00000001 +#define RXADDR_WRAP 0x00000002 + +#define RXBUF_FRMLEN_MASK 0x00000fff +#define RXBUF_FRAME_START 0x00004000 +#define RXBUF_FRAME_END 0x00008000 +#define RXBUF_TYPEID_MATCH 0x00400000 +#define RXBUF_ADDR4_MATCH 0x00800000 +#define RXBUF_ADDR3_MATCH 0x01000000 +#define RXBUF_ADDR2_MATCH 0x02000000 +#define RXBUF_ADDR1_MATCH 0x04000000 +#define RXBUF_BROADCAST 0x80000000 + +#define TXBUF_FRMLEN_MASK 0x000007ff +#define TXBUF_FRAME_END 0x00008000 +#define TXBUF_NOCRC 0x00010000 +#define TXBUF_EXHAUSTED 0x08000000 +#define TXBUF_UNDERRUN 0x10000000 +#define TXBUF_MAXRETRY 0x20000000 +#define TXBUF_WRAP 0x40000000 +#define TXBUF_USED 0x80000000 + +struct macb_device { + void *regs; + + unsigned int rx_tail; + unsigned int tx_head; + unsigned int tx_tail; + + void *rx_buffer; + void *tx_buffer; + struct macb_dma_desc *rx_ring; + struct macb_dma_desc *tx_ring; + + unsigned long rx_buffer_dma; + unsigned long rx_ring_dma; + unsigned long tx_ring_dma; + + const struct device *dev; + struct eth_device netdev; + unsigned short phy_addr; +}; +#define to_macb(_nd) container_of(_nd, struct macb_device, netdev) + +static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + int iflag; + + local_irq_save(iflag); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + local_irq_restore(iflag); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(macb, MAN, frame); + + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + local_irq_save(iflag); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + local_irq_restore(iflag); +} + +static u16 macb_mdio_read(struct macb_device *macb, u8 reg) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + int iflag; + + local_irq_save(iflag); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + local_irq_restore(iflag); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(macb, MAN, frame); + + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + frame = macb_readl(macb, MAN); + + local_irq_save(iflag); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + local_irq_restore(iflag); + + return MACB_BFEXT(DATA, frame); +} + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +static int macb_send(struct eth_device *netdev, volatile void *packet, + int length) +{ + struct macb_device *macb = to_macb(netdev); + unsigned long paddr, ctrl; + unsigned int tx_head = macb->tx_head; + int i; + + paddr = dma_map_single(packet, length, DMA_TO_DEVICE); + + ctrl = length & TXBUF_FRMLEN_MASK; + ctrl |= TXBUF_FRAME_END; + if (tx_head == (CFG_MACB_TX_RING_SIZE - 1)) { + ctrl |= TXBUF_WRAP; + macb->tx_head = 0; + } else + macb->tx_head++; + + macb->tx_ring[tx_head].ctrl = ctrl; + macb->tx_ring[tx_head].addr = paddr; + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); + + /* + * I guess this is necessary because the networking core may + * re-use the transmit buffer as soon as we return... + */ + i = 0; + while (!(macb->tx_ring[tx_head].ctrl & TXBUF_USED)) { + if (i > CFG_MACB_TX_TIMEOUT) { + printf("%s: TX timeout\n", netdev->name); + break; + } + udelay(1); + i++; + } + + dma_unmap_single(packet, length, paddr); + + if (i <= CFG_MACB_TX_TIMEOUT) { + ctrl = macb->tx_ring[tx_head].ctrl; + if (ctrl & TXBUF_UNDERRUN) + printf("%s: TX underrun\n", netdev->name); + if (ctrl & TXBUF_EXHAUSTED) + printf("%s: TX buffers exhausted in mid frame\n", + netdev->name); + } + + /* No one cares anyway */ + return 0; +} + +static void reclaim_rx_buffers(struct macb_device *macb, + unsigned int new_tail) +{ + unsigned int i; + + i = macb->rx_tail; + while (i > new_tail) { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + if (i > CFG_MACB_RX_RING_SIZE) + i = 0; + } + + while (i < new_tail) { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + } + + macb->rx_tail = new_tail; +} + +static int macb_recv(struct eth_device *netdev) +{ + struct macb_device *macb = to_macb(netdev); + unsigned int rx_tail = macb->rx_tail; + void *buffer; + int length; + int wrapped = 0; + u32 status; + + for (;;) { + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) + return -1; + + status = macb->rx_ring[rx_tail].ctrl; + if (status & RXBUF_FRAME_START) { + if (rx_tail != macb->rx_tail) + reclaim_rx_buffers(macb, rx_tail); + wrapped = 0; + } + + if (status & RXBUF_FRAME_END) { + buffer = macb->rx_buffer + 128 * macb->rx_tail; + length = status & RXBUF_FRMLEN_MASK; + if (wrapped) { + unsigned int headlen, taillen; + + headlen = 128 * (CFG_MACB_RX_RING_SIZE + - macb->rx_tail); + taillen = length - headlen; + memcpy((void *)NetRxPackets[0], + buffer, headlen); + memcpy((void *)NetRxPackets[0] + headlen, + macb->rx_buffer, taillen); + buffer = (void *)NetRxPackets[0]; + } + + NetReceive(buffer, length); + if (++rx_tail >= CFG_MACB_RX_RING_SIZE) + rx_tail = 0; + reclaim_rx_buffers(macb, rx_tail); + } else { + if (++rx_tail >= CFG_MACB_RX_RING_SIZE) { + wrapped = 1; + rx_tail = 0; + } + } + } + + return 0; +} + +static int macb_phy_init(struct macb_device *macb) +{ + struct eth_device *netdev = &macb->netdev; + u32 ncfgr; + u16 phy_id, status, lpa; + int media, speed, duplex; + int i; + + /* Check if the PHY is up to snuff... */ + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id == 0xffff) { + printf("%s: No PHY present\n", netdev->name); + return 0; + } + + macb_mdio_write(macb, MII_ADVERTISE, + ADVERTISE_CSMA | ADVERTISE_ALL); + printf("%s: Starting autonegotiation...\n", netdev->name); + macb_mdio_write(macb, MII_BMCR, (BMCR_SPEED100 + | BMCR_ANENABLE + | BMCR_ANRESTART + | BMCR_FULLDPLX)); + +#if 0 + for (i = 0; i < 9; i++) + printf("mii%d: 0x%04x\n", i, macb_mdio_read(macb, i)); +#endif + + for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } + + if (status & BMSR_ANEGCOMPLETE) + printf("%s: Autonegotiation complete\n", netdev->name); + else + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + netdev->name, status); + + if (!(status & BMSR_LSTATUS)) { + printf("%s: link down\n", netdev->name); + return 0; + } else { + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & ADVERTISE_ALL); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + netdev->name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); + + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (speed) + ncfgr |= MACB_BIT(SPD); + if (duplex) + ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); + return 1; + } +} + +static int macb_init(struct eth_device *netdev, bd_t *bd) +{ + struct macb_device *macb = to_macb(netdev); + unsigned long paddr; + u32 hwaddr_bottom; + u16 hwaddr_top; + int i; + + /* + * macb_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ + + /* initialize DMA descriptors */ + paddr = macb->rx_buffer_dma; + for (i = 0; i < CFG_MACB_RX_RING_SIZE; i++) { + if (i == (CFG_MACB_RX_RING_SIZE - 1)) + paddr |= RXADDR_WRAP; + macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].ctrl = 0; + paddr += 128; + } + for (i = 0; i < CFG_MACB_TX_RING_SIZE; i++) { + macb->tx_ring[i].addr = 0; + if (i == (CFG_MACB_TX_RING_SIZE - 1)) + macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; + else + macb->tx_ring[i].ctrl = TXBUF_USED; + } + macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + + macb_writel(macb, RBQP, macb->rx_ring_dma); + macb_writel(macb, TBQP, macb->tx_ring_dma); + + /* set hardware address */ + hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))); + macb_writel(macb, SA1T, hwaddr_top); + + /* choose RMII or MII mode. This depends on the board */ +#ifdef CONFIG_RMII_PHY + macb_writel(macb, USRIO, 0); +#else + macb_writel(macb, USRIO, 1); +#endif + + if (!macb_phy_init(macb)) + return 0; + + /* Enable TX and RX */ + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); + + return 1; +} + +static void macb_halt(struct eth_device *netdev) +{ + struct macb_device *macb = to_macb(netdev); + u32 ncr, tsr; + int iflag; + + /* Halt the controller and wait for any ongoing transmission to end. */ + local_irq_save(iflag); + ncr = macb_readl(macb, NCR); + ncr |= MACB_BIT(THALT); + macb_writel(macb, NCR, ncr); + local_irq_restore(iflag); + + do { + tsr = macb_readl(macb, TSR); + } while (tsr & MACB_BIT(TGO)); + + /* Disable TX and RX, and clear statistics */ + macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); +} + +int macb_eth_initialize(int id, unsigned long base_addr, + unsigned int phy_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + struct macb_device *macb; + const struct device *dev; + struct eth_device *netdev; + unsigned long macb_hz; + u32 ncfgr; + + macb = malloc(sizeof(struct macb_device)); + if (!macb) { + printf("Error: Failed to allocate memory for MACB%d\n", id); + return -1; + } + memset(macb, 0, sizeof(struct macb_device)); + + dev = get_device(DEVICE_MACB0 + id); + macb->dev = dev; + netdev = &macb->netdev; + + macb->rx_buffer = dma_alloc_coherent(CFG_MACB_RX_BUFFER_SIZE, + &macb->rx_buffer_dma); + macb->rx_ring = dma_alloc_coherent(CFG_MACB_RX_RING_SIZE + * sizeof(struct macb_dma_desc), + &macb->rx_ring_dma); + macb->tx_ring = dma_alloc_coherent(CFG_MACB_TX_RING_SIZE + * sizeof(struct macb_dma_desc), + &macb->tx_ring_dma); + + macb->regs = dev->regs; + macb->phy_addr = phy_addr; + + sprintf(netdev->name, "macb%d", id); + netdev->init = macb_init; + netdev->halt = macb_halt; + netdev->send = macb_send; + netdev->recv = macb_recv; + + /* + * Do some basic initialization so that we at least can talk + * to the PHY + */ + macb_hz = pm_get_clock_freq(dev->resource[0].u.clock.id); + if (macb_hz < 200000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); + else if (macb_hz < 40000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); + else if (macb_hz < 80000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); + else + ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); + + macb_writel(macb, NCFGR, ncfgr); + + eth_register(netdev); + + return 0; +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */ + +#if (CONFIG_COMMANDS & CFG_CMD_MII) + +int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + int iflag; + + iflag = disable_interrupts(); + netctl = macb_readl(&macb, EMACB_NCR); + netctl |= MACB_BIT(MPE); + macb_writel(&macb, EMACB_NCR, netctl); + if (iflag) + enable_interrupts(); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(&macb, EMACB_MAN, frame); + + do { + netstat = macb_readl(&macb, EMACB_NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + frame = macb_readl(&macb, EMACB_MAN); + *value = MACB_BFEXT(DATA, frame); + + iflag = disable_interrupts(); + netctl = macb_readl(&macb, EMACB_NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(&macb, EMACB_NCR, netctl); + if (iflag) + enable_interrupts(); + + return 0; +} + +int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + int iflag; + + iflag = disable_interrupts(); + netctl = macb_readl(&macb, EMACB_NCR); + netctl |= MACB_BIT(MPE); + macb_writel(&macb, EMACB_NCR, netctl); + if (iflag) + enable_interrupts(); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(&macb, EMACB_MAN, frame); + + do { + netstat = macb_readl(&macb, EMACB_NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + iflag = disable_interrupts(); + netctl = macb_readl(&macb, EMACB_NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(&macb, EMACB_NCR, netctl); + if (iflag) + enable_interrupts(); + + return 0; +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#endif /* CONFIG_MACB */ diff -Nur u-boot-1.1.4/drivers/macb.h u-boot-1.1.4-avr32-20060621/drivers/macb.h --- u-boot-1.1.4/drivers/macb.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/drivers/macb.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,396 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PERIPH_MACB_H__ +#define __ASM_AVR32_PERIPH_MACB_H__ + +/* MACB register offsets */ +#define MACB_NCR 0x0000 +#define MACB_NCFGR 0x0004 +#define MACB_NSR 0x0008 +#define MACB_TSR 0x0014 +#define MACB_RBQP 0x0018 +#define MACB_TBQP 0x001c +#define MACB_RSR 0x0020 +#define MACB_ISR 0x0024 +#define MACB_IER 0x0028 +#define MACB_IDR 0x002c +#define MACB_IMR 0x0030 +#define MACB_MAN 0x0034 +#define MACB_PTR 0x0038 +#define MACB_PFR 0x003c +#define MACB_FTO 0x0040 +#define MACB_SCF 0x0044 +#define MACB_MCF 0x0048 +#define MACB_FRO 0x004c +#define MACB_FCSE 0x0050 +#define MACB_ALE 0x0054 +#define MACB_DTF 0x0058 +#define MACB_LCOL 0x005c +#define MACB_EXCOL 0x0060 +#define MACB_TUND 0x0064 +#define MACB_CSE 0x0068 +#define MACB_RRE 0x006c +#define MACB_ROVR 0x0070 +#define MACB_RSE 0x0074 +#define MACB_ELE 0x0078 +#define MACB_RJA 0x007c +#define MACB_USF 0x0080 +#define MACB_STE 0x0084 +#define MACB_RLE 0x0088 +#define MACB_TPF 0x008c +#define MACB_HRB 0x0090 +#define MACB_HRT 0x0094 +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c +#define MACB_SA2B 0x00a0 +#define MACB_SA2T 0x00a4 +#define MACB_SA3B 0x00a8 +#define MACB_SA3T 0x00ac +#define MACB_SA4B 0x00b0 +#define MACB_SA4T 0x00b4 +#define MACB_TID 0x00b8 +#define MACB_TPQ 0x00bc +#define MACB_USRIO 0x00c0 +#define MACB_WOL 0x00c4 +#define MACB_VERSION 0x00fc + +/* Bitfields in NCR */ +#define MACB_LB_OFFSET 0 +#define MACB_LB_SIZE 1 +#define MACB_LLB_OFFSET 1 +#define MACB_LLB_SIZE 1 +#define MACB_RE_OFFSET 2 +#define MACB_RE_SIZE 1 +#define MACB_TE_OFFSET 3 +#define MACB_TE_SIZE 1 +#define MACB_MPE_OFFSET 4 +#define MACB_MPE_SIZE 1 +#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_SIZE 1 +#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_SIZE 1 +#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_SIZE 1 +#define MACB_BP_OFFSET 8 +#define MACB_BP_SIZE 1 +#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_SIZE 1 +#define MACB_THALT_OFFSET 10 +#define MACB_THALT_SIZE 1 +#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_SIZE 1 +#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_SIZE 1 + +/* Bitfields in NCFGR */ +#define MACB_SPD_OFFSET 0 +#define MACB_SPD_SIZE 1 +#define MACB_FD_OFFSET 1 +#define MACB_FD_SIZE 1 +#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_SIZE 1 +#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_SIZE 1 +#define MACB_CAF_OFFSET 4 +#define MACB_CAF_SIZE 1 +#define MACB_NBC_OFFSET 5 +#define MACB_NBC_SIZE 1 +#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_SIZE 1 +#define MACB_UNI_OFFSET 7 +#define MACB_UNI_SIZE 1 +#define MACB_BIG_OFFSET 8 +#define MACB_BIG_SIZE 1 +#define MACB_EAE_OFFSET 9 +#define MACB_EAE_SIZE 1 +#define MACB_CLK_OFFSET 10 +#define MACB_CLK_SIZE 2 +#define MACB_RTY_OFFSET 12 +#define MACB_RTY_SIZE 1 +#define MACB_PAE_OFFSET 13 +#define MACB_PAE_SIZE 1 +#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_SIZE 2 +#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_SIZE 1 +#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_SIZE 1 +#define MACB_EFRHD_OFFSET 18 +#define MACB_EFRHD_SIZE 1 +#define MACB_IRXFCS_OFFSET 19 +#define MACB_IRXFCS_SIZE 1 + +/* Bitfields in NSR */ +#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_SIZE 1 +#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_SIZE 1 +#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_SIZE 1 + +/* Bitfields in TSR */ +#define MACB_UBR_OFFSET 0 +#define MACB_UBR_SIZE 1 +#define MACB_COL_OFFSET 1 +#define MACB_COL_SIZE 1 +#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_SIZE 1 +#define MACB_TGO_OFFSET 3 +#define MACB_TGO_SIZE 1 +#define MACB_BEX_OFFSET 4 +#define MACB_BEX_SIZE 1 +#define MACB_COMP_OFFSET 5 +#define MACB_COMP_SIZE 1 +#define MACB_UND_OFFSET 6 +#define MACB_UND_SIZE 1 + +/* Bitfields in RBQP */ + +/* Bitfields in TBQP */ + +/* Bitfields in RSR */ +#define MACB_BNA_OFFSET 0 +#define MACB_BNA_SIZE 1 +#define MACB_REC_OFFSET 1 +#define MACB_REC_SIZE 1 +#define MACB_OVR_OFFSET 2 +#define MACB_OVR_SIZE 1 + +/* Bitfields in ISR */ + +/* Bitfields in IER */ + +/* Bitfields in IDR */ +#define MACB_MFD_OFFSET 0 +#define MACB_MFD_SIZE 1 +#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_SIZE 1 +#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_SIZE 1 +#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_SIZE 1 +#define MACB_IDR_TUND_OFFSET 4 +#define MACB_IDR_TUND_SIZE 1 +#define MACB_IDR_RLE_OFFSET 5 +#define MACB_IDR_RLE_SIZE 1 +#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_SIZE 1 +#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_SIZE 1 +#define MACB_IDR_LINK_OFFSET 9 +#define MACB_IDR_LINK_SIZE 1 +#define MACB_IDR_ROVR_OFFSET 10 +#define MACB_IDR_ROVR_SIZE 1 +#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_SIZE 1 +#define MACB_PFR_OFFSET 12 +#define MACB_PFR_SIZE 1 +#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_SIZE 1 + +/* Bitfields in IMR */ + +/* Bitfields in MAN */ +#define MACB_DATA_OFFSET 0 +#define MACB_DATA_SIZE 16 +#define MACB_CODE_OFFSET 16 +#define MACB_CODE_SIZE 2 +#define MACB_REGA_OFFSET 18 +#define MACB_REGA_SIZE 5 +#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_SIZE 5 +#define MACB_RW_OFFSET 28 +#define MACB_RW_SIZE 2 +#define MACB_SOF_OFFSET 30 +#define MACB_SOF_SIZE 2 + +/* Bitfields in PTR */ +#define MACB_PTIME_OFFSET 0 +#define MACB_PTIME_SIZE 16 + +/* Bitfields in PFR */ +#define MACB_PFR_FROK_OFFSET 0 +#define MACB_PFR_FROK_SIZE 16 + +/* Bitfields in FTO */ +#define MACB_FTOK_OFFSET 0 +#define MACB_FTOK_SIZE 24 + +/* Bitfields in SCF */ +#define MACB_SCF_OFFSET 0 +#define MACB_SCF_SIZE 16 + +/* Bitfields in MCF */ +#define MACB_MCF_OFFSET 0 +#define MACB_MCF_SIZE 16 + +/* Bitfields in FRO */ +#define MACB_FRO_FROK_OFFSET 0 +#define MACB_FRO_FROK_SIZE 24 + +/* Bitfields in FCSE */ +#define MACB_FCSE_OFFSET 0 +#define MACB_FCSE_SIZE 8 + +/* Bitfields in ALE */ +#define MACB_ALE_OFFSET 0 +#define MACB_ALE_SIZE 8 + +/* Bitfields in DTF */ +#define MACB_DTF_OFFSET 0 +#define MACB_DTF_SIZE 16 + +/* Bitfields in LCOL */ +#define MACB_LCOL_OFFSET 0 +#define MACB_LCOL_SIZE 8 + +/* Bitfields in EXCOL */ +#define MACB_EXCOL_OFFSET 0 +#define MACB_EXCOL_SIZE 8 + +/* Bitfields in TUND */ +#define MACB_TUND_TUND_OFFSET 0 +#define MACB_TUND_TUND_SIZE 8 + +/* Bitfields in CSE */ +#define MACB_CSE_OFFSET 0 +#define MACB_CSE_SIZE 8 + +/* Bitfields in RRE */ +#define MACB_RRE_OFFSET 0 +#define MACB_RRE_SIZE 16 + +/* Bitfields in ROVR */ +#define MACB_ROVR_ROVR_OFFSET 0 +#define MACB_ROVR_ROVR_SIZE 8 + +/* Bitfields in RSE */ +#define MACB_RSE_OFFSET 0 +#define MACB_RSE_SIZE 8 + +/* Bitfields in ELE */ +#define MACB_EXL_OFFSET 0 +#define MACB_EXL_SIZE 8 + +/* Bitfields in RJA */ +#define MACB_RJB_OFFSET 0 +#define MACB_RJB_SIZE 8 + +/* Bitfields in USF */ +#define MACB_USF_OFFSET 0 +#define MACB_USF_SIZE 8 + +/* Bitfields in STE */ +#define MACB_SQER_OFFSET 0 +#define MACB_SQER_SIZE 8 + +/* Bitfields in RLE */ +#define MACB_RLFM_OFFSET 0 +#define MACB_RLFM_SIZE 8 + +/* Bitfields in TPF */ +#define MACB_TPF_TPF_OFFSET 0 +#define MACB_TPF_TPF_SIZE 16 + +/* Bitfields in HRB */ +#define MACB_HRB_ADDR_OFFSET 0 +#define MACB_HRB_ADDR_SIZE 32 + +/* Bitfields in HRT */ + +/* Bitfields in SA1B */ + +/* Bitfields in SA1T */ +#define MACB_SA1T_ADDR_OFFSET 0 +#define MACB_SA1T_ADDR_SIZE 16 + +/* Bitfields in SA2B */ +#define MACB_SA2B_ADDR_OFFSET 0 +#define MACB_SA2B_ADDR_SIZE 32 + +/* Bitfields in SA2T */ +#define MACB_SA2T_ADDR_OFFSET 0 +#define MACB_SA2T_ADDR_SIZE 16 + +/* Bitfields in SA3B */ +#define MACB_SA3B_ADDR_OFFSET 0 +#define MACB_SA3B_ADDR_SIZE 32 + +/* Bitfields in SA3T */ +#define MACB_SA3T_ADDR_OFFSET 0 +#define MACB_SA3T_ADDR_SIZE 16 + +/* Bitfields in SA4B */ +#define MACB_SA4B_ADDR_OFFSET 0 +#define MACB_SA4B_ADDR_SIZE 32 + +/* Bitfields in SA4T */ +#define MACB_SA4T_ADDR_OFFSET 0 +#define MACB_SA4T_ADDR_SIZE 16 + +/* Bitfields in TID */ +#define MACB_TID_OFFSET 0 +#define MACB_TID_SIZE 16 + +/* Bitfields in TPQ */ +#define MACB_TPQ_OFFSET 0 +#define MACB_TPQ_SIZE 16 + +/* Bitfields in USRIO */ +#define MACB_RMII_OFFSET 0 +#define MACB_RMII_SIZE 1 + +/* Bitfields in WOL */ +#define MACB_IP_OFFSET 0 +#define MACB_IP_SIZE 16 +#define MACB_MAG_OFFSET 16 +#define MACB_MAG_SIZE 1 +#define MACB_ARP_OFFSET 17 +#define MACB_ARP_SIZE 1 +#define MACB_SA1_OFFSET 18 +#define MACB_SA1_SIZE 1 +#define MACB_WOL_MTI_OFFSET 19 +#define MACB_WOL_MTI_SIZE 1 + +/* Bitfields in VERSION */ +#define MACB_REVISION_REFERENCE_OFFSET 0 +#define MACB_REVISION_REFERENCE_SIZE 16 +#define MACB_PART_REFERENCE_OFFSET 16 +#define MACB_PART_REFERENCE_SIZE 16 + +/* Constants for CLK */ +#define MACB_CLK_DIV8 0 +#define MACB_CLK_DIV16 1 +#define MACB_CLK_DIV32 2 +#define MACB_CLK_DIV64 3 + +/* Bit manipulation macros */ +#define MACB_BIT(name) (1 << MACB_##name##_OFFSET) +#define MACB_BF(name,value) (((value) & ((1 << MACB_##name##_SIZE) - 1)) << MACB_##name##_OFFSET) +#define MACB_BFEXT(name,value) (((value) >> MACB_##name##_OFFSET) & ((1 << MACB_##name##_SIZE) - 1)) +#define MACB_BFINS(name,value,old) (((old) & ~(((1 << MACB_##name##_SIZE) - 1) << MACB_##name##_OFFSET)) | MACB_BF(name,value)) + +/* Register access macros */ +#define macb_readl(port,reg) readl((port)->regs + MACB_##reg) +#define macb_writel(port,reg,value) writel((value), (port)->regs + MACB_##reg) + +#endif /* __ASM_AVR32_PERIPH_MACB_H__ */ diff -Nur u-boot-1.1.4/drivers/Makefile u-boot-1.1.4-avr32-20060621/drivers/Makefile --- u-boot-1.1.4/drivers/Makefile 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/drivers/Makefile 2006-06-21 11:58:25.000000000 +0200 @@ -27,12 +27,12 @@ LIB = libdrivers.a -OBJS = 3c589.o 5701rls.o ali512x.o \ +OBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ e1000.o eepro100.o \ i8042.o i82365.o inca-ip_sw.o keyboard.o \ - lan91c96.o \ + lan91c96.o macb.o \ natsemi.o ne2000.o netarm_eth.o netconsole.o \ ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \ omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \ diff -Nur u-boot-1.1.4/examples/Makefile u-boot-1.1.4-avr32-20060621/examples/Makefile --- u-boot-1.1.4/examples/Makefile 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/examples/Makefile 2006-06-21 11:58:22.000000000 +0200 @@ -53,6 +53,10 @@ LOAD_ADDR = 0x80F00000 endif +ifeq ($(ARCH),avr32) +LOAD_ADDR = 0x00000000 +endif + include $(TOPDIR)/config.mk SREC = hello_world.srec diff -Nur u-boot-1.1.4/examples/stubs.c u-boot-1.1.4-avr32-20060621/examples/stubs.c --- u-boot-1.1.4/examples/stubs.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/examples/stubs.c 2006-06-21 11:58:25.000000000 +0200 @@ -125,6 +125,19 @@ " lwi r5, r5, %1\n" \ " bra r5\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5"); +#elif defined(CONFIG_AVR32) +/* + * r6 holds the pointer to the global_data. r8 is call clobbered. + */ +#define EXPORT_FUNC(x) \ + asm volatile( \ + " .globl\t" #x "\n" \ + #x ":\n" \ + " ld.w r8, r6[%0]\n" \ + " ld.w pc, r8[%1]\n" \ + : \ + : "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \ + : "r8"); #else #error stubs definition missing for this architecture #endif @@ -137,9 +150,10 @@ * arguments can be used only inside the functions (gcc limitation) */ #if GCC_VERSION < 3004 -static +static void __attribute__((unused)) dummy(void) +#else +static void __attribute__((used)) dummy(void) #endif /* GCC_VERSION */ -void __attribute__((unused)) dummy(void) { #include <_exports.h> } diff -Nur u-boot-1.1.4/include/asm-avr32/addrspace.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/addrspace.h --- u-boot-1.1.4/include/asm-avr32/addrspace.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/addrspace.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ADDRSPACE_H +#define __ASM_AVR32_ADDRSPACE_H + +/* Memory segments when segmentation is enabled */ +#define P0SEG 0x00000000 +#define P1SEG 0x80000000 +#define P2SEG 0xa0000000 +#define P3SEG 0xc0000000 +#define P4SEG 0xe0000000 + +/* Returns the privileged segment base of a given address */ +#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) + +/* Returns the physical address of a PnSEG (n=1,2) address */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +/* + * Map an address to a certain privileged segment + */ +#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) +#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) +#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) +#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) + +#endif /* __ASM_AVR32_ADDRSPACE_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/arch-ap7000/hmatrix2.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/arch-ap7000/hmatrix2.h --- u-boot-1.1.4/include/asm-avr32/arch-ap7000/hmatrix2.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/arch-ap7000/hmatrix2.h 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,388 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_HMATRIX2_H__ +#define __ASM_AVR32_HMATRIX2_H__ + +/* HMATRIX2 register offsets */ +#define HMATRIX2_MCFG0 0x0000 +#define HMATRIX2_MCFG1 0x0004 +#define HMATRIX2_MCFG2 0x0008 +#define HMATRIX2_MCFG3 0x000c +#define HMATRIX2_MCFG4 0x0010 +#define HMATRIX2_MCFG5 0x0014 +#define HMATRIX2_MCFG6 0x0018 +#define HMATRIX2_MCFG7 0x001c +#define HMATRIX2_MCFG8 0x0020 +#define HMATRIX2_MCFG9 0x0024 +#define HMATRIX2_MCFG10 0x0028 +#define HMATRIX2_MCFG11 0x002c +#define HMATRIX2_MCFG12 0x0030 +#define HMATRIX2_MCFG13 0x0034 +#define HMATRIX2_MCFG14 0x0038 +#define HMATRIX2_MCFG15 0x003c +#define HMATRIX2_SCFG0 0x0040 +#define HMATRIX2_SCFG1 0x0044 +#define HMATRIX2_SCFG2 0x0048 +#define HMATRIX2_SCFG3 0x004c +#define HMATRIX2_SCFG4 0x0050 +#define HMATRIX2_SCFG5 0x0054 +#define HMATRIX2_SCFG6 0x0058 +#define HMATRIX2_SCFG7 0x005c +#define HMATRIX2_SCFG8 0x0060 +#define HMATRIX2_SCFG9 0x0064 +#define HMATRIX2_SCFG10 0x0068 +#define HMATRIX2_SCFG11 0x006c +#define HMATRIX2_SCFG12 0x0070 +#define HMATRIX2_SCFG13 0x0074 +#define HMATRIX2_SCFG14 0x0078 +#define HMATRIX2_SCFG15 0x007c +#define HMATRIX2_PRAS0 0x0080 +#define HMATRIX2_PRBS0 0x0084 +#define HMATRIX2_PRAS1 0x0088 +#define HMATRIX2_PRBS1 0x008c +#define HMATRIX2_PRAS2 0x0090 +#define HMATRIX2_PRBS2 0x0094 +#define HMATRIX2_PRAS3 0x0098 +#define HMATRIX2_PRBS3 0x009c +#define HMATRIX2_PRAS4 0x00a0 +#define HMATRIX2_PRBS4 0x00a4 +#define HMATRIX2_PRAS5 0x00a8 +#define HMATRIX2_PRBS5 0x00ac +#define HMATRIX2_PRAS6 0x00b0 +#define HMATRIX2_PRBS6 0x00b4 +#define HMATRIX2_PRAS7 0x00b8 +#define HMATRIX2_PRBS7 0x00bc +#define HMATRIX2_PRAS8 0x00c0 +#define HMATRIX2_PRBS8 0x00c4 +#define HMATRIX2_PRAS9 0x00c8 +#define HMATRIX2_PRBS9 0x00cc +#define HMATRIX2_PRAS10 0x00d0 +#define HMATRIX2_PRBS10 0x00d4 +#define HMATRIX2_PRAS11 0x00d8 +#define HMATRIX2_PRBS11 0x00dc +#define HMATRIX2_PRAS12 0x00e0 +#define HMATRIX2_PRBS12 0x00e4 +#define HMATRIX2_PRAS13 0x00e8 +#define HMATRIX2_PRBS13 0x00ec +#define HMATRIX2_PRAS14 0x00f0 +#define HMATRIX2_PRBS14 0x00f4 +#define HMATRIX2_PRAS15 0x00f8 +#define HMATRIX2_PRBS15 0x00fc +#define HMATRIX2_MRCR 0x0100 +#define HMATRIX2_SFR0 0x0110 +#define HMATRIX2_SFR1 0x0114 +#define HMATRIX2_SFR2 0x0118 +#define HMATRIX2_SFR3 0x011c +#define HMATRIX2_SFR4 0x0120 +#define HMATRIX2_SFR5 0x0124 +#define HMATRIX2_SFR6 0x0128 +#define HMATRIX2_SFR7 0x012c +#define HMATRIX2_SFR8 0x0130 +#define HMATRIX2_SFR9 0x0134 +#define HMATRIX2_SFR10 0x0138 +#define HMATRIX2_SFR11 0x013c +#define HMATRIX2_SFR12 0x0140 +#define HMATRIX2_SFR13 0x0144 +#define HMATRIX2_SFR14 0x0148 +#define HMATRIX2_SFR15 0x014c +#define HMATRIX2_VERSION 0x01fc + +/* Bitfields in MCFG0 */ +#define HMATRIX2_ULBT_OFFSET 0 +#define HMATRIX2_ULBT_SIZE 3 + +/* Bitfields in MCFG1 */ + +/* Bitfields in MCFG2 */ + +/* Bitfields in MCFG3 */ + +/* Bitfields in MCFG4 */ + +/* Bitfields in MCFG5 */ + +/* Bitfields in MCFG6 */ + +/* Bitfields in MCFG7 */ + +/* Bitfields in MCFG8 */ + +/* Bitfields in MCFG9 */ + +/* Bitfields in MCFG10 */ + +/* Bitfields in MCFG11 */ + +/* Bitfields in MCFG12 */ + +/* Bitfields in MCFG13 */ + +/* Bitfields in MCFG14 */ + +/* Bitfields in MCFG15 */ + +/* Bitfields in SCFG0 */ +#define HMATRIX2_SLOT_CYCLE_OFFSET 0 +#define HMATRIX2_SLOT_CYCLE_SIZE 8 +#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16 +#define HMATRIX2_DEFMSTR_TYPE_SIZE 2 +#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18 +#define HMATRIX2_FIXED_DEFMSTR_SIZE 4 +#define HMATRIX2_ARBT_OFFSET 24 +#define HMATRIX2_ARBT_SIZE 2 + +/* Bitfields in SCFG1 */ + +/* Bitfields in SCFG2 */ + +/* Bitfields in SCFG3 */ + +/* Bitfields in SCFG4 */ + +/* Bitfields in SCFG5 */ + +/* Bitfields in SCFG6 */ + +/* Bitfields in SCFG7 */ + +/* Bitfields in SCFG8 */ + +/* Bitfields in SCFG9 */ + +/* Bitfields in SCFG10 */ + +/* Bitfields in SCFG11 */ + +/* Bitfields in SCFG12 */ + +/* Bitfields in SCFG13 */ + +/* Bitfields in SCFG14 */ + +/* Bitfields in SCFG15 */ + +/* Bitfields in PRAS0 */ +#define HMATRIX2_M0PR_OFFSET 0 +#define HMATRIX2_M0PR_SIZE 4 +#define HMATRIX2_M1PR_OFFSET 4 +#define HMATRIX2_M1PR_SIZE 4 +#define HMATRIX2_M2PR_OFFSET 8 +#define HMATRIX2_M2PR_SIZE 4 +#define HMATRIX2_M3PR_OFFSET 12 +#define HMATRIX2_M3PR_SIZE 4 +#define HMATRIX2_M4PR_OFFSET 16 +#define HMATRIX2_M4PR_SIZE 4 +#define HMATRIX2_M5PR_OFFSET 20 +#define HMATRIX2_M5PR_SIZE 4 +#define HMATRIX2_M6PR_OFFSET 24 +#define HMATRIX2_M6PR_SIZE 4 +#define HMATRIX2_M7PR_OFFSET 28 +#define HMATRIX2_M7PR_SIZE 4 + +/* Bitfields in PRBS0 */ +#define HMATRIX2_M8PR_OFFSET 0 +#define HMATRIX2_M8PR_SIZE 4 +#define HMATRIX2_M9PR_OFFSET 4 +#define HMATRIX2_M9PR_SIZE 4 +#define HMATRIX2_M10PR_OFFSET 8 +#define HMATRIX2_M10PR_SIZE 4 +#define HMATRIX2_M11PR_OFFSET 12 +#define HMATRIX2_M11PR_SIZE 4 +#define HMATRIX2_M12PR_OFFSET 16 +#define HMATRIX2_M12PR_SIZE 4 +#define HMATRIX2_M13PR_OFFSET 20 +#define HMATRIX2_M13PR_SIZE 4 +#define HMATRIX2_M14PR_OFFSET 24 +#define HMATRIX2_M14PR_SIZE 4 +#define HMATRIX2_M15PR_OFFSET 28 +#define HMATRIX2_M15PR_SIZE 4 + +/* Bitfields in PRAS1 */ + +/* Bitfields in PRBS1 */ + +/* Bitfields in PRAS2 */ + +/* Bitfields in PRBS2 */ + +/* Bitfields in PRAS3 */ + +/* Bitfields in PRBS3 */ + +/* Bitfields in PRAS4 */ + +/* Bitfields in PRBS4 */ + +/* Bitfields in PRAS5 */ + +/* Bitfields in PRBS5 */ + +/* Bitfields in PRAS6 */ + +/* Bitfields in PRBS6 */ + +/* Bitfields in PRAS7 */ + +/* Bitfields in PRBS7 */ + +/* Bitfields in PRAS8 */ + +/* Bitfields in PRBS8 */ + +/* Bitfields in PRAS9 */ + +/* Bitfields in PRBS9 */ + +/* Bitfields in PRAS10 */ + +/* Bitfields in PRBS10 */ + +/* Bitfields in PRAS11 */ + +/* Bitfields in PRBS11 */ + +/* Bitfields in PRAS12 */ + +/* Bitfields in PRBS12 */ + +/* Bitfields in PRAS13 */ + +/* Bitfields in PRBS13 */ + +/* Bitfields in PRAS14 */ + +/* Bitfields in PRBS14 */ + +/* Bitfields in PRAS15 */ + +/* Bitfields in PRBS15 */ + +/* Bitfields in MRCR */ +#define HMATRIX2_RBC0_OFFSET 0 +#define HMATRIX2_RBC0_SIZE 1 +#define HMATRIX2_RBC1_OFFSET 1 +#define HMATRIX2_RBC1_SIZE 1 +#define HMATRIX2_RBC2_OFFSET 2 +#define HMATRIX2_RBC2_SIZE 1 +#define HMATRIX2_RBC3_OFFSET 3 +#define HMATRIX2_RBC3_SIZE 1 +#define HMATRIX2_RBC4_OFFSET 4 +#define HMATRIX2_RBC4_SIZE 1 +#define HMATRIX2_RBC5_OFFSET 5 +#define HMATRIX2_RBC5_SIZE 1 +#define HMATRIX2_RBC6_OFFSET 6 +#define HMATRIX2_RBC6_SIZE 1 +#define HMATRIX2_RBC7_OFFSET 7 +#define HMATRIX2_RBC7_SIZE 1 +#define HMATRIX2_RBC8_OFFSET 8 +#define HMATRIX2_RBC8_SIZE 1 +#define HMATRIX2_RBC9_OFFSET 9 +#define HMATRIX2_RBC9_SIZE 1 +#define HMATRIX2_RBC10_OFFSET 10 +#define HMATRIX2_RBC10_SIZE 1 +#define HMATRIX2_RBC11_OFFSET 11 +#define HMATRIX2_RBC11_SIZE 1 +#define HMATRIX2_RBC12_OFFSET 12 +#define HMATRIX2_RBC12_SIZE 1 +#define HMATRIX2_RBC13_OFFSET 13 +#define HMATRIX2_RBC13_SIZE 1 +#define HMATRIX2_RBC14_OFFSET 14 +#define HMATRIX2_RBC14_SIZE 1 +#define HMATRIX2_RBC15_OFFSET 15 +#define HMATRIX2_RBC15_SIZE 1 + +/* Bitfields in SFR0 */ +#define HMATRIX2_SFR_OFFSET 0 +#define HMATRIX2_SFR_SIZE 32 + +/* Bitfields in SFR1 */ + +/* Bitfields in SFR2 */ + +/* Bitfields in SFR3 */ + +/* Bitfields in SFR4 */ +#define HMATRIX2_CS1A_OFFSET 1 +#define HMATRIX2_CS1A_SIZE 1 +#define HMATRIX2_CS3A_OFFSET 3 +#define HMATRIX2_CS3A_SIZE 1 +#define HMATRIX2_CS4A_OFFSET 4 +#define HMATRIX2_CS4A_SIZE 1 +#define HMATRIX2_CS5A_OFFSET 5 +#define HMATRIX2_CS5A_SIZE 1 +#define HMATRIX2_DBPUC_OFFSET 8 +#define HMATRIX2_DBPUC_SIZE 1 + +/* Bitfields in SFR5 */ + +/* Bitfields in SFR6 */ + +/* Bitfields in SFR7 */ + +/* Bitfields in SFR8 */ + +/* Bitfields in SFR9 */ + +/* Bitfields in SFR10 */ + +/* Bitfields in SFR11 */ + +/* Bitfields in SFR12 */ + +/* Bitfields in SFR13 */ + +/* Bitfields in SFR14 */ + +/* Bitfields in SFR15 */ + +/* Bitfields in VERSION */ +#define HMATRIX2_VERSION_OFFSET 0 +#define HMATRIX2_VERSION_SIZE 12 +#define HMATRIX2_MFN_OFFSET 16 +#define HMATRIX2_MFN_SIZE 3 + +/* Constants for ULBT */ +#define HMATRIX2_ULBT_INFINITE 0 +#define HMATRIX2_ULBT_SINGLE 1 +#define HMATRIX2_ULBT_FOUR_BEAT 2 +#define HMATRIX2_ULBT_SIXTEEN_BEAT 4 + +/* Constants for DEFMSTR_TYPE */ +#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0 +#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1 +#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2 + +/* Constants for ARBT */ +#define HMATRIX2_ARBT_ROUND_ROBIN 0 +#define HMATRIX2_ARBT_FIXED_PRIORITY 1 + +/* Bit manipulation macros */ +#define HMATRIX2_BIT(name) (1 << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BF(name,value) (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) << HMATRIX2_##name##_OFFSET) +#define HMATRIX2_BFEXT(name,value) (((value) >> HMATRIX2_##name##_OFFSET) & ((1 << HMATRIX2_##name##_SIZE) - 1)) +#define HMATRIX2_BFINS(name,value,old) (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) << HMATRIX2_##name##_OFFSET)) | HMATRIX2_BF(name,value)) + +/* Register access macros */ +#define hmatrix2_readl(port,reg) readl((port)->regs + HMATRIX2_##reg) +#define hmatrix2_writel(port,reg,value) writel((value), (port)->regs + HMATRIX2_##reg) + +#endif /* __ASM_AVR32_HMATRIX2_H__ */ diff -Nur u-boot-1.1.4/include/asm-avr32/arch-ap7000/memory-map.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/arch-ap7000/memory-map.h --- u-boot-1.1.4/include/asm-avr32/arch-ap7000/memory-map.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/arch-ap7000/memory-map.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__ +#define __ASM_AVR32_PART_MEMORY_MAP_H__ + +#define AUDIOC_BASE 0xFFF02800 +#define DAC_BASE 0xFFF02000 +#define DMAC_BASE 0xFF200000 +#define ECC_BASE 0xFFF03C00 +#define HISI_BASE 0xFFF02C00 +#define HMATRIX_BASE 0xFFF00800 +#define HSDRAMC_BASE 0xFFF03800 +#define HSMC_BASE 0xFFF03400 +#define LCDC_BASE 0xFF000000 +#define MACB0_BASE 0xFFF01800 +#define MACB1_BASE 0xFFF01C00 +#define MMCI_BASE 0xFFF02400 +#define PIOA_BASE 0xFFE02800 +#define PIOB_BASE 0xFFE02C00 +#define PIOC_BASE 0xFFE03000 +#define PIOD_BASE 0xFFE03400 +#define PIOE_BASE 0xFFE03800 +#define PSIF_BASE 0xFFE03C00 +#define PWM_BASE 0xFFF01400 +#define SM_BASE 0xFFF00000 +#define INTC_BASE 0XFFF00400 +#define SPI0_BASE 0xFFE00000 +#define SPI1_BASE 0xFFE00400 +#define SSC0_BASE 0xFFE01C00 +#define SSC1_BASE 0xFFE02000 +#define SSC2_BASE 0xFFE02400 +#define TIMER0_BASE 0xFFF00C00 +#define TIMER1_BASE 0xFFF01000 +#define TWI_BASE 0xFFE00800 +#define USART0_BASE 0xFFE00C00 +#define USART1_BASE 0xFFE01000 +#define USART2_BASE 0xFFE01400 +#define USART3_BASE 0xFFE01800 +#define USB_FIFO 0xFF300000 +#define USB_BASE 0xFFF03000 + +#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */ diff -Nur u-boot-1.1.4/include/asm-avr32/arch-ap7000/mmc.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/arch-ap7000/mmc.h --- u-boot-1.1.4/include/asm-avr32/arch-ap7000/mmc.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/arch-ap7000/mmc.h 2006-06-21 11:58:24.000000000 +0200 @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_MMC_H +#define __ASM_AVR32_ARCH_MMC_H + +#include + +#endif /* __ASM_AVR32_ARCH_MMC_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/arch-ap7000/platform.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/arch-ap7000/platform.h --- u-boot-1.1.4/include/asm-avr32/arch-ap7000/platform.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/arch-ap7000/platform.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_AVR32_ARCH_PM_H +#define _ASM_AVR32_ARCH_PM_H + +#include + +enum clock_domain_id { + CLOCK_CPU, + CLOCK_AHB, + CLOCK_APBA, + CLOCK_APBB, + NR_CLOCK_DOMAINS, +}; + +enum resource_type { + RESOURCE_GPIO, + RESOURCE_CLOCK, +}; + +enum gpio_func { + GPIO_FUNC_GPIO, + GPIO_FUNC_A, + GPIO_FUNC_B, +}; + +enum device_id { + DEVICE_HEBI, + DEVICE_APBA_BRIDGE, + DEVICE_APBB_BRIDGE, + DEVICE_HRAMC, + /* GPIO controllers must be kept together */ + DEVICE_PIOA, + DEVICE_PIOB, + DEVICE_PIOC, + DEVICE_PIOD, + DEVICE_PIOE, + DEVICE_SM, + DEVICE_INTC, + DEVICE_HMATRIX, +#if defined(CFG_HPDC) + DEVICE_HPDC, +#endif +#if defined(CFG_MACB0) + DEVICE_MACB0, +#endif +#if defined(CFG_MACB1) + DEVICE_MACB1, +#endif +#if defined(CFG_LCDC) + DEVICE_LCDC, +#endif +#if defined(CFG_USART0) + DEVICE_USART0, +#endif +#if defined(CFG_USART1) + DEVICE_USART1, +#endif +#if defined(CFG_USART2) + DEVICE_USART2, +#endif +#if defined(CFG_USART3) + DEVICE_USART3, +#endif +#if defined(CFG_MMCI) + DEVICE_MMCI, +#endif +#if defined(CFG_DMAC) + DEVICE_DMAC, +#endif + NR_DEVICES, + NO_DEVICE = -1, +}; + +struct resource { + enum resource_type type; + union { + struct { + unsigned long base; + } iomem; + struct { + unsigned char nr_pins; + enum device_id gpio_dev; + enum gpio_func func; + unsigned short start; + } gpio; + struct { + enum clock_domain_id id; + unsigned char index; + } clock; + } u; +}; + +struct device { + void *regs; + unsigned int nr_resources; + const struct resource *resource; +}; + +struct clock_domain { + unsigned short reg; + enum clock_domain_id id; + enum device_id bridge; +}; + +extern const struct device chip_device[NR_DEVICES]; +extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS]; + +/** + * Set up PIO, clock management and I/O memory for a device. + */ +const struct device *get_device(enum device_id devid); +void put_device(const struct device *dev); + +int gpio_set_func(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins, enum gpio_func func); +void gpio_free(enum device_id gpio_devid, unsigned int start, + unsigned int nr_pins); + +int pm_enable_clock(enum clock_domain_id id, unsigned int index); +void pm_disable_clock(enum clock_domain_id id, unsigned int index); +unsigned long pm_get_clock_freq(enum clock_domain_id domain); + +void cpu_enable_sdram(void); + +#endif /* _ASM_AVR32_ARCH_PM_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/bitops.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/bitops.h --- u-boot-1.1.4/include/asm-avr32/bitops.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/bitops.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,308 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_BITOPS_H +#define __ASM_AVR32_BITOPS_H + +#ifdef __KERNEL__ +#include + +static __inline__ void set_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a |= mask; + local_irq_restore(flags); +} + +static __inline__ void __set_bit(int nr, volatile void *addr) +{ + int mask; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +/* + * clear_bit() doesn't provide any barrier for the compiler (?) + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +static __inline__ void clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a &= ~mask; + local_irq_restore(flags); +} + +static __inline__ void __clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a &= ~mask; +} + +static __inline__ void change_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a ^= mask; + local_irq_restore(flags); +} + +static __inline__ void __change_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a ^= mask; +} + +static __inline__ int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a |= mask; + local_irq_restore(flags); + + return retval; +} + +static __inline__ int __test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + + return retval; +} + +static __inline__ int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + local_irq_restore(flags); + + return retval; +} + +static __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + + return retval; +} + +static __inline__ int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a ^= mask; + local_irq_restore(flags); + + return retval; +} + +static __inline__ int __test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + + return retval; +} + +static __inline__ int test_bit(int nr, const volatile void * addr) +{ + return 1UL & (((const volatile unsigned int *)addr)[nr >> 5] >> (nr & 31)); +} + +/* Find First bit Set */ +static __inline__ unsigned long __ffs(unsigned long word) +{ + unsigned long result; + + __asm__("brev %1\n\t" + "clz %0,%1" + : "=r"(result), "=r"(word) + : "1"(word)); + return result; +} + +/* Find First Zero */ +static __inline__ unsigned long ffz(unsigned long word) +{ + return __ffs(~word); +} + +/* Find Last bit Set */ +static __inline__ unsigned long fls(unsigned long word) +{ + unsigned long result; + + __asm__("clz %0,%1" : "=r"(result) : "r"(word)); + return 32 - result; +} + +/* TODO: Review and optimize. This is entirely stolen from SH */ +static __inline__ int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *)addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32 - offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL << size; +found_middle: + return result + ffz(tmp); +} + +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + * + * The difference is that bit numbering starts at 1, and if no bit is set, + * the function returns 0. + */ +static __inline__ unsigned long ffs(unsigned long word) +{ + if(word == 0) + return 0; + return __ffs(word) + 1; +} + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +/* + * Every architecture must define this function. It's the fastest + * way of searching a 140-bit bitmap where the first 100 bits are + * unlikely to be set. It's guaranteed that at least one of the 140 + * bits is cleared. + */ +static inline int sched_find_first_bit(unsigned long *b) +{ + if (unlikely(b[0])) + return __ffs(b[0]); + if (unlikely(b[1])) + return __ffs(b[1]) + 32; + if (unlikely(b[2])) + return __ffs(b[2]) + 64; + if (b[3]) + return __ffs(b[3]) + 96; + return __ffs(b[4]) + 128; +} + +#endif /* __KERNEL__ */ + + +#endif /* __ASM_AVR32_BITOPS_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/byteorder.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/byteorder.h --- u-boot-1.1.4/include/asm-avr32/byteorder.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/byteorder.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_BYTEORDER_H +#define __ASM_AVR32_BYTEORDER_H + +#include +#include + +#ifdef __CHECKER__ +extern unsigned long __builtin_bswap_32(unsigned long x); +extern unsigned short __builtin_bswap_16(unsigned short x); +#endif + +#define __arch__swab32(x) __builtin_bswap_32(x) +#define __arch__swab16(x) __builtin_bswap_16(x) + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#include + +#endif /* __ASM_AVR32_BYTEORDER_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/cacheflush.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/cacheflush.h --- u-boot-1.1.4/include/asm-avr32/cacheflush.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/cacheflush.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_CACHEFLUSH_H +#define __ASM_AVR32_CACHEFLUSH_H + +/* + * Invalidate any cacheline containing virtual address vaddr without + * writing anything back to memory. + * + * Note that this function may corrupt unrelated data structures when + * applied on buffers that are not cacheline aligned in both ends. + */ +static inline void dcache_invalidate_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory"); +} + +/* + * Make sure any cacheline containing virtual address vaddr is written + * to memory. + */ +static inline void dcache_clean_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory"); +} + +/* + * Make sure any cacheline containing virtual address vaddr is written + * to memory and then invalidate it. + */ +static inline void dcache_flush_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory"); +} + +/* + * Invalidate any instruction cacheline containing virtual address + * vaddr. + */ +static inline void icache_invalidate_line(volatile void *vaddr) +{ + asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory"); +} + +/* + * Applies the above functions on all lines that are touched by the + * specified virtual address range. + */ +void dcache_invalidate_range(volatile void *start, size_t len); +void dcache_clean_range(volatile void *start, size_t len); +void dcache_flush_range(volatile void *start, size_t len); +void icache_invalidate_range(volatile void *start, size_t len); + +static inline void dcache_flush_unlocked(void) +{ + asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory"); +} + +/* + * Make sure any pending writes are completed before continuing. + */ +#define sync_write_buffer() asm volatile("sync 0" : : : "memory") + +#endif /* __ASM_AVR32_CACHEFLUSH_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/dbgregs.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/dbgregs.h --- u-boot-1.1.4/include/asm-avr32/dbgregs.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/dbgregs.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_DBGREGS_H__ +#define __ASM_AVR32_DBGREGS_H__ + +#define DBGREG_DID 0x00000000 +# define DBGREG_DID_RN_OFFSET 28 +# define DBGREG_DID_RN_SIZE 4 +# define DBGREG_DID_PN_OFFSET 12 +# define DBGREG_DID_PN_SIZE 16 +# define DBGREG_DID_MID_OFFSET 1 +# define DBGREG_DID_MID_SIZE 12 +#define DBGREG_DC 0x00000008 +# define DBGREG_DC_ABORT_OFFSET 31 +# define DBGREG_DC_ABORT_SIZE 1 +# define DBGREG_DC_RES_OFFSET 30 +# define DBGREG_DC_RES_SIZE 1 +# define DBGREG_DC_MM_OFFSET 29 +# define DBGREG_DC_MM_SIZE 1 +# define DBGREG_DC_ORP_OFFSET 28 +# define DBGREG_DC_ORP_SIZE 1 +# define DBGREG_DC_RID_OFFSET 27 +# define DBGREG_DC_RID_SIZE 1 +# define DBGREG_DC_TSR_OFFSET 26 +# define DBGREG_DC_TSR_SIZE 1 +# define DBGREG_DC_TOZ_OFFSET 25 +# define DBGREG_DC_TOZ_SIZE 1 +# define DBGREG_DC_IFM_OFFSET 24 +# define DBGREG_DC_IFM_SIZE 1 +# define DBGREG_DC_IRP_OFFSET 23 +# define DBGREG_DC_IRP_SIZE 1 +# define DBGREG_DC_SQA_OFFSET 22 +# define DBGREG_DC_SQA_SIZE 1 +# define DBGREG_DC_EOS_OFFSET 20 +# define DBGREG_DC_EOS_SIZE 2 +# define DBGREG_DC_DBE_OFFSET 13 +# define DBGREG_DC_DBE_SIZE 1 +# define DBGREG_DC_DBR_OFFSET 12 +# define DBGREG_DC_DBR_SIZE 1 +# define DBGREG_DC_SS_OFFSET 8 +# define DBGREG_DC_SS_SIZE 1 +# define DBGREG_DC_OVC_OFFSET 5 +# define DBGREG_DC_OVC_SIZE 3 +# define DBGREG_DC_EIC_OFFSET 3 +# define DBGREG_DC_EIC_SIZE 2 +# define DBGREG_DC_TM_OFFSET 0 +# define DBGREG_DC_TM_SIZE 2 +#define DBGREG_DS 0x00000010 +# define DBGREG_DS_NTBF_OFFSET 28 +# define DBGREG_DS_NTBF_SIZE 1 +# define DBGREG_DS_EXB_OFFSET 27 +# define DBGREG_DS_EXB_SIZE 1 +# define DBGREG_DS_DBA_OFFSET 26 +# define DBGREG_DS_DBA_SIZE 1 +# define DBGREG_DS_BOZ_OFFSET 25 +# define DBGREG_DS_BOZ_SIZE 1 +# define DBGREG_DS_INC_OFFSET 24 +# define DBGREG_DS_INC_SIZE 1 +# define DBGREG_DS_BP_OFFSET 8 +# define DBGREG_DS_BP_SIZE 18 +# define DBGREG_DS_DBS_OFFSET 5 +# define DBGREG_DS_DBS_SIZE 1 +# define DBGREG_DS_STP_OFFSET 4 +# define DBGREG_DS_STP_SIZE 1 +# define DBGREG_DS_HWE_OFFSET 3 +# define DBGREG_DS_HWE_SIZE 1 +# define DBGREG_DS_HWB_OFFSET 2 +# define DBGREG_DS_HWB_SIZE 1 +# define DBGREG_DS_SWB_OFFSET 1 +# define DBGREG_DS_SWB_SIZE 1 +# define DBGREG_DS_SSS_OFFSET 0 +# define DBGREG_DS_SSS_SIZE 1 +#define DBGREG_RWCS 0x0000001C +# define DBGREG_RWCS_AC_OFFSET 31 +# define DBGREG_RWCS_AC_SIZE 1 +# define DBGREG_RWCS_RW_OFFSET 30 +# define DBGREG_RWCS_RW_SIZE 1 +# define DBGREG_RWCS_SZ_OFFSET 27 +# define DBGREG_RWCS_SZ_SIZE 3 +# define DBGREG_RWCS_CCTRL_OFFSET 25 +# define DBGREG_RWCS_CCTRL_SIZE 2 +# define DBGREG_RWCS_WRAPPED_OFFSET 24 +# define DBGREG_RWCS_WRAPPED_SIZE 1 +# define DBGREG_RWCS_NTAP_OFFSET 23 +# define DBGREG_RWCS_NTAP_SIZE 1 +# define DBGREG_RWCS_NTE_OFFSET 22 +# define DBGREG_RWCS_NTE_SIZE 1 +# define DBGREG_RWCS_NTBC_OFFSET 20 +# define DBGREG_RWCS_NTBC_SIZE 2 +# define DBGREG_RWCS_CRC_OFFSET 19 +# define DBGREG_RWCS_CRC_SIZE 1 +# define DBGREG_RWCS_CNT_OFFSET 2 +# define DBGREG_RWCS_CNT_SIZE 14 +# define DBGREG_RWCS_ERR_OFFSET 1 +# define DBGREG_RWCS_ERR_SIZE 1 +# define DBGREG_RWCS_DV_OFFSET 0 +# define DBGREG_RWCS_DV_SIZE 1 +#define DBGREG_RWA 0x00000024 +# define DBGREG_RWA_RWA_OFFSET 0 +# define DBGREG_RWA_RWA_SIZE 32 +#define DBGREG_RWD 0x00000028 +# define DBGREG_RWD_RWD_OFFSET 0 +# define DBGREG_RWD_RWD_SIZE 32 +#define DBGREG_WT 0x0000002C +# define DBGREG_WT_PTS_OFFSET 29 +# define DBGREG_WT_PTS_SIZE 3 +# define DBGREG_WT_PTE_OFFSET 26 +# define DBGREG_WT_PTE_SIZE 3 +# define DBGREG_WT_DTS_OFFSET 23 +# define DBGREG_WT_DTS_SIZE 3 +# define DBGREG_WT_DTE_OFFSET 20 +# define DBGREG_WT_DTE_SIZE 3 +#define DBGREG_DTC 0x00000034 +# define DBGREG_DTC_RWT0_OFFSET 30 +# define DBGREG_DTC_RWT0_SIZE 2 +# define DBGREG_DTC_RWT1_OFFSET 28 +# define DBGREG_DTC_RWT1_SIZE 2 +# define DBGREG_DTC_ASID1_OFFSET 12 +# define DBGREG_DTC_ASID1_SIZE 8 +# define DBGREG_DTC_ASID1EN_OFFSET 11 +# define DBGREG_DTC_ASID1EN_SIZE 1 +# define DBGREG_DTC_ASID0_OFFSET 3 +# define DBGREG_DTC_ASID0_SIZE 8 +# define DBGREG_DTC_ASID0EN_OFFSET 2 +# define DBGREG_DTC_ASID0EN_SIZE 1 +# define DBGREG_DTC_T1WP_OFFSET 1 +# define DBGREG_DTC_T1WP_SIZE 1 +# define DBGREG_DTC_T0WP_OFFSET 0 +# define DBGREG_DTC_T0WP_SIZE 1 +#define DBGREG_DTSA0 0x00000038 +# define DBGREG_DTSA0_DTSA_OFFSET 0 +# define DBGREG_DTSA0_DTSA_SIZE 32 +#define DBGREG_DTSA1 0x0000003C +# define DBGREG_DTSA1_DTSA_OFFSET 0 +# define DBGREG_DTSA1_DTSA_SIZE 32 +#define DBGREG_DTEA0 0x00000048 +# define DBGREG_DTEA0_DTEA_OFFSET 0 +# define DBGREG_DTEA0_DTEA_SIZE 32 +#define DBGREG_DTEA1 0x0000004C +# define DBGREG_DTEA1_DTEA_OFFSET 0 +# define DBGREG_DTEA1_DTEA_SIZE 32 +#define DBGREG_BWC0A 0x00000058 +# define DBGREG_BWC0A_BWE_OFFSET 30 +# define DBGREG_BWC0A_BWE_SIZE 2 +# define DBGREG_BWC0A_AME_OFFSET 25 +# define DBGREG_BWC0A_AME_SIZE 1 +# define DBGREG_BWC0A_AMB_OFFSET 20 +# define DBGREG_BWC0A_AMB_SIZE 5 +# define DBGREG_BWC0A_EOC_OFFSET 14 +# define DBGREG_BWC0A_EOC_SIZE 1 +# define DBGREG_BWC0A_ASID_OFFSET 1 +# define DBGREG_BWC0A_ASID_SIZE 8 +# define DBGREG_BWC0A_ASIDEN_OFFSET 0 +# define DBGREG_BWC0A_ASIDEN_SIZE 1 +#define DBGREG_BWC0B 0x0000005C +# define DBGREG_BWC0B_BWE_OFFSET 30 +# define DBGREG_BWC0B_BWE_SIZE 2 +# define DBGREG_BWC0B_AME_OFFSET 25 +# define DBGREG_BWC0B_AME_SIZE 1 +# define DBGREG_BWC0B_AMB_OFFSET 20 +# define DBGREG_BWC0B_AMB_SIZE 5 +# define DBGREG_BWC0B_EOC_OFFSET 14 +# define DBGREG_BWC0B_EOC_SIZE 1 +# define DBGREG_BWC0B_ASID_OFFSET 1 +# define DBGREG_BWC0B_ASID_SIZE 8 +# define DBGREG_BWC0B_ASIDEN_OFFSET 0 +# define DBGREG_BWC0B_ASIDEN_SIZE 1 +#define DBGREG_BWC1A 0x00000060 +# define DBGREG_BWC1A_BWE_OFFSET 30 +# define DBGREG_BWC1A_BWE_SIZE 2 +# define DBGREG_BWC1A_AME_OFFSET 25 +# define DBGREG_BWC1A_AME_SIZE 1 +# define DBGREG_BWC1A_AMB_OFFSET 20 +# define DBGREG_BWC1A_AMB_SIZE 5 +# define DBGREG_BWC1A_EOC_OFFSET 14 +# define DBGREG_BWC1A_EOC_SIZE 1 +# define DBGREG_BWC1A_ASID_OFFSET 1 +# define DBGREG_BWC1A_ASID_SIZE 8 +# define DBGREG_BWC1A_ASIDEN_OFFSET 0 +# define DBGREG_BWC1A_ASIDEN_SIZE 1 +#define DBGREG_BWC1B 0x00000064 +# define DBGREG_BWC1B_BWE_OFFSET 30 +# define DBGREG_BWC1B_BWE_SIZE 2 +# define DBGREG_BWC1B_AME_OFFSET 25 +# define DBGREG_BWC1B_AME_SIZE 1 +# define DBGREG_BWC1B_AMB_OFFSET 20 +# define DBGREG_BWC1B_AMB_SIZE 5 +# define DBGREG_BWC1B_EOC_OFFSET 14 +# define DBGREG_BWC1B_EOC_SIZE 1 +# define DBGREG_BWC1B_ASID_OFFSET 1 +# define DBGREG_BWC1B_ASID_SIZE 8 +# define DBGREG_BWC1B_ASIDEN_OFFSET 0 +# define DBGREG_BWC1B_ASIDEN_SIZE 1 +#define DBGREG_BWC2A 0x00000068 +# define DBGREG_BWC2A_BWE_OFFSET 30 +# define DBGREG_BWC2A_BWE_SIZE 2 +# define DBGREG_BWC2A_AME_OFFSET 25 +# define DBGREG_BWC2A_AME_SIZE 1 +# define DBGREG_BWC2A_AMB_OFFSET 20 +# define DBGREG_BWC2A_AMB_SIZE 5 +# define DBGREG_BWC2A_EOC_OFFSET 14 +# define DBGREG_BWC2A_EOC_SIZE 1 +# define DBGREG_BWC2A_ASID_OFFSET 1 +# define DBGREG_BWC2A_ASID_SIZE 8 +# define DBGREG_BWC2A_ASIDEN_OFFSET 0 +# define DBGREG_BWC2A_ASIDEN_SIZE 1 +#define DBGREG_BWC2B 0x0000006C +# define DBGREG_BWC2B_BWE_OFFSET 30 +# define DBGREG_BWC2B_BWE_SIZE 2 +# define DBGREG_BWC2B_AME_OFFSET 25 +# define DBGREG_BWC2B_AME_SIZE 1 +# define DBGREG_BWC2B_AMB_OFFSET 20 +# define DBGREG_BWC2B_AMB_SIZE 5 +# define DBGREG_BWC2B_EOC_OFFSET 14 +# define DBGREG_BWC2B_EOC_SIZE 1 +# define DBGREG_BWC2B_ASID_OFFSET 1 +# define DBGREG_BWC2B_ASID_SIZE 8 +# define DBGREG_BWC2B_ASIDEN_OFFSET 0 +# define DBGREG_BWC2B_ASIDEN_SIZE 1 +#define DBGREG_BWC3A 0x00000070 +# define DBGREG_BWC3A_BWE_OFFSET 30 +# define DBGREG_BWC3A_BWE_SIZE 2 +# define DBGREG_BWC3A_BRW_OFFSET 28 +# define DBGREG_BWC3A_BRW_SIZE 2 +# define DBGREG_BWC3A_BME_OFFSET 20 +# define DBGREG_BWC3A_BME_SIZE 4 +# define DBGREG_BWC3A_BWO_OFFSET 16 +# define DBGREG_BWC3A_BWO_SIZE 2 +# define DBGREG_BWC3A_EOC_OFFSET 14 +# define DBGREG_BWC3A_EOC_SIZE 1 +# define DBGREG_BWC3A_SIZE_OFFSET 9 +# define DBGREG_BWC3A_SIZE_SIZE 3 +# define DBGREG_BWC3A_ASID_OFFSET 1 +# define DBGREG_BWC3A_ASID_SIZE 8 +# define DBGREG_BWC3A_ASIDEN_OFFSET 0 +# define DBGREG_BWC3A_ASIDEN_SIZE 1 +#define DBGREG_BWC3B 0x00000074 +# define DBGREG_BWC3B_BWE_OFFSET 30 +# define DBGREG_BWC3B_BWE_SIZE 2 +# define DBGREG_BWC3B_BRW_OFFSET 28 +# define DBGREG_BWC3B_BRW_SIZE 2 +# define DBGREG_BWC3B_BME_OFFSET 20 +# define DBGREG_BWC3B_BME_SIZE 4 +# define DBGREG_BWC3B_BWO_OFFSET 16 +# define DBGREG_BWC3B_BWO_SIZE 2 +# define DBGREG_BWC3B_EOC_OFFSET 14 +# define DBGREG_BWC3B_EOC_SIZE 1 +# define DBGREG_BWC3B_SIZE_OFFSET 9 +# define DBGREG_BWC3B_SIZE_SIZE 3 +# define DBGREG_BWC3B_ASID_OFFSET 1 +# define DBGREG_BWC3B_ASID_SIZE 8 +# define DBGREG_BWC3B_ASIDEN_OFFSET 0 +# define DBGREG_BWC3B_ASIDEN_SIZE 1 +#define DBGREG_BWA0A 0x00000078 +# define DBGREG_BWA0A_BWA_OFFSET 0 +# define DBGREG_BWA0A_BWA_SIZE 32 +#define DBGREG_BWA0B 0x0000007C +# define DBGREG_BWA0B_BWA_OFFSET 0 +# define DBGREG_BWA0B_BWA_SIZE 32 +#define DBGREG_BWA1A 0x00000080 +# define DBGREG_BWA1A_BWA_OFFSET 0 +# define DBGREG_BWA1A_BWA_SIZE 32 +#define DBGREG_BWA1B 0x00000084 +# define DBGREG_BWA1B_BWA_OFFSET 0 +# define DBGREG_BWA1B_BWA_SIZE 32 +#define DBGREG_BWA2A 0x00000088 +# define DBGREG_BWA2A_BWA_OFFSET 0 +# define DBGREG_BWA2A_BWA_SIZE 32 +#define DBGREG_BWA2B 0x0000008C +# define DBGREG_BWA2B_BWA_OFFSET 0 +# define DBGREG_BWA2B_BWA_SIZE 32 +#define DBGREG_BWA3A 0x00000090 +# define DBGREG_BWA3A_BWA_OFFSET 0 +# define DBGREG_BWA3A_BWA_SIZE 32 +#define DBGREG_BWA3B 0x00000094 +# define DBGREG_BWA3B_BWA_OFFSET 0 +# define DBGREG_BWA3B_BWA_SIZE 32 +#define DBGREG_NXCFG 0x00000100 +# define DBGREG_NXCFG_NXDMA_OFFSET 28 +# define DBGREG_NXCFG_NXDMA_SIZE 1 +# define DBGREG_NXCFG_NXDTC_OFFSET 25 +# define DBGREG_NXCFG_NXDTC_SIZE 3 +# define DBGREG_NXCFG_NXDRT_OFFSET 24 +# define DBGREG_NXCFG_NXDRT_SIZE 1 +# define DBGREG_NXCFG_NXDWT_OFFSET 23 +# define DBGREG_NXCFG_NXDWT_SIZE 1 +# define DBGREG_NXCFG_NXOT_OFFSET 22 +# define DBGREG_NXCFG_NXOT_SIZE 1 +# define DBGREG_NXCFG_NXPT_OFFSET 21 +# define DBGREG_NXCFG_NXPT_SIZE 1 +# define DBGREG_NXCFG_NXMDO_OFFSET 17 +# define DBGREG_NXCFG_NXMDO_SIZE 4 +# define DBGREG_NXCFG_MXMSEO_OFFSET 16 +# define DBGREG_NXCFG_MXMSEO_SIZE 1 +# define DBGREG_NXCFG_NXDB_OFFSET 12 +# define DBGREG_NXCFG_NXDB_SIZE 4 +# define DBGREG_NXCFG_NXPCB_OFFSET 8 +# define DBGREG_NXCFG_NXPCB_SIZE 4 +# define DBGREG_NXCFG_NXOCD_OFFSET 4 +# define DBGREG_NXCFG_NXOCD_SIZE 4 +# define DBGREG_NXCFG_NXARCH_OFFSET 0 +# define DBGREG_NXCFG_NXARCH_SIZE 4 +#define DBGREG_DINST 0x00000104 +# define DBGREG_DINST_DINST_OFFSET 0 +# define DBGREG_DINST_DINST_SIZE 32 +#define DBGREG_DPC 0x00000108 +#define DBGREG_CPUCM 0x0000010C +# define DBGREG_CPUCM_IEEM_OFFSET 5 +# define DBGREG_CPUCM_IEEM_SIZE 1 +# define DBGREG_CPUCM_IBEM_OFFSET 4 +# define DBGREG_CPUCM_IBEM_SIZE 1 +# define DBGREG_CPUCM_REM_OFFSET 3 +# define DBGREG_CPUCM_REM_SIZE 1 +# define DBGREG_CPUCM_FEM_OFFSET 2 +# define DBGREG_CPUCM_FEM_SIZE 1 +# define DBGREG_CPUCM_BEM_OFFSET 1 +# define DBGREG_CPUCM_BEM_SIZE 1 +#define DBGREG_DCCPU 0x00000110 +# define DBGREG_DCCPU_DATA_OFFSET 0 +# define DBGREG_DCCPU_DATA_SIZE 32 +#define DBGREG_DCEMU 0x00000114 +# define DBGREG_DCEMU_DATA_OFFSET 0 +# define DBGREG_DCEMU_DATA_SIZE 32 +#define DBGREG_DCSR 0x00000118 +# define DBGREG_DCSR_EMUD_OFFSET 1 +# define DBGREG_DCSR_EMUD_SIZE 1 +# define DBGREG_DCSR_CPUD_OFFSET 0 +# define DBGREG_DCSR_CPUD_SIZE 1 +#define DBGREG_PID 0x0000011C +# define DBGREG_PID_PROCESS_OFFSET 0 +# define DBGREG_PID_PROCESS_SIZE 32 +#define DBGREG_EPC0 0x00000120 +# define DBGREG_EPC0_ECNT_OFFSET 16 +# define DBGREG_EPC0_ECNT_SIZE 16 +# define DBGREG_EPC0_CE_OFFSET 4 +# define DBGREG_EPC0_CE_SIZE 1 +# define DBGREG_EPC0_RNG_OFFSET 0 +# define DBGREG_EPC0_RNG_SIZE 2 +#define DBGREG_EPC1 0x00000124 +# define DBGREG_EPC1_AM_OFFSET 6 +# define DBGREG_EPC1_AM_SIZE 1 +# define DBGREG_EPC1_ATB_OFFSET 5 +# define DBGREG_EPC1_ATB_SIZE 1 +# define DBGREG_EPC1_RNG_OFFSET 0 +# define DBGREG_EPC1_RNG_SIZE 2 +#define DBGREG_EPC2 0x00000128 +# define DBGREG_EPC2_DB_OFFSET 2 +# define DBGREG_EPC2_DB_SIZE 2 +# define DBGREG_EPC2_RNG_OFFSET 0 +# define DBGREG_EPC2_RNG_SIZE 2 +#define DBGREG_EPC3 0x0000012C +# define DBGREG_EPC3_DWE_OFFSET 2 +# define DBGREG_EPC3_DWE_SIZE 1 +# define DBGREG_EPC3_RNG_OFFSET 0 +# define DBGREG_EPC3_RNG_SIZE 2 +#define DBGREG_AXC 0x00000130 +# define DBGREG_AXC_REX_OFFSET 12 +# define DBGREG_AXC_REX_SIZE 1 +# define DBGREG_AXC_REXTEN_OFFSET 13 +# define DBGREG_AXC_REXTEN_SIZE 1 +# define DBGREG_AXC_LS_OFFSET 11 +# define DBGREG_AXC_LS_SIZE 1 +# define DBGREG_AXC_DDR_OFFSET 10 +# define DBGREG_AXC_DDR_SIZE 1 +# define DBGREG_AXC_AXS_OFFSET 9 +# define DBGREG_AXC_AXS_SIZE 1 +# define DBGREG_AXC_AXE_OFFSET 8 +# define DBGREG_AXC_AXE_SIZE 1 +# define DBGREG_AXC_DIV_OFFSET 0 +# define DBGREG_AXC_DIV_SIZE 4 + +#define DBGREG_BIT(name) (1 << DBGREG_##name##_OFFSET) +#define DBGREG_MKBF(name, value) (((value) & ((1 << DBGREG_##name##_SIZE) - 1)) << DBGREG_##name##_OFFSET) +#define DBGREG_GETBF(name, value) (((value) >> DBGREG_##name##_OFFSET) & ((1 << DBGREG_##name##_SIZE) - 1)) + +#define dbgreg_read(addr) __builtin_mfdr(addr) +#define dbgreg_write(addr, value) __builtin_mtdr(addr, value) + +#endif /* __ASM_AVR32_DBGREGS_H__ */ diff -Nur u-boot-1.1.4/include/asm-avr32/dma-mapping.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/dma-mapping.h --- u-boot-1.1.4/include/asm-avr32/dma-mapping.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/dma-mapping.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_DMA_MAPPING_H +#define __ASM_AVR32_DMA_MAPPING_H + +#include +#include + +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, +}; +extern void *dma_alloc_coherent(size_t len, unsigned long *handle); + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + extern void __bad_dma_data_direction(void); + + switch (dir) { + case DMA_BIDIRECTIONAL: + dcache_flush_range(vaddr, len); + break; + case DMA_TO_DEVICE: + dcache_clean_range(vaddr, len); + break; + case DMA_FROM_DEVICE: + dcache_invalidate_range(vaddr, len); + break; + default: + /* This will cause a linker error */ + __bad_dma_data_direction(); + } + + return virt_to_phys(vaddr); +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ + +} + +#endif /* __ASM_AVR32_DMA_MAPPING_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/errno-base.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/errno-base.h --- u-boot-1.1.4/include/asm-avr32/errno-base.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/errno-base.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_GENERIC_ERRNO_BASE_H +#define _ASM_GENERIC_ERRNO_BASE_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#endif diff -Nur u-boot-1.1.4/include/asm-avr32/errno.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/errno.h --- u-boot-1.1.4/include/asm-avr32/errno.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/errno.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_GENERIC_ERRNO_H +#define _ASM_GENERIC_ERRNO_H + +#include + +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#endif diff -Nur u-boot-1.1.4/include/asm-avr32/global_data.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/global_data.h --- u-boot-1.1.4/include/asm-avr32/global_data.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/global_data.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_GLOBAL_DATA_H__ +#define __ASM_GLOBAL_DATA_H__ + +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + const struct device *console_uart; + const struct device *sm; + unsigned long baudrate; + unsigned long sdram_size; + unsigned long have_console; /* serial_init() was called */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of env struct */ + unsigned long env_valid; /* Checksum of env valid? */ + unsigned long cpu_hz; /* TODO: remove */ + void **jt; +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5") + +#endif /* __ASM_GLOBAL_DATA_H__ */ diff -Nur u-boot-1.1.4/include/asm-avr32/initcalls.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/initcalls.h --- u-boot-1.1.4/include/asm-avr32/initcalls.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/initcalls.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2005, 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_INITCALLS_H__ +#define __ASM_AVR32_INITCALLS_H__ + +#include + +extern int cpu_init(void); +extern int timer_init(void); +extern void board_init_memories(void); +extern void board_init_pio(void); +extern void board_init_info(void); + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +extern void net_init(void); +#else +static inline void net_init(void) { } +#endif + +#ifdef CFG_DMA_ALLOC_START +extern void dma_mem_init(void); +#else +static inline void dma_mem_init(void) { } +#endif + +#endif /* __ASM_AVR32_INITCALLS_H__ */ diff -Nur u-boot-1.1.4/include/asm-avr32/io.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/io.h --- u-boot-1.1.4/include/asm-avr32/io.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/io.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_IO_H +#define __ASM_AVR32_IO_H + +#ifdef __KERNEL__ + +/* + * Generic IO read/write. These perform native-endian accesses. Note + * that some architectures will want to re-define __raw_{read,write}w. + */ +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +/* As long as I/O is only performed in P4 (or possibly P3), we're safe */ +#define writeb(v,a) __raw_writeb(v,a) +#define writew(v,a) __raw_writew(v,a) +#define writel(v,a) __raw_writel(v,a) + +#define readb(a) __raw_readb(a) +#define readw(a) __raw_readw(a) +#define readl(a) __raw_readl(a) + +/* + * Bad read/write accesses... + */ +extern void __readwrite_bug(const char *fn); + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * All I/O is memory mapped, so these macros doesn't make very much sense + */ +#define outb(v,p) __raw_writeb(v, p) +#define outw(v,p) __raw_writew(cpu_to_le16(v),p) +#define outl(v,p) __raw_writel(cpu_to_le32(v),p) + +#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) +#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) +#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) + +#include + +/* virt_to_phys will only work when address is in P1 or P2 */ +static __inline__ unsigned long virt_to_phys(volatile void *address) +{ + return PHYSADDR(address); +} + +static __inline__ void * phys_to_virt(unsigned long address) +{ + return (void *)P1SEGADDR(address); +} + +#define DEV_ACCESSOR_FUNCTIONS(size, type, dev, name) \ + static inline type name##_read##size (unsigned long offset) \ + { \ + DECLARE_GLOBAL_DATA_PTR; \ + return read##size (gd->devices[dev] + offset); \ + } \ + static inline void name##_write##size (type value, \ + unsigned long offset) \ + { \ + DECLARE_GLOBAL_DATA_PTR; \ + write##size (value, gd->devices[dev] + offset); \ + } + +#define cached(addr) ((void *)P1SEGADDR(addr)) +#define uncached(addr) ((void *)P2SEGADDR(addr)) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_AVR32_IO_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/kmap_types.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/kmap_types.h --- u-boot-1.1.4/include/asm-avr32/kmap_types.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/kmap_types.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_KMAP_TYPES_H +#define __ASM_AVR32_KMAP_TYPES_H + +#include + +#ifdef CONFIG_DEBUG_HIGHMEM +# define D(n) __KM_FENCE_##n , +#else +# define D(n) +#endif + +enum km_type { +D(0) KM_BOUNCE_READ, +D(1) KM_SKB_SUNRPC_DATA, +D(2) KM_SKB_DATA_SOFTIRQ, +D(3) KM_USER0, +D(4) KM_USER1, +D(5) KM_BIO_SRC_IRQ, +D(6) KM_BIO_DST_IRQ, +D(7) KM_PTE0, +D(8) KM_PTE1, +D(9) KM_PTE2, +D(10) KM_IRQ0, +D(11) KM_IRQ1, +D(12) KM_SOFTIRQ0, +D(13) KM_SOFTIRQ1, +D(14) KM_TYPE_NR +}; + +#undef D + +#endif /* __ASM_AVR32_KMAP_TYPES_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/mmc.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/mmc.h --- u-boot-1.1.4/include/asm-avr32/mmc.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/mmc.h 2006-06-21 11:58:25.000000000 +0200 @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_MMC_H +#define __ASM_AVR32_MMC_H + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure:2, + spec_vers:4, + rsvd1:2; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc:12, + read_bl_len:4; + u64 read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + sector_size:5, + erase_grp_size:5, + wp_grp_size:5, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:5; + u8 file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; + u8 crc:7; + u8 one:1; +}; + +/* MMC Command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +#define MMC_ACMD_SD_SEND_OP_COND 41 + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#endif /* __ASM_AVR32_MMC_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/page.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/page.h --- u-boot-1.1.4/include/asm-avr32/page.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/page.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PAGE_H +#define __ASM_AVR32_PAGE_H + +/* PAGE_SHIFT determines the page size */ +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) +#define PTE_MASK PAGE_MASK + +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + +extern void clear_page(void *to); +extern void copy_page(void *to, void *from); + +#define clear_user_page(page, vaddr, pg) clear_page(page) +#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { unsigned long pte; } pte_t; +typedef struct { unsigned long pmd; } pmd_t; +typedef struct { unsigned long pgd; } pgd_t; +typedef struct { unsigned long pgprot; } pgprot_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((x).pmd) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) }) +#define __pmd(x) ((pmd_t) { (x) }) +#define __pgd(x) ((pgd_t) { (x) }) +#define __pgprot(x) ((pgprot_t) { (x) }) + +extern unsigned long memory_start, memory_end; + +#endif /* !__ASSEMBLY__ */ + +/* Align the pointer to the (next) page boundary */ +#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) + +#define PAGE_OFFSET (0x80000000UL) +#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET) +#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET)) + +#define MAP_NR(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> PAGE_SHIFT) + +#define phys_to_page(phys) (mem_map + ((phys) >> PAGE_SHIFT)) +#define page_to_phys(page) (((page) - mem_map) << PAGE_SHIFT) + +#define pfn_to_page(pfn) (mem_map + (pfn)) +#define page_to_pfn(page) ((unsigned long)((page) - mem_map)) +#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) +#define pfn_valid(pfn) ((pfn) < max_mapnr) +#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) + +#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +/* + * Memory above this physical address will be considered highmem. + */ +#define HIGHMEM_START 0x20000000UL + +#endif /* __KERNEL__ */ + +#endif /* __ASM_AVR32_PAGE_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/posix_types.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/posix_types.h --- u-boot-1.1.4/include/asm-avr32/posix_types.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/posix_types.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_POSIX_TYPES_H +#define __ASM_AVR32_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +/* XXX: This file was shamelessly stolen from SH */ +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned long __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; +typedef unsigned short __kernel_old_dev_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* __ASM_AVR32_POSIX_TYPES_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/processor.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/processor.h --- u-boot-1.1.4/include/asm-avr32/processor.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/processor.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PROCESSOR_H +#define __ASM_AVR32_PROCESSOR_H + +#include + +#ifndef __ASSEMBLY__ + +#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; }) + +struct avr32_cpuinfo { + unsigned long loops_per_jiffy; +}; + +extern struct avr32_cpuinfo boot_cpu_data; + +#ifdef CONFIG_SMP +extern struct avr32_cpuinfo cpu_data[]; +#define current_cpu_data cpu_data[smp_processor_id()] +#else +#define cpu_data (&boot_cpu_data) +#define current_cpu_data boot_cpu_data +#endif + +/* TODO: Make configurable (2GB will serve as a reasonable default) */ +#define TASK_SIZE 0x80000000 + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +#define cpu_relax() barrier() + +/* This struct contains the CPU context as stored by switch_to() */ +struct thread_struct { + unsigned long pc; + unsigned long ksp; /* Kernel stack pointer */ + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; +}; + +#define INIT_THREAD { \ + .ksp = sizeof(init_stack) + (long)&init_stack, \ +} + +/* + * Do necessary setup to start up a newly executed thread. + */ +#define start_thread(regs, new_pc, new_sp) \ + set_fs(USER_DS); \ + regs->sr = 0; /* User mode. */ \ + regs->gr[REG_PC] = new_pc; \ + regs->gr[REG_SP] = new_sp + +struct task_struct; + +/* Free all resources held by a thread */ +extern void release_thread(struct task_struct *); + +/* Create a kernel thread without removing it from tasklists */ +extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +/* Prepare to copy thread state - unlazy all lazy status */ +#define prepare_to_copy(tsk) do { } while(0) + +/* Return saved PC of a blocked thread */ +#define thread_saved_pc(tsk) (tsk->thread.pc) + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_AVR32_PROCESSOR_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/ptrace.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/ptrace.h --- u-boot-1.1.4/include/asm-avr32/ptrace.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/ptrace.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_PTRACE_H +#define __ASM_AVR32_PTRACE_H + +/* + * Status Register bits + */ +#define SR_H 0x40000000 +#define SR_R 0x20000000 +#define SR_J 0x10000000 +#define SR_DM 0x08000000 +#define SR_D 0x04000000 +#define MODE_NMI 0x01c00000 +#define MODE_EXCEPTION 0x01800000 +#define MODE_INT3 0x01400000 +#define MODE_INT2 0x01000000 +#define MODE_INT1 0x00c00000 +#define MODE_INT0 0x00800000 +#define MODE_SUPERVISOR 0x00400000 +#define MODE_USER 0x00000000 +#define MODE_MASK 0x01c00000 +#define SR_EM 0x00200000 +#define SR_I3M 0x00100000 +#define SR_I2M 0x00080000 +#define SR_I1M 0x00040000 +#define SR_I0M 0x00020000 +#define SR_GM 0x00010000 + +#define MODE_SHIFT 22 +#define SR_EM_BIT 21 +#define SR_I3M_BIT 20 +#define SR_I2M_BIT 19 +#define SR_I1M_BIT 18 +#define SR_I0M_BIT 17 +#define SR_GM_BIT 16 + +/* The user-visible part */ +#define SR_Q 0x00000010 +#define SR_V 0x00000008 +#define SR_N 0x00000004 +#define SR_Z 0x00000002 +#define SR_C 0x00000001 + +/* + * The order is defined by the stdsp instruction. r0 is stored first, so it + * gets the highest address. + * + * Registers 0-12 are general-purpose registers (r12 is normally used for + * the function return value). + * Register 13 is the stack pointer + * Register 14 is the link register + * Register 15 is the program counter + */ +#define FRAME_SIZE_FULL 72 +#define REG_R12_ORIG 68 +#define REG_R0 64 +#define REG_R1 60 +#define REG_R2 56 +#define REG_R3 52 +#define REG_R4 48 +#define REG_R5 44 +#define REG_R6 40 +#define REG_R7 36 +#define REG_R8 32 +#define REG_R9 28 +#define REG_R10 34 +#define REG_R11 20 +#define REG_R12 16 +#define REG_SP 12 +#define REG_LR 8 + +#define FRAME_SIZE_MIN 8 +#define REG_PC 4 +#define REG_SR 0 + +#ifndef __ASSEMBLY__ +struct pt_regs { + /* These are always saved */ + unsigned long sr; + unsigned long pc; + + /* These are sometimes saved */ + unsigned long lr; + unsigned long sp; + unsigned long r12; + unsigned long r11; + unsigned long r10; + unsigned long r9; + unsigned long r8; + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; + + /* Only saved on system call */ + unsigned long r12_orig; +}; + +#ifdef __KERNEL__ +# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) +# define instruction_pointer(regs) ((regs)->pc) +extern void show_regs (struct pt_regs *); + +static __inline__ int valid_user_regs(struct pt_regs *regs) +{ + /* + * Some of the Java bits might be acceptable if/when we + * implement some support for that stuff... + */ + if ((regs->sr & 0xffff0000) == 0) + return 1; + + /* + * Force status register flags to be sane and report this + * illegal behaviour... + */ + regs->sr &= 0x0000ffff; + return 0; +} +#endif + +#endif /* ! __ASSEMBLY__ */ + +#endif /* __ASM_AVR32_PTRACE_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/sdram.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/sdram.h --- u-boot-1.1.4/include/asm-avr32/sdram.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/sdram.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SDRAM_H +#define __ASM_AVR32_SDRAM_H + +struct sdram_info { + unsigned long phys_addr; + unsigned int row_bits, col_bits, bank_bits; + unsigned int cas, twr, trc, trp, trcd, tras, txsr; +}; + +extern unsigned long sdram_init(const struct sdram_info *info); + +#endif /* __ASM_AVR32_SDRAM_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/sections.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/sections.h --- u-boot-1.1.4/include/asm-avr32/sections.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/sections.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SECTIONS_H +#define __ASM_AVR32_SECTIONS_H + +/* References to section boundaries */ + +extern char _text[], _etext[]; +extern char __flashprog_start[], __flashprog_end[]; +extern char _data[], __data_lma[], _edata[], __edata_lma[]; +extern char __got_start[], __got_lma[], __got_end[]; +extern char _end[]; + +/* + * Everything in .flashprog will be locked in the icache so it doesn't + * get disturbed when executing flash commands. + */ +#define __flashprog __attribute__((section(".flashprog"), __noinline__)) + +#endif /* __ASM_AVR32_SECTIONS_H */ + diff -Nur u-boot-1.1.4/include/asm-avr32/setup.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/setup.h --- u-boot-1.1.4/include/asm-avr32/setup.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/setup.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * Based on linux/include/asm-arm/setup.h + * Copyright (C) 1997-1999 Russel King + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SETUP_H__ +#define __ASM_AVR32_SETUP_H__ + +#define COMMAND_LINE_SIZE 256 + +/* Magic number indicating that a tag table is present */ +#define ATAG_MAGIC 0xa2a25441 + +#ifndef __ASSEMBLY__ + +/* + * Generic memory range, used by several tags. + * + * addr is always physical. + * size is measured in bytes. + * next is for use by the OS, e.g. for grouping regions into + * linked lists. + */ +struct tag_mem_range { + u32 addr; + u32 size; + struct tag_mem_range * next; +}; + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 +/* ATAG_MEM uses tag_mem_range */ + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410003 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* Ramdisk image (may be compressed) */ +#define ATAG_RDIMG 0x54410004 +/* ATAG_RDIMG uses tag_mem_range */ + +/* Information about various clocks present in the system */ +#define ATAG_CLOCK 0x54410005 + +struct tag_clock { + u32 clock_id; /* Which clock are we talking about? */ + u32 clock_flags; /* Special features */ + u64 clock_hz; /* Clock speed in Hz */ +}; + +/* The clock types we know about */ +#define CLOCK_BOOTCPU 0 +#define CLOCK_AMBA 1 + +/* Memory reserved for the system (e.g. the bootloader) */ +#define ATAG_RSVD_MEM 0x54410006 +/* ATAG_RSVD_MEM uses tag_mem_range */ + +/* Ethernet information */ + +#define ATAG_ETHERNET 0x54410007 + +struct tag_ethernet { + u8 mac_index; + u8 mii_phy_addr; + u8 hw_address[6]; +}; + +#define ETH_INVALID_PHY 0xff + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem_range mem_range; + struct tag_cmdline cmdline; + struct tag_clock clock; + struct tag_ethernet ethernet; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(struct tag *); +}; + +#define __tag __attribute_used__ __attribute__((__section__(".taglist"))) +#define __tagtable(tag, fn) \ + static struct tagtable __tagtable_##fn __tag = { tag, fn } + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +extern struct tag_mem_range *mem_phys; +extern struct tag_mem_range *mem_reserved; +extern struct tag_mem_range *mem_ramdisk; + +extern struct tag *bootloader_tags; + +extern void setup_bootmem(void); +extern void setup_board(struct tag **); +extern void setup_processor(void); + +#endif /* !__ASSEMBLY__ */ + +#endif /* __ASM_AVR32_SETUP_H__ */ + diff -Nur u-boot-1.1.4/include/asm-avr32/string.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/string.h --- u-boot-1.1.4/include/asm-avr32/string.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/string.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_STRING_H +#define __ASM_AVR32_STRING_H + +#define __HAVE_ARCH_MEMSET +extern void *memset(void *s, int c, size_t n); + +#endif /* __ASM_AVR32_STRING_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/sysregs.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/sysregs.h --- u-boot-1.1.4/include/asm-avr32/sysregs.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/sysregs.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SYSREGS_H__ +#define __ASM_AVR32_SYSREGS_H__ + +#define SYSREG_SR 0x00000000 +# define SYSREG_SR_H_OFFSET 30 +# define SYSREG_SR_H_SIZE 1 +# define SYSREG_SR_R_OFFSET 29 +# define SYSREG_SR_R_SIZE 1 +# define SYSREG_SR_J_OFFSET 28 +# define SYSREG_SR_J_SIZE 1 +# define SYSREG_SR_DM_OFFSET 27 +# define SYSREG_SR_DM_SIZE 1 +# define SYSREG_SR_D_OFFSET 26 +# define SYSREG_SR_D_SIZE 1 +# define SYSREG_SR_M2_OFFSET 24 +# define SYSREG_SR_M2_SIZE 1 +# define SYSREG_SR_M1_OFFSET 23 +# define SYSREG_SR_M1_SIZE 1 +# define SYSREG_SR_M0_OFFSET 22 +# define SYSREG_SR_M0_SIZE 1 +# define SYSREG_SR_EM_OFFSET 21 +# define SYSREG_SR_EM_SIZE 1 +# define SYSREG_SR_I3M_OFFSET 20 +# define SYSREG_SR_I3M_SIZE 1 +# define SYSREG_SR_I2M_OFFSET 19 +# define SYSREG_SR_I2M_SIZE 1 +# define SYSREG_SR_I1M_OFFSET 18 +# define SYSREG_SR_I1M_SIZE 1 +# define SYSREG_SR_I0M_OFFSET 17 +# define SYSREG_SR_I0M_SIZE 1 +# define SYSREG_SR_GM_OFFSET 16 +# define SYSREG_SR_GM_SIZE 1 +# define SYSREG_SR_Q_OFFSET 4 +# define SYSREG_SR_Q_SIZE 1 +# define SYSREG_SR_V_OFFSET 3 +# define SYSREG_SR_V_SIZE 1 +# define SYSREG_SR_N_OFFSET 2 +# define SYSREG_SR_N_SIZE 1 +# define SYSREG_SR_Z_OFFSET 1 +# define SYSREG_SR_Z_SIZE 1 +# define SYSREG_SR_C_OFFSET 0 +# define SYSREG_SR_C_SIZE 1 +#define SYSREG_EVBA 0x00000004 +#define SYSREG_ACBA 0x00000008 +#define SYSREG_CPUCR 0x0000000C +# define SYSREG_CPUCR_IEE_OFFSET 5 +# define SYSREG_CPUCR_IEE_SIZE 1 +# define SYSREG_CPUCR_IBE_OFFSET 4 +# define SYSREG_CPUCR_IBE_SIZE 1 +# define SYSREG_CPUCR_RE_OFFSET 3 +# define SYSREG_CPUCR_RE_SIZE 1 +# define SYSREG_CPUCR_FE_OFFSET 2 +# define SYSREG_CPUCR_FE_SIZE 1 +# define SYSREG_CPUCR_BE_OFFSET 1 +# define SYSREG_CPUCR_BE_SIZE 1 +# define SYSREG_CPUCR_BI_OFFSET 0 +# define SYSREG_CPUCR_BI_SIZE 1 +#define SYSREG_ECR 0x00000010 +#define SYSREG_RSR_SUP 0x00000014 +#define SYSREG_RSR_INT0 0x00000018 +#define SYSREG_RSR_INT1 0x0000001C +#define SYSREG_RSR_INT2 0x00000020 +#define SYSREG_RSR_INT3 0x00000024 +#define SYSREG_RSR_EX 0x00000028 +#define SYSREG_RSR_NMI 0x0000002C +#define SYSREG_RSR_DBG 0x00000030 +#define SYSREG_RAR_SUP 0x00000034 +#define SYSREG_RAR_INT0 0x00000038 +#define SYSREG_RAR_INT1 0x0000003C +#define SYSREG_RAR_INT2 0x00000040 +#define SYSREG_RAR_INT3 0x00000044 +#define SYSREG_RAR_EX 0x00000048 +#define SYSREG_RAR_NMI 0x0000004C +#define SYSREG_RAR_DBG 0x00000050 +#define SYSREG_JECR 0x00000054 +#define SYSREG_JOSP 0x00000058 +#define SYSREG_JAVA_LV0 0x0000005C +#define SYSREG_JAVA_LV1 0x00000060 +#define SYSREG_JAVA_LV2 0x00000064 +#define SYSREG_JAVA_LV3 0x00000068 +#define SYSREG_JAVA_LV4 0x0000006C +#define SYSREG_JAVA_LV5 0x00000070 +#define SYSREG_JAVA_LV6 0x00000074 +#define SYSREG_JAVA_LV7 0x00000078 +#define SYSREG_JTBA 0x0000007C +#define SYSREG_JBCR 0x00000080 +#define SYSREG_CONFIG0 0x00000100 +# define SYSREG_CONFIG0_ProcessorID_OFFSET 24 +# define SYSREG_CONFIG0_ProcessorID_SIZE 8 +# define SYSREG_CONFIG0_ProcessorRevision_OFFSET 16 +# define SYSREG_CONFIG0_ProcessorRevision_SIZE 8 +# define SYSREG_CONFIG0_AT_OFFSET 13 +# define SYSREG_CONFIG0_AT_SIZE 3 +# define SYSREG_CONFIG0_AR_OFFSET 10 +# define SYSREG_CONFIG0_AR_SIZE 3 +# define SYSREG_CONFIG0_MMUT_OFFSET 7 +# define SYSREG_CONFIG0_MMUT_SIZE 3 +# define SYSREG_CONFIG0_F_OFFSET 6 +# define SYSREG_CONFIG0_F_SIZE 1 +# define SYSREG_CONFIG0_J_OFFSET 5 +# define SYSREG_CONFIG0_J_SIZE 1 +# define SYSREG_CONFIG0_P_OFFSET 4 +# define SYSREG_CONFIG0_P_SIZE 1 +# define SYSREG_CONFIG0_O_OFFSET 3 +# define SYSREG_CONFIG0_O_SIZE 1 +# define SYSREG_CONFIG0_S_OFFSET 2 +# define SYSREG_CONFIG0_S_SIZE 1 +# define SYSREG_CONFIG0_D_OFFSET 1 +# define SYSREG_CONFIG0_D_SIZE 1 +#define SYSREG_CONFIG1 0x00000104 +# define SYSREG_CONFIG1_IMMUSZ_OFFSET 26 +# define SYSREG_CONFIG1_IMMUSZ_SIZE 6 +# define SYSREG_CONFIG1_DMMUSZ_OFFSET 20 +# define SYSREG_CONFIG1_DMMUSZ_SIZE 6 +# define SYSREG_CONFIG1_ISET_OFFSET 16 +# define SYSREG_CONFIG1_ISET_SIZE 4 +# define SYSREG_CONFIG1_ILSZ_OFFSET 13 +# define SYSREG_CONFIG1_ILSZ_SIZE 3 +# define SYSREG_CONFIG1_IASS_OFFSET 10 +# define SYSREG_CONFIG1_IASS_SIZE 2 +# define SYSREG_CONFIG1_DSET_OFFSET 6 +# define SYSREG_CONFIG1_DSET_SIZE 4 +# define SYSREG_CONFIG1_DLSZ_OFFSET 3 +# define SYSREG_CONFIG1_DLSZ_SIZE 3 +# define SYSREG_CONFIG1_DASS_OFFSET 0 +# define SYSREG_CONFIG1_DASS_SIZE 3 +#define SYSREG_COUNT 0x00000108 +#define SYSREG_COMPARE 0x0000010C +#define SYSREG_TLBEHI 0x00000110 +#define SYSREG_TLBELO 0x00000114 +#define SYSREG_PTBR 0x00000118 +#define SYSREG_TLBEAR 0x0000011C +#define SYSREG_MMUCR 0x00000120 +#define SYSREG_TLBARLO 0x00000124 +#define SYSREG_TLBARHI 0x00000128 +#define SYSREG_PCCNT 0x0000012C +#define SYSREG_PCNT0 0x00000130 +#define SYSREG_PCNT1 0x00000134 +#define SYSREG_PCCR 0x00000138 +#define SYSREG_SABAL 0x0000013C +#define SYSREG_SABAH 0x00000140 +#define SYSREG_SABD 0x00000144 +#define SYSREG_BEAR 0x00000148 + +#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) +#define SYSREG_MKBF(name, value) (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) << SYSREG_##name##_OFFSET) +#define SYSREG_GETBF(name, value) (((value) >> SYSREG_##name##_OFFSET) & ((1 << SYSREG_##name##_SIZE) - 1)) + +/* Exception causes (stored in SYSREG_ECR) */ +#define ECR_UNRECOVERABLE 0x00 +#define ECR_TLB_MULTIPLE 0x01 +#define ECR_BUS_ERROR_WRITE 0x02 +#define ECR_BUS_ERROR_READ 0x03 +#define ECR_NMI 0x04 +#define ECR_INSN_ADDR 0x05 +#define ECR_TLB_PROTECTION_X 0x06 +#define ECR_BREAKPOINT 0x07 +#define ECR_ILL_OPCODE 0x08 +#define ECR_UNIMPL_INSN 0x09 +#define ECR_PRIV_VIOLATION 0x0a +#define ECR_FLOATING_POINT 0x0b +#define ECR_COPROC_ABSENT 0x0c +#define ECR_DATA_ADDR_R 0x0d +#define ECR_DATA_ADDR_W 0x0e +#define ECR_TLB_PROTECTION_R 0x0f +#define ECR_TLB_PROTECTION_W 0x10 +#define ECR_DIRTY_PAGE 0x11 +#define ECR_TLB_MISS_X 0x14 +#define ECR_TLB_MISS_R 0x18 +#define ECR_TLB_MISS_W 0x1c + +#define sysreg_read(addr) __builtin_mfsr(addr) +#define sysreg_write(addr, value) __builtin_mtsr(addr, value) + +#endif /* __ASM_AVR32_SYSREGS_H__ */ diff -Nur u-boot-1.1.4/include/asm-avr32/system.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/system.h --- u-boot-1.1.4/include/asm-avr32/system.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/system.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_SYSTEM_H +#define __ASM_AVR32_SYSTEM_H + +#include + +#define xchg(ptr,x) \ + ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) + +#define nop() __asm__ __volatile__ ("nop") + +#define mb() __asm__ __volatile__ ("" : : : "memory") +#define rmb() mb() +#define wmb() mb() +#define read_barrier_depends() do { } while(0) +#define set_mb(var, value) do { var = value; mb(); } while(0) +#define set_wmb(var, value) do { var = value; wmb(); } while(0) + +/* + * switch_to(prev, next, last) should switch from task `prev' to task + * `next'. `prev' will never be the same as `next'. + * + * We just delegate everything to the __switch_to assembly function, + * which is implemented in arch/avr32/kernel/switch_to.S + * + * mb() tells GCC not to cache `current' across this call. + */ +struct thread_struct; +struct task_struct; +extern struct task_struct *__switch_to(struct task_struct *, + struct thread_struct *, + struct thread_struct *); +#define switch_to(prev, next, last) \ + do { \ + last = __switch_to(prev, &prev->thread + 1, &next->thread); \ + mb(); \ + } while (0) + +#ifdef CONFIG_SMP +# error "The AVR32 port does not support SMP" +#else +# define smp_mb() barrier() +# define smp_rmb() barrier() +# define smp_wmb() barrier() +# define smp_read_barrier_depends() do { } while(0) +#endif + +/* Interrupt Control */ +#define AVR32_SYSREG_SR 0 +#define AVR32_SR_GM 16 + +#define local_irq_enable() \ + __asm__ __volatile__ ("csrf %0" : : "n"(AVR32_SR_GM) : "memory") +#define local_irq_disable() \ + __asm__ __volatile__ ("ssrf %0" : : "n"(AVR32_SR_GM) : "memory") +/* FIXME: Using a temporary volatile variable should be unnecessary, but + * gcc chokes without it. */ +#define local_save_flags(x) \ + do { \ + volatile __typeof__(x) __tmp; \ + __asm__ __volatile__ ("mfsr %0, 0" : "=r"(__tmp)); \ + x = __tmp; \ + } while(0) +#define irqs_disabled() \ + ({ \ + unsigned long flags; \ + local_save_flags(flags); \ + ((flags & (1UL << AVR32_SR_GM)) != 0); \ + }) + +/* XXX: Will restore ALL status register flags, not only interrupt mask. + * FIXME: Using a temporary volatile variable should be unnecessary, but + * gcc chokes without it. */ +#define local_irq_restore(x) \ + do { \ + volatile __typeof__(x) __tmp = x; \ + __asm__ __volatile__ ("mtsr 0, %0" \ + : \ + : "r"(__tmp) \ + : "memory", "cc"); \ + } while(0) +#define local_irq_save(flags) \ + do { \ + local_save_flags(flags); \ + local_irq_disable(); \ + } while(0) + +extern void __xchg_called_with_bad_pointer(void); + +static __inline__ unsigned long xchg_u32(unsigned long val, volatile int *m) +{ + unsigned long retval; + + __asm__("xchg %0, %1, %2" : "=r"(retval) : "r"(m), "r"(val)); + return retval; +} + +static __inline__ unsigned long __xchg(unsigned long x, + volatile void *ptr, + int size) +{ + switch(size) { + case 4: + return xchg_u32(x, ptr); + break; + /* case 1: + return xchg_u8(x, ptr); + break; */ + } + __xchg_called_with_bad_pointer(); + return x; +} + +#define die(msg, regs) \ + __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__) +#define die_if_kernel(msg, regs) \ + __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__) + +#endif /* __ASM_AVR32_SYSTEM_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/types.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/types.h --- u-boot-1.1.4/include/asm-avr32/types.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/types.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_TYPES_H +#define __ASM_AVR32_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +#endif /* __ASSEMBLY__ */ + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +#define BITS_PER_LONG 32 + +#ifndef __ASSEMBLY__ + +typedef __signed__ char s8; +typedef unsigned char u8; + +typedef __signed__ short s16; +typedef unsigned short u16; + +typedef __signed__ int s32; +typedef unsigned int u32; + +typedef __signed__ long long s64; +typedef unsigned long long u64; + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#ifdef CONFIG_LBD +typedef u64 sector_t; +#define HAVE_SECTOR_T +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + + +#endif /* __ASM_AVR32_TYPES_H */ diff -Nur u-boot-1.1.4/include/asm-avr32/u-boot.h u-boot-1.1.4-avr32-20060621/include/asm-avr32/u-boot.h --- u-boot-1.1.4/include/asm-avr32/u-boot.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/asm-avr32/u-boot.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_U_BOOT_H__ +#define __ASM_U_BOOT_H__ 1 + +typedef struct bd_info { + unsigned long bi_baudrate; + unsigned long bi_ip_addr; + unsigned char bi_enetaddr[6]; + unsigned char bi_phy_id[4]; + struct environment_s *bi_env; + unsigned long bi_board_number; + void *bi_boot_params; + struct { + unsigned long start; + unsigned long size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; + unsigned long bi_flashstart; + unsigned long bi_flashsize; + unsigned long bi_flashoffset; +} bd_t; + +#define bi_memstart bi_dram[0].start +#define bi_memsize bi_dram[0].size + +/** + * container_of - cast a member of a structure out to the containing structure + * + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#endif /* __ASM_U_BOOT_H__ */ diff -Nur u-boot-1.1.4/include/configs/atstk1002.h u-boot-1.1.4-avr32-20060621/include/configs/atstk1002.h --- u-boot-1.1.4/include/configs/atstk1002.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/configs/atstk1002.h 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Configuration settings for the ATSTK1002 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP7XXX 1 +#define CONFIG_AP7000 1 +#define CONFIG_ATSTK1002 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + gd->cpu_hz; \ + }) + +/* + * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL + * frequency and the peripherals to run at 1/4 the PLL frequency. + */ +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_AHB 1 +#define CFG_CLKDIV_APBA 2 +#define CFG_CLKDIV_APBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CFG_USART1 1 +#define CFG_MMCI 1 +#define CFG_MACB0 1 +#define CFG_MACB1 1 + +#define CFG_CONSOLE_UART_DEV DEVICE_USART1 + +/* User serviceable stuff */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyUS0 root=/dev/mmcblk0p1 fbmem=600k" +#define CONFIG_BOOTCOMMAND \ + "mmcinit; ext2load mmc 0:1 0x90400000 /uImage; bootm 0x90400000" + +#define CONFIG_BOOTDELAY 2 +#define CONFIG_AUTOBOOT 1 + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * These are "locally administered ethernet addresses" generated by + * ./tools/gen_eth_addr + * + * After booting the board for the first time, new addresses should be + * generated and assigned to the environment variables "ethaddr" and + * "eth1addr". + */ +#define CONFIG_ETHADDR "6a:87:71:14:cd:cb" +#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \ + | CONFIG_BOOTP_GATEWAY) + + +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_COMMANDS (CFG_CMD_BDI \ + /* | CFG_CMD_LOADS */ \ + /* | CFG_CMD_LOADB */ \ + /* | CFG_CMD_IMI */ \ + /* | CFG_CMD_CACHE */ \ + | CFG_CMD_FLASH \ + | CFG_CMD_MEMORY \ + | CFG_CMD_NET \ + | CFG_CMD_ENV \ + /* | CFG_CMD_IRQ */ \ + | CFG_CMD_BOOTD \ + | CFG_CMD_CONSOLE \ + /* | CFG_CMD_EEPROM */ \ + | CFG_CMD_ASKENV \ + | CFG_CMD_RUN \ + | CFG_CMD_ECHO \ + /* | CFG_CMD_I2C */ \ + | CFG_CMD_REGINFO \ + /* | CFG_CMD_DATE */ \ + | CFG_CMD_DHCP \ + /* | CFG_CMD_AUTOSCRIPT */ \ + /* | CFG_CMD_MII */ \ + | CFG_CMD_MISC \ + /* | CFG_CMD_SDRAM */ \ + /* | CFG_CMD_DIAG */ \ + /* | CFG_CMD_HWFLOW */ \ + /* | CFG_CMD_SAVES */ \ + /* | CFG_CMD_SPI */ \ + /* | CFG_CMD_PING */ \ + | CFG_CMD_MMC \ + /* | CFG_CMD_FAT */ \ + /* | CFG_CMD_IMLS */ \ + /* | CFG_CMD_ITEST */ \ + | CFG_CMD_EXT2 \ + ) + +#include + +#define CONFIG_USART3_SERIAL 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 + +#ifdef CONFIG_ATSTK1000 +# define CFG_HSDRAMC 1 +/* # define CONFIG_HARD_I2C 1 */ +# define CONFIG_MMC 1 +# define CONFIG_MACB 1 +#endif + +/* See comment in drivers/macb.c */ +#define CFG_RX_ETH_BUFFER 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +/* To be moved into atstk1000.h */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#ifdef CONFIG_ATSTK1000 +# define CFG_MALLOC_LEN (256*1024) +# define CFG_MALLOC_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + CFG_SDRAM_BASE + gd->sdram_size; \ + }) +# define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) + +# define CFG_DMA_ALLOC_LEN (16384) +# define CFG_DMA_ALLOC_END (CFG_MALLOC_START) +# define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) +/* Allow 2MB for the kernel run-time image */ +# define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) +# define CFG_BOOTPARAMS_LEN (16 * 1024) +#else +# define CFG_MALLOC_LEN (8*1024) +# define CFG_MALLOC_START ((CFG_INTRAM_BASE + CFG_ENV_SIZE) | 0x80000000) +# define CFG_MALLOC_END (CFG_MALLOC_START + CFG_MALLOC_LEN) +# define CFG_LOAD_ADDR (CFG_MALLOC_END) +#endif + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 8 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START \ + ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) +#define CFG_MEMTEST_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ + }) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ diff -Nur u-boot-1.1.4/include/image.h u-boot-1.1.4-avr32-20060621/include/image.h --- u-boot-1.1.4/include/image.h 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/image.h 2006-06-21 11:58:23.000000000 +0200 @@ -75,6 +75,7 @@ #define IH_CPU_NIOS 13 /* Nios-32 */ #define IH_CPU_MICROBLAZE 14 /* MicroBlaze */ #define IH_CPU_NIOS2 15 /* Nios-II */ +#define IH_CPU_AVR32 16 /* AVR32 */ /* * Image Types diff -Nur u-boot-1.1.4/include/linux/compiler-gcc2.h u-boot-1.1.4-avr32-20060621/include/linux/compiler-gcc2.h --- u-boot-1.1.4/include/linux/compiler-gcc2.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/linux/compiler-gcc2.h 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,24 @@ +/* Never include this file directly. Include instead. */ + +/* These definitions are for GCC v2.x. */ + +/* Somewhere in the middle of the GCC 2.96 development cycle, we implemented + a mechanism by which the user can annotate likely branch directions and + expect the blocks to be reordered appropriately. Define __builtin_expect + to nothing for earlier compilers. */ +#include + +#if __GNUC_MINOR__ < 96 +# define __builtin_expect(x, expected_value) (x) +#endif + +#define __attribute_used__ __attribute__((__unused__)) + +/* + * The attribute `pure' is not implemented in GCC versions earlier + * than 2.96. + */ +#if __GNUC_MINOR__ >= 96 +# define __attribute_pure__ __attribute__((pure)) +# define __attribute_const__ __attribute__((__const__)) +#endif diff -Nur u-boot-1.1.4/include/linux/compiler-gcc3.h u-boot-1.1.4-avr32-20060621/include/linux/compiler-gcc3.h --- u-boot-1.1.4/include/linux/compiler-gcc3.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/linux/compiler-gcc3.h 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,34 @@ +/* Never include this file directly. Include instead. */ + +/* These definitions are for GCC v3.x. */ +#include + +#if __GNUC_MINOR__ >= 1 +# define inline inline __attribute__((always_inline)) +# define __inline__ __inline__ __attribute__((always_inline)) +# define __inline __inline __attribute__((always_inline)) +#endif + +#if __GNUC_MINOR__ > 0 +# define __deprecated __attribute__((deprecated)) +#endif + +#if __GNUC_MINOR__ >= 3 +# define __attribute_used__ __attribute__((__used__)) +#else +# define __attribute_used__ __attribute__((__unused__)) +#endif + +#define __attribute_pure__ __attribute__((pure)) +#define __attribute_const__ __attribute__((__const__)) + +#if __GNUC_MINOR__ >= 1 +#define noinline __attribute__((noinline)) +#endif +#if __GNUC_MINOR__ >= 4 +#define __must_check __attribute__((warn_unused_result)) +#endif + +#if __GNUC_MINOR__ >= 5 +#define __compiler_offsetof(a,b) __builtin_offsetof(a,b) +#endif diff -Nur u-boot-1.1.4/include/linux/compiler-gcc.h u-boot-1.1.4-avr32-20060621/include/linux/compiler-gcc.h --- u-boot-1.1.4/include/linux/compiler-gcc.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/linux/compiler-gcc.h 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,17 @@ +/* Never include this file directly. Include instead. */ + +/* + * Common definitions for all gcc versions go here. + */ + + +/* Optimization barrier */ +/* The "volatile" is due to gcc bugs */ +#define barrier() __asm__ __volatile__("": : :"memory") + +/* This macro obfuscates arithmetic on a variable address so that gcc + shouldn't recognize the original var, and make assumptions about it */ +#define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __asm__ ("" : "=g"(__ptr) : "0"(ptr)); \ + (typeof(ptr)) (__ptr + (off)); }) diff -Nur u-boot-1.1.4/include/linux/compiler-gcc+.h u-boot-1.1.4-avr32-20060621/include/linux/compiler-gcc+.h --- u-boot-1.1.4/include/linux/compiler-gcc+.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/linux/compiler-gcc+.h 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,16 @@ +/* Never include this file directly. Include instead. */ + +/* + * These definitions are for Ueber-GCC: always newer than the latest + * version and hence sporting everything plus a kitchen-sink. + */ +#include + +#define inline inline __attribute__((always_inline)) +#define __inline__ __inline__ __attribute__((always_inline)) +#define __inline __inline __attribute__((always_inline)) +#define __deprecated __attribute__((deprecated)) +#define __attribute_used__ __attribute__((__used__)) +#define __attribute_pure__ __attribute__((pure)) +#define __attribute_const__ __attribute__((__const__)) +#define __must_check __attribute__((warn_unused_result)) diff -Nur u-boot-1.1.4/include/linux/compiler.h u-boot-1.1.4-avr32-20060621/include/linux/compiler.h --- u-boot-1.1.4/include/linux/compiler.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/linux/compiler.h 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,148 @@ +#ifndef __LINUX_COMPILER_H +#define __LINUX_COMPILER_H + +#ifndef __ASSEMBLY__ + +#ifdef __CHECKER__ +# define __user __attribute__((noderef, address_space(1))) +# define __kernel /* default address space */ +# define __safe __attribute__((safe)) +# define __force __attribute__((force)) +# define __iomem __attribute__((noderef, address_space(2))) +# define __acquires(x) __attribute__((context(0,1))) +# define __releases(x) __attribute__((context(1,0))) +# define __acquire(x) __context__(1) +# define __release(x) __context__(-1) +# define __cond_lock(x) ((x) ? ({ __context__(1); 1; }) : 0) +extern void __chk_user_ptr(void __user *); +extern void __chk_io_ptr(void __iomem *); +#else +# define __user +# define __kernel +# define __safe +# define __force +# define __iomem +# define __chk_user_ptr(x) (void)0 +# define __chk_io_ptr(x) (void)0 +# define __builtin_warning(x, y...) (1) +# define __acquires(x) +# define __releases(x) +# define __acquire(x) (void)0 +# define __release(x) (void)0 +# define __cond_lock(x) (x) +#endif + +#ifdef __KERNEL__ + +#if __GNUC__ > 3 +# include /* catch-all for GCC 4, 5, etc. */ +#elif __GNUC__ == 3 +# include +#elif __GNUC__ == 2 +# include +#else +# error Sorry, your compiler is too old/not recognized. +#endif + +/* Intel compiler defines __GNUC__. So we will overwrite implementations + * coming from above header files here + */ +#ifdef __INTEL_COMPILER +# include +#endif + +/* + * Generic compiler-dependent macros required for kernel + * build go below this comment. Actual compiler/compiler version + * specific implementations come from the above header files + */ + +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) + +/* Optimization barrier */ +#ifndef barrier +# define barrier() __memory_barrier() +#endif + +#ifndef RELOC_HIDE +# define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __ptr = (unsigned long) (ptr); \ + (typeof(ptr)) (__ptr + (off)); }) +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + +/* + * Allow us to mark functions as 'deprecated' and have gcc emit a nice + * warning for each use, in hopes of speeding the functions removal. + * Usage is: + * int __deprecated foo(void) + */ +#ifndef __deprecated +# define __deprecated /* unimplemented */ +#endif + +#ifndef __must_check +#define __must_check +#endif + +/* + * Allow us to avoid 'defined but not used' warnings on functions and data, + * as well as force them to be emitted to the assembly file. + * + * As of gcc 3.3, static functions that are not marked with attribute((used)) + * may be elided from the assembly file. As of gcc 3.3, static data not so + * marked will not be elided, but this may change in a future gcc version. + * + * In prior versions of gcc, such functions and data would be emitted, but + * would be warned about except with attribute((unused)). + */ +#ifndef __attribute_used__ +# define __attribute_used__ /* unimplemented */ +#endif + +/* + * From the GCC manual: + * + * Many functions have no effects except the return value and their + * return value depends only on the parameters and/or global + * variables. Such a function can be subject to common subexpression + * elimination and loop optimization just as an arithmetic operator + * would be. + * [...] + */ +#ifndef __attribute_pure__ +# define __attribute_pure__ /* unimplemented */ +#endif + +/* + * From the GCC manual: + * + * Many functions do not examine any values except their arguments, + * and have no effects except the return value. Basically this is + * just slightly more strict class than the `pure' attribute above, + * since function is not allowed to read global memory. + * + * Note that a function that has pointer arguments and examines the + * data pointed to must _not_ be declared `const'. Likewise, a + * function that calls a non-`const' function usually must not be + * `const'. It does not make sense for a `const' function to return + * `void'. + */ +#ifndef __attribute_const__ +# define __attribute_const__ /* unimplemented */ +#endif + +#ifndef noinline +#define noinline +#endif + +#ifndef __always_inline +#define __always_inline inline +#endif + +#endif /* __LINUX_COMPILER_H */ diff -Nur u-boot-1.1.4/include/linux/compiler-intel.h u-boot-1.1.4-avr32-20060621/include/linux/compiler-intel.h --- u-boot-1.1.4/include/linux/compiler-intel.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/linux/compiler-intel.h 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,24 @@ +/* Never include this file directly. Include instead. */ + +#ifdef __ECC + +/* Some compiler specific definitions are overwritten here + * for Intel ECC compiler + */ + +#include + +/* Intel ECC compiler doesn't support gcc specific asm stmts. + * It uses intrinsics to do the equivalent things. + */ +#undef barrier +#undef RELOC_HIDE + +#define barrier() __memory_barrier() + +#define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __ptr = (unsigned long) (ptr); \ + (typeof(ptr)) (__ptr + (off)); }) + +#endif diff -Nur u-boot-1.1.4/include/linux/mii.h u-boot-1.1.4-avr32-20060621/include/linux/mii.h --- u-boot-1.1.4/include/linux/mii.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/include/linux/mii.h 2006-06-21 11:58:26.000000000 +0200 @@ -0,0 +1,158 @@ +/* + * linux/mii.h: definitions for MII-compatible transceivers + * Originally drivers/net/sunhme.h. + * + * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) + */ + +#ifndef __LINUX_MII_H__ +#define __LINUX_MII_H__ + +/* Generic MII registers. */ + +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x07c0 /* Unused... */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_RESV 0x1c00 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* Link partner ability register. */ +#define LPA_SLCT 0x001f /* Same as advertise selector */ +#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ +#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ +#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ +#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ +#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ +#define LPA_RESV 0x1c00 /* Unused... */ +#define LPA_RFAULT 0x2000 /* Link partner faulted */ +#define LPA_LPACK 0x4000 /* Link partner acked us */ +#define LPA_NPAGE 0x8000 /* Next page bit */ + +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) + +/* Expansion register for auto-negotiation. */ +#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ +#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ +#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ +#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ +#define EXPANSION_RESV 0xffe0 /* Unused... */ + +/* N-way test register. */ +#define NWAYTEST_RESV1 0x00ff /* Unused... */ +#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ +#define NWAYTEST_RESV2 0xfe00 /* Unused... */ + + +/** + * mii_nway_result + * @negotiated: value of MII ANAR and'd with ANLPAR + * + * Given a set of MII abilities, check each bit and returns the + * currently supported media, in the priority order defined by + * IEEE 802.3u. We use LPA_xxx constants but note this is not the + * value of LPA solely, as described above. + * + * The one exception to IEEE 802.3u is that 100baseT4 is placed + * between 100T-full and 100T-half. If your phy does not support + * 100T4 this is fine. If your phy places 100T4 elsewhere in the + * priority order, you will need to roll your own function. + */ +static inline unsigned int mii_nway_result (unsigned int negotiated) +{ + unsigned int ret; + + if (negotiated & LPA_100FULL) + ret = LPA_100FULL; + else if (negotiated & LPA_100BASE4) + ret = LPA_100BASE4; + else if (negotiated & LPA_100HALF) + ret = LPA_100HALF; + else if (negotiated & LPA_10FULL) + ret = LPA_10FULL; + else + ret = LPA_10HALF; + + return ret; +} + +/** + * mii_duplex + * @duplex_lock: Non-zero if duplex is locked at full + * @negotiated: value of MII ANAR and'd with ANLPAR + * + * A small helper function for a common case. Returns one + * if the media is operating or locked at full duplex, and + * returns zero otherwise. + */ +static inline unsigned int mii_duplex (unsigned int duplex_lock, + unsigned int negotiated) +{ + if (duplex_lock) + return 1; + if (mii_nway_result(negotiated) & LPA_DUPLEX) + return 1; + return 0; +} + + +#endif /* __LINUX_MII_H__ */ diff -Nur u-boot-1.1.4/lib_avr32/avr32_linux.c u-boot-1.1.4-avr32-20060621/lib_avr32/avr32_linux.c --- u-boot-1.1.4/lib_avr32/avr32_linux.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/lib_avr32/avr32_linux.c 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include + +#include "tagtable.h" + +extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* CPU-specific hook to allow flushing of caches, etc. */ +extern void prepare_to_boot(void); + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +extern image_header_t header; /* from cmd_bootm.c */ + +extern char _start, _end; + +void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + unsigned long addr, unsigned long *len_ptr, int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned long data, len = 0; + unsigned long initrd_start, initrd_end; + unsigned long image_start, image_end; + unsigned long checksum; + void (*theKernel)(int magic, void *tagtable); + image_header_t *hdr; + struct tag *params, *params_start; + char *commandline = getenv("bootargs"); + + hdr = (image_header_t *)addr; + image_start = addr; + image_end = addr + hdr->ih_size; + + theKernel = (void *)ntohl(hdr->ih_ep); + + /* + * Check if there is an initrd image + */ + if (argc >= 3) { + SHOW_BOOT_PROGRESS(9); + + addr = simple_strtoul(argv[2], NULL, 16); + + printf("## Loading RAMDISK image at %08lx ...\n", addr); + + memcpy(&header, (char *)addr, sizeof(header)); + hdr = &header; + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS(-10); + do_reset(cmdtp, flag, argc, argv); + } + + data = (unsigned long)hdr; + len = sizeof(*hdr); + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32(0, (char *)data, len) != checksum) { + puts("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS(-11); + do_reset(cmdtp, flag, argc, argv); + } + + SHOW_BOOT_PROGRESS(10); + + print_image_hdr(hdr); + + data = addr + sizeof(header); + len = ntohl(hdr->ih_size); + + if (verify) { + unsigned long csum = 0; + + puts(" Verifying Checksum ... "); + csum = crc32(0, (char *)data, len); + if (csum != ntohl(hdr->ih_dcrc)) { + puts("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS(-12); + do_reset(cmdtp, flag, argc, argv); + } + puts("OK\n"); + } + + SHOW_BOOT_PROGRESS(11); + + if ((hdr->ih_os != IH_OS_LINUX) || + (hdr->ih_arch != IH_CPU_AVR32) || + (hdr->ih_type != IH_TYPE_RAMDISK)) { + puts("Not a Linux/AVR32 RAMDISK image\n"); + SHOW_BOOT_PROGRESS(-13); + do_reset(cmdtp, flag, argc, argv); + } + } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { + ulong tail = ntohl (len_ptr[0]) % 4; + int i; + + SHOW_BOOT_PROGRESS (13); + + /* skip kernel length and terminator */ + data = (ulong) (&len_ptr[2]); + /* skip any additional image length fields */ + for (i = 1; len_ptr[i]; ++i) + data += 4; + /* add kernel length, and align */ + data += ntohl (len_ptr[0]); + if (tail) { + data += 4 - tail; + } + + len = ntohl (len_ptr[1]); + } else { + /* no initrd image */ + SHOW_BOOT_PROGRESS(14); + len = data = 0; + } + + if (data) { + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = 0; + initrd_end = 0; + } + + SHOW_BOOT_PROGRESS(15); + + params = params_start = (struct tag *)gd->bd->bi_boot_params; + params = setup_start_tag(params); + params = setup_memory_tags(params); + if (initrd_start) { + params = setup_ramdisk_tag(params, + PHYSADDR(initrd_start), + PHYSADDR(initrd_end)); + } + params = setup_commandline_tag(params, commandline); + params = setup_clock_tags(params); + params = setup_ethernet_tags(params); + setup_end_tag(params); + + printf("\nStarting kernel at %p (params at %p)...\n\n", + theKernel, params_start); + + prepare_to_boot(); + + theKernel(ATAG_MAGIC, params_start); +} diff -Nur u-boot-1.1.4/lib_avr32/board.c u-boot-1.1.4-avr32-20060621/lib_avr32/board.c --- u-boot-1.1.4/lib_avr32/board.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/lib_avr32/board.c 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +const char version_string[] = + U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ") " CONFIG_IDENT_STRING; + +unsigned long monitor_flash_len; + +/* + * Begin and end of memory area for malloc(), and current "brk" + */ +static unsigned long mem_malloc_start = 0; +static unsigned long mem_malloc_end = 0; +static unsigned long mem_malloc_brk = 0; + +/* The malloc area is wherever the board wants it to be */ +static void mem_malloc_init(void) +{ + mem_malloc_start = CFG_MALLOC_START; + mem_malloc_end = CFG_MALLOC_END; + mem_malloc_brk = mem_malloc_start; + + printf("malloc: Using memory from 0x%08lx to 0x%08lx\n", + mem_malloc_start, mem_malloc_end); + + memset ((void *)mem_malloc_start, 0, + mem_malloc_end - mem_malloc_start); +} + +void *sbrk(ptrdiff_t increment) +{ + unsigned long old = mem_malloc_brk; + unsigned long new = old + increment; + + if ((new < mem_malloc_start) || (new > mem_malloc_end)) + return NULL; + + mem_malloc_brk = new; + return ((void *)old); +} + +static int init_baudrate(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned char tmp[64]; + int i; + + i = getenv_r("baudrate", tmp, sizeof(tmp)); + if (i > 0) { + gd->baudrate = simple_strtoul(tmp, NULL, 10); + } else { + gd->baudrate = CONFIG_BAUDRATE; + } + return 0; +} + + +static int display_banner (void) +{ + printf ("\n\n%s\n\n", version_string); + printf ("U-Boot code: %p -> %p data: %p -> %p\n", + _text, _etext, _data, _end); + return 0; +} + +void hang(void) +{ + for (;;) ; +} + +static int display_dram_config (void) +{ + DECLARE_GLOBAL_DATA_PTR; + int i; + + puts ("DRAM Configuration:\n"); + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); + print_size (gd->bd->bi_dram[i].size, "\n"); + } + + return 0; +} + +static void display_flash_config (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + puts ("Flash: "); + print_size(gd->bd->bi_flashsize, " "); + printf("at address 0x%08lx\n", gd->bd->bi_flashstart); +} + +void start_u_boot (void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd_t gd_data; + + /* Initialize the global data pointer */ + memset(&gd_data, 0, sizeof(gd_data)); + gd = &gd_data; + + /* Argh...gcc doesn't put gd in r5 even though we + * _specifically_ told it to. What's even more amazing is that + * gcc actually expects gd to magically show up in r5 + * anyway. Workaround time... */ + asm volatile("mov r5, %0" : : "r"(&gd_data)); + + monitor_flash_len = _edata - _text; + + /* Perform initialization sequence */ + cpu_init(); + timer_init(); + env_init(); + init_baudrate(); + serial_init(); + console_init_f(); + display_banner(); + + board_init_memories(); + mem_malloc_init(); + dma_mem_init(); + + gd->bd = malloc(sizeof(bd_t)); + memset(gd->bd, 0, sizeof(bd_t)); + gd->bd->bi_baudrate = gd->baudrate; + gd->bd->bi_dram[0].start = CFG_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->sdram_size; + + board_init_info(); + flash_init(); + + if (gd->bd->bi_flashsize) + display_flash_config(); + if (gd->bd->bi_dram[0].size) + display_dram_config(); + + gd->bd->bi_boot_params = malloc(CFG_BOOTPARAMS_LEN); + if (!gd->bd->bi_boot_params) + puts("WARNING: Cannot allocate space for boot parameters\n"); + + /* initialize environment */ + env_relocate(); + + devices_init(); + jumptable_init(); + console_init_r(); + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + net_init(); +# ifdef CONFIG_NET_MULTI + puts("Net: "); + eth_initialize(gd->bd); +# endif +#endif + + for (;;) { + main_loop(); + } +} diff -Nur u-boot-1.1.4/lib_avr32/cache.c u-boot-1.1.4-avr32-20060621/lib_avr32/cache.c --- u-boot-1.1.4/lib_avr32/cache.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/lib_avr32/cache.c 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* for now: just dummy functions to satisfy the linker */ + +void flush_cache (unsigned long dummy1, unsigned long dummy2) +{ + return; +} diff -Nur u-boot-1.1.4/lib_avr32/dma-alloc.c u-boot-1.1.4-avr32-20060621/lib_avr32/dma-alloc.c --- u-boot-1.1.4/lib_avr32/dma-alloc.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/lib_avr32/dma-alloc.c 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CFG_DMA_ALLOC_START +#include + +static unsigned long dma_alloc_brk; + +void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + unsigned long paddr = dma_alloc_brk; + + if (dma_alloc_brk + len > CFG_DMA_ALLOC_START + CFG_DMA_ALLOC_LEN) + return NULL; + + dma_alloc_brk = ((paddr + len + CFG_DCACHE_LINESZ - 1) + & ~(CFG_DCACHE_LINESZ - 1)); + + *handle = paddr; + return uncached(paddr); +} + +void dma_mem_init(void) +{ + dma_alloc_brk = CFG_DMA_ALLOC_START; + + dcache_invalidate_range(cached(CFG_DMA_ALLOC_START), + CFG_DMA_ALLOC_LEN); +} + +#endif /* CFG_DMA_ALLOC_START */ diff -Nur u-boot-1.1.4/lib_avr32/Makefile u-boot-1.1.4-avr32-20060621/lib_avr32/Makefile --- u-boot-1.1.4/lib_avr32/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/lib_avr32/Makefile 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,46 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2004-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = memset.o + +COBJS = board.o time.o avr32_linux.o cache.o dma-alloc.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff -Nur u-boot-1.1.4/lib_avr32/memset.S u-boot-1.1.4-avr32-20060621/lib_avr32/memset.S --- u-boot-1.1.4/lib_avr32/memset.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/lib_avr32/memset.S 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + /* + * r12: void *b + * r11: int c + * r10: size_t len + * + * Returns b in r12 + */ + .text + + /* We should be 32-byte aligned at this point */ + .global memset + .type memset, @function + .align 5 +memset: + mov r9, r12 + mov r8, r12 + or r11, r11, r11 << 8 + andl r9, 3, COH + brne 1f + +2: or r11, r11, r11 << 16 + sub r10, 4 + brlt 5f + + /* Let's do some real work */ +4: st.w r8++, r11 + sub r10, 4 + brge 4b + + /* + * When we get here, we've got less than 4 bytes to set. r10 + * might be negative. + */ +5: sub r10, -4 + reteq r12 + + /* Fastpath ends here, exactly 32 bytes from memset */ + + /* Handle unaligned count or pointer */ + bld r10, 1 + brcc 6f + st.b r8++, r11 + st.b r8++, r11 + bld r10, 0 + retcc r12 +6: st.b r8++, r11 + mov pc, lr + + /* Handle unaligned pointer */ +1: sub r10, 4 + brlt 5b + add r10, r9 + lsl r9, 1 + add pc, r9 + st.b r8++, r11 + st.b r8++, r11 + st.b r8++, r11 + rjmp 2b + + .size memset, . - memset diff -Nur u-boot-1.1.4/lib_avr32/tagtable.h u-boot-1.1.4-avr32-20060621/lib_avr32/tagtable.h --- u-boot-1.1.4/lib_avr32/tagtable.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/lib_avr32/tagtable.h 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __AVR32_TAGTABLE_H +#define __AVR32_TAGTABLE_H + +#include +#include + +static inline struct tag *setup_start_tag(struct tag *params) +{ + params->hdr.tag = ATAG_CORE; + params->hdr.size = tag_size(tag_core); + + params->u.core.flags = 0; + params->u.core.pagesize = 4096; + params->u.core.rootdev = 0; + + return tag_next(params); +} + +static inline struct tag *setup_memory_tags(struct tag *params) +{ + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + params->hdr.tag = ATAG_MEM; + params->hdr.size = tag_size(tag_mem_range); + + params->u.mem_range.addr = bd->bi_dram[i].start; + params->u.mem_range.size = bd->bi_dram[i].size; + + params = tag_next(params); + } + + return params; +} + +static inline struct tag *setup_commandline_tag(struct tag *params, + char *cmdline) +{ + if (!cmdline) + return params; + + /* eat leading white space */ + while (*cmdline == ' ') cmdline++; + + /* + * Don't include tags for empty command lines; let the kernel + * use its default command line. + */ + if (*cmdline == '\0') + return params; + + params->hdr.tag = ATAG_CMDLINE; + params->hdr.size = + (sizeof (struct tag_header) + strlen(cmdline) + 1 + 3) >> 2; + strcpy(params->u.cmdline.cmdline, cmdline); + + return tag_next(params); +} + +static inline struct tag *setup_ramdisk_tag(struct tag *params, + unsigned long rd_start, + unsigned long rd_end) +{ + if (rd_start == rd_end) + return params; + + params->hdr.tag = ATAG_RDIMG; + params->hdr.size = tag_size(tag_mem_range); + + params->u.mem_range.addr = rd_start; + params->u.mem_range.size = rd_end - rd_start; + + return tag_next(params); +} + +static inline struct tag *setup_clock_tags(struct tag *params) +{ + DECLARE_GLOBAL_DATA_PTR; + + params->hdr.tag = ATAG_CLOCK; + params->hdr.size = tag_size(tag_clock); + params->u.clock.clock_id = CLOCK_BOOTCPU; + params->u.clock.clock_flags = 0; + params->u.clock.clock_hz = gd->cpu_hz; + + params = tag_next(params); + + params->hdr.tag = ATAG_CLOCK; + params->hdr.size = tag_size(tag_clock); + params->u.clock.clock_id = CLOCK_AMBA; + params->u.clock.clock_flags = 0; + params->u.clock.clock_hz = pm_get_clock_freq(CLOCK_AHB); + + return tag_next(params); +} + +static inline struct tag *setup_reserved_tag(struct tag *params, + unsigned long start, + unsigned long end) +{ + params->hdr.tag = ATAG_RSVD_MEM; + params->hdr.size = tag_size(tag_mem_range); + + params->u.mem_range.addr = start; + params->u.mem_range.size = end - start; + + return tag_next(params); +} + +static inline struct tag *setup_ethernet_tag(struct tag *params, + char *addr, int index) +{ + DECLARE_GLOBAL_DATA_PTR; + char *s, *e; + int i; + + params->hdr.tag = ATAG_ETHERNET; + params->hdr.size = tag_size(tag_ethernet); + + params->u.ethernet.mac_index = index; + params->u.ethernet.mii_phy_addr = gd->bd->bi_phy_id[index]; + + s = addr; + for (i = 0; i < 6; i++) { + params->u.ethernet.hw_address[i] = simple_strtoul(s, &e, 16); + s = e + 1; + } + + return tag_next(params); +} + +static inline struct tag *setup_ethernet_tags(struct tag *params) +{ + char name[16] = "ethaddr"; + char *addr; + int i = 0; + + do { + addr = getenv(name); + if (addr) + params = setup_ethernet_tag(params, addr, i); + sprintf(name, "eth%daddr", ++i); + } while (i < 4); + + return params; +} + +static inline void setup_end_tag(struct tag *params) +{ + params->hdr.tag = ATAG_NONE; + params->hdr.size = 0; +} + +#endif /* __AVR32_TAGTABLE_H */ diff -Nur u-boot-1.1.4/lib_avr32/time.c u-boot-1.1.4-avr32-20060621/lib_avr32/time.c --- u-boot-1.1.4/lib_avr32/time.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/lib_avr32/time.c 2006-06-21 11:58:23.000000000 +0200 @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +static inline void set_compare(u32 val) +{ + sysreg_write(SYSREG_COMPARE, val); +} + +static inline void set_count(u32 val) +{ + sysreg_write(SYSREG_COUNT, val); +} + +static inline u32 get_count(void) +{ + return sysreg_read(SYSREG_COUNT); +} + +int timer_init(void) +{ + set_compare(0); + set_count(0); + return 0; +} + +void reset_timer(void) +{ + set_count(0); +} + +unsigned long get_timer(unsigned long base) +{ + return get_count() - base; +} + +void set_timer(unsigned long t) +{ + set_count(t); +} + +void udelay(unsigned long usec) +{ + unsigned long start, stop; + unsigned long ticks; + + start = get_count(); + ticks = usec * (CFG_HZ / 1000000); + stop = start + ticks; + + if (start > stop) + while (get_count() > start) ; + + while (get_count() < stop) ; +} + +unsigned long long get_ticks(void) +{ + return get_count(); +} + +unsigned long get_tbclk(void) +{ + return CFG_HZ; +} diff -Nur u-boot-1.1.4/Makefile u-boot-1.1.4-avr32-20060621/Makefile --- u-boot-1.1.4/Makefile 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/Makefile 2006-06-21 11:58:25.000000000 +0200 @@ -49,6 +49,10 @@ # load other configuration include $(TOPDIR)/config.mk +ifeq ($(ARCH),avr32) +CROSS_COMPILE = avr32- +endif + ifndef CROSS_COMPILE ifeq ($(HOSTARCH),ppc) CROSS_COMPILE = @@ -130,15 +134,20 @@ # The "tools" are needed early, so put this first # Don't include stuff already done in $(LIBS) SUBDIRS = tools \ - examples \ + #examples \ post \ post/cpu .PHONY : $(SUBDIRS) +ifeq ($(ARCH),avr32) +%.lds: %.lds.S + $(MAKE) -C $(dir $@) $(notdir $@) +endif + ######################################################################### ######################################################################### -ALL = u-boot.srec u-boot.bin System.map +ALL = u-boot.elf u-boot.srec u-boot.bin System.map all: $(ALL) @@ -151,6 +160,9 @@ u-boot.bin: u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ +u-boot.elf: u-boot + $(OBJCOPY) ${OBJCFLAGS} $< $@ + u-boot.img: u-boot.bin ./tools/mkimage -A $(ARCH) -T firmware -C none \ -a $(TEXT_BASE) -e 0 \ @@ -161,7 +173,7 @@ u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ -u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) +u-boot: depend $(LDSCRIPT) $(SUBDIRS) $(OBJS) $(LIBS) UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \ --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \ @@ -1812,6 +1824,16 @@ @echo "#define CONFIG_SUZAKU 1" >> include/config.h @./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno +#======================================================================== +# AVR32 +#======================================================================== +######################################################################### +## AT32AP7xxx +######################################################################### + +atstk1002_config : unconfig + @./mkconfig $(@:_config=) avr32 at32ap7xxx atstk1000 NULL ap7000 + ######################################################################### ######################################################################### diff -Nur u-boot-1.1.4/net/bootp.c u-boot-1.1.4-avr32-20060621/net/bootp.c --- u-boot-1.1.4/net/bootp.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/net/bootp.c 2006-06-21 11:58:26.000000000 +0200 @@ -820,10 +820,7 @@ bp->bp_hlen = HWL_ETHER; bp->bp_hops = 0; bp->bp_secs = htons(get_timer(0) / CFG_HZ); - NetCopyIP(&bp->bp_ciaddr, &bp_offer->bp_ciaddr); /* both in network byte order */ - NetCopyIP(&bp->bp_yiaddr, &bp_offer->bp_yiaddr); - NetCopyIP(&bp->bp_siaddr, &bp_offer->bp_siaddr); - NetCopyIP(&bp->bp_giaddr, &bp_offer->bp_giaddr); + NetCopyIP(&bp->bp_ciaddr, &bp_offer->bp_yiaddr); memcpy (bp->bp_chaddr, NetOurEther, 6); /* diff -Nur u-boot-1.1.4/net/eth.c u-boot-1.1.4-avr32-20060621/net/eth.c --- u-boot-1.1.4/net/eth.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/net/eth.c 2006-06-21 11:58:25.000000000 +0200 @@ -53,6 +53,7 @@ extern int scc_initialize(bd_t*); extern int skge_initialize(bd_t*); extern int tsec_initialize(bd_t*, int, char *); +extern int atstk1000_eth_initialize(bd_t *); static struct eth_device *eth_devices, *eth_current; @@ -231,6 +232,9 @@ #if defined(CONFIG_RTL8169) rtl8169_initialize(bis); #endif +#if defined(CONFIG_ATSTK1000) + atstk1000_eth_initialize(bis); +#endif if (!eth_devices) { puts ("No ethernet found.\n"); diff -Nur u-boot-1.1.4/net/net.c u-boot-1.1.4-avr32-20060621/net/net.c --- u-boot-1.1.4/net/net.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/net/net.c 2006-06-21 11:58:26.000000000 +0200 @@ -168,7 +168,7 @@ int nc_input_packet(uchar *pkt, unsigned dest, unsigned src, unsigned len); #endif -volatile uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN]; +volatile uchar *PktBuf; volatile uchar *NetRxPackets[PKTBUFSRX]; /* Receive packets */ @@ -191,6 +191,11 @@ ulong NetArpWaitTimerStart; int NetArpWaitTry; +void net_init(void) +{ + PktBuf = malloc((PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN); +} + void ArpRequest (void) { int i; diff -Nur u-boot-1.1.4/net/tftp.c u-boot-1.1.4-avr32-20060621/net/tftp.c --- u-boot-1.1.4/net/tftp.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/net/tftp.c 2006-06-21 11:58:26.000000000 +0200 @@ -35,6 +35,7 @@ #define TFTP_OACK 6 +static IPaddr_t TftpServerIP; /* The IP of the TFTP server */ static int TftpServerPort; /* The UDP port at their end */ static int TftpOurPort; /* The UDP port at our end */ static int TftpTimeoutCount; @@ -168,7 +169,7 @@ break; } - NetSendUDPPacket(NetServerEther, NetServerIP, TftpServerPort, TftpOurPort, len); + NetSendUDPPacket(NetServerEther, TftpServerIP, TftpServerPort, TftpOurPort, len); } @@ -331,16 +332,21 @@ tftp_filename = BootFile; } + /* Allow environment to override the TFTP server address */ + TftpServerIP = getenv_IPaddr("tftpip"); + if (!TftpServerIP) + NetCopyIP(&TftpServerIP, &NetServerIP); + #if defined(CONFIG_NET_MULTI) printf ("Using %s device\n", eth_get_name()); #endif - puts ("TFTP from server "); print_IPaddr (NetServerIP); + puts ("TFTP from server "); print_IPaddr (TftpServerIP); puts ("; our IP address is "); print_IPaddr (NetOurIP); /* Check if we need to send across this subnet */ if (NetOurGatewayIP && NetOurSubnetMask) { IPaddr_t OurNet = NetOurIP & NetOurSubnetMask; - IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask; + IPaddr_t ServerNet = TftpServerIP & NetOurSubnetMask; if (OurNet != ServerNet) { puts ("; sending through gateway "); diff -Nur u-boot-1.1.4/tools/mkimage.c u-boot-1.1.4-avr32-20060621/tools/mkimage.c --- u-boot-1.1.4/tools/mkimage.c 2005-12-16 17:39:27.000000000 +0100 +++ u-boot-1.1.4-avr32-20060621/tools/mkimage.c 2006-06-21 11:58:23.000000000 +0200 @@ -93,6 +93,7 @@ { IH_CPU_SH, "sh", "SuperH", }, { IH_CPU_SPARC, "sparc", "SPARC", }, { IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", }, + { IH_CPU_AVR32, "avr32", "AVR32" }, { -1, "", "", }, };